1 /* $NetBSD: kfd_mqd_manager.c,v 1.3 2021/12/18 23:44:59 riastradh Exp $ */
2
3 /*
4 * Copyright 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: kfd_mqd_manager.c,v 1.3 2021/12/18 23:44:59 riastradh Exp $");
28
29 #include "kfd_mqd_manager.h"
30 #include "amdgpu_amdkfd.h"
31 #include "kfd_device_queue_manager.h"
32
33 /* Mapping queue priority to pipe priority, indexed by queue priority */
34 int pipe_priority_map[] = {
35 KFD_PIPE_PRIORITY_CS_LOW,
36 KFD_PIPE_PRIORITY_CS_LOW,
37 KFD_PIPE_PRIORITY_CS_LOW,
38 KFD_PIPE_PRIORITY_CS_LOW,
39 KFD_PIPE_PRIORITY_CS_LOW,
40 KFD_PIPE_PRIORITY_CS_LOW,
41 KFD_PIPE_PRIORITY_CS_LOW,
42 KFD_PIPE_PRIORITY_CS_MEDIUM,
43 KFD_PIPE_PRIORITY_CS_MEDIUM,
44 KFD_PIPE_PRIORITY_CS_MEDIUM,
45 KFD_PIPE_PRIORITY_CS_MEDIUM,
46 KFD_PIPE_PRIORITY_CS_HIGH,
47 KFD_PIPE_PRIORITY_CS_HIGH,
48 KFD_PIPE_PRIORITY_CS_HIGH,
49 KFD_PIPE_PRIORITY_CS_HIGH,
50 KFD_PIPE_PRIORITY_CS_HIGH
51 };
52
allocate_hiq_mqd(struct kfd_dev * dev,struct queue_properties * q)53 struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_dev *dev, struct queue_properties *q)
54 {
55 struct kfd_mem_obj *mqd_mem_obj = NULL;
56
57 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
58 if (!mqd_mem_obj)
59 return NULL;
60
61 mqd_mem_obj->gtt_mem = dev->dqm->hiq_sdma_mqd.gtt_mem;
62 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr;
63 mqd_mem_obj->cpu_ptr = dev->dqm->hiq_sdma_mqd.cpu_ptr;
64
65 return mqd_mem_obj;
66 }
67
allocate_sdma_mqd(struct kfd_dev * dev,struct queue_properties * q)68 struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_dev *dev,
69 struct queue_properties *q)
70 {
71 struct kfd_mem_obj *mqd_mem_obj = NULL;
72 uint64_t offset;
73
74 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
75 if (!mqd_mem_obj)
76 return NULL;
77
78 offset = (q->sdma_engine_id *
79 dev->device_info->num_sdma_queues_per_engine +
80 q->sdma_queue_id) *
81 dev->dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size;
82
83 offset += dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
84
85 mqd_mem_obj->gtt_mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.gtt_mem
86 + offset);
87 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset;
88 mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t)
89 dev->dqm->hiq_sdma_mqd.cpu_ptr + offset);
90
91 return mqd_mem_obj;
92 }
93
free_mqd_hiq_sdma(struct mqd_manager * mm,void * mqd,struct kfd_mem_obj * mqd_mem_obj)94 void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd,
95 struct kfd_mem_obj *mqd_mem_obj)
96 {
97 WARN_ON(!mqd_mem_obj->gtt_mem);
98 kfree(mqd_mem_obj);
99 }
100
mqd_symmetrically_map_cu_mask(struct mqd_manager * mm,const uint32_t * cu_mask,uint32_t cu_mask_count,uint32_t * se_mask)101 void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
102 const uint32_t *cu_mask, uint32_t cu_mask_count,
103 uint32_t *se_mask)
104 {
105 struct kfd_cu_info cu_info;
106 uint32_t cu_per_se[KFD_MAX_NUM_SE] = {0};
107 int i, se, sh, cu = 0;
108
109 amdgpu_amdkfd_get_cu_info(mm->dev->kgd, &cu_info);
110
111 if (cu_mask_count > cu_info.cu_active_number)
112 cu_mask_count = cu_info.cu_active_number;
113
114 for (se = 0; se < cu_info.num_shader_engines; se++)
115 for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)
116 cu_per_se[se] += hweight32(cu_info.cu_bitmap[se % 4][sh + (se / 4)]);
117
118 /* Symmetrically map cu_mask to all SEs:
119 * cu_mask[0] bit0 -> se_mask[0] bit0;
120 * cu_mask[0] bit1 -> se_mask[1] bit0;
121 * ... (if # SE is 4)
122 * cu_mask[0] bit4 -> se_mask[0] bit1;
123 * ...
124 */
125 se = 0;
126 for (i = 0; i < cu_mask_count; i++) {
127 if (cu_mask[i / 32] & (1 << (i % 32)))
128 se_mask[se] |= 1 << cu;
129
130 do {
131 se++;
132 if (se == cu_info.num_shader_engines) {
133 se = 0;
134 cu++;
135 }
136 } while (cu >= cu_per_se[se] && cu < 32);
137 }
138 }
139