1 /* $NetBSD: if_iwnreg.h,v 1.18 2021/06/17 02:05:47 msaitoh Exp $ */ 2 /* $OpenBSD: if_iwnreg.h,v 1.49 2014/09/09 18:56:24 sthen Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/endian.h> 22 23 /* XXX Added for NetBSD */ 24 #define IEEE80211_TKIP_MICLEN 8 25 26 #define IWN_TX_RING_COUNT 256 27 #define IWN_TX_RING_LOMARK 192 28 #define IWN_TX_RING_HIMARK 224 29 #define IWN_RX_RING_COUNT_LOG 6 30 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 31 32 #define IWN4965_NTXQUEUES 16 33 #define IWN5000_NTXQUEUES 20 34 35 #define IWN4965_NDMACHNLS 7 36 #define IWN5000_NDMACHNLS 8 37 38 #define IWN_SRVC_DMACHNL 9 39 40 #define IWN_ICT_SIZE 4096 41 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 42 43 /* Maximum number of DMA segments for TX. */ 44 #define IWN_MAX_SCATTER 20 45 46 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 47 #define IWN_RBUF_SIZE (4 * 1024) 48 49 #if defined(__LP64__) 50 /* HW supports 36-bit DMA addresses. */ 51 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 52 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 53 #else 54 #define IWN_LOADDR(paddr) (paddr) 55 #define IWN_HIADDR(paddr) (0) 56 #endif 57 58 /* Base Address Register. */ 59 #define IWN_PCI_BAR0 PCI_MAPREG_START 60 61 /* 62 * Control and status registers. 63 */ 64 #define IWN_HW_IF_CONFIG 0x000 65 #define IWN_INT_COALESCING 0x004 66 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 67 #define IWN_INT 0x008 68 #define IWN_INT_MASK 0x00c 69 #define IWN_FH_INT 0x010 70 #define IWN_RESET 0x020 71 #define IWN_GP_CNTRL 0x024 72 #define IWN_HW_REV 0x028 73 #define IWN_EEPROM 0x02c 74 #define IWN_EEPROM_GP 0x030 75 #define IWN_OTP_GP 0x034 76 #define IWN_GIO 0x03c 77 #define IWN_GP_DRIVER 0x050 78 #define IWN_UCODE_GP1_CLR 0x05c 79 #define IWN_LED 0x094 80 #define IWN_DRAM_INT_TBL 0x0a0 81 #define IWN_SHADOW_REG_CTRL 0x0a8 82 #define IWN_GIO_CHICKEN 0x100 83 #define IWN_ANA_PLL 0x20c 84 #define IWN_HW_REV_WA 0x22c 85 #define IWN_DBG_HPET_MEM 0x240 86 #define IWN_DBG_LINK_PWR_MGMT 0x250 87 #define IWN_MEM_RADDR 0x40c 88 #define IWN_MEM_WADDR 0x410 89 #define IWN_MEM_WDATA 0x418 90 #define IWN_MEM_RDATA 0x41c 91 #define IWN_PRPH_WADDR 0x444 92 #define IWN_PRPH_RADDR 0x448 93 #define IWN_PRPH_WDATA 0x44c 94 #define IWN_PRPH_RDATA 0x450 95 #define IWN_HBUS_TARG_WRPTR 0x460 96 97 /* 98 * Flow-Handler registers. 99 */ 100 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 101 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 102 #define IWN_FH_KW_ADDR 0x197c 103 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 104 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 105 #define IWN_FH_STATUS_WPTR 0x1bc0 106 #define IWN_FH_RX_BASE 0x1bc4 107 #define IWN_FH_RX_WPTR 0x1bc8 108 #define IWN_FH_RX_CONFIG 0x1c00 109 #define IWN_FH_RX_STATUS 0x1c44 110 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 111 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 112 #define IWN_FH_TX_CHICKEN 0x1e98 113 #define IWN_FH_TX_STATUS 0x1eb0 114 115 /* 116 * TX scheduler registers. 117 */ 118 #define IWN_SCHED_BASE 0xa02c00 119 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 120 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 121 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 122 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 123 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 124 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 125 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 126 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 127 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 128 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 129 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 130 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 131 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 132 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 133 134 /* 135 * Offsets in TX scheduler's SRAM. 136 */ 137 #define IWN4965_SCHED_CTX_OFF 0x380 138 #define IWN4965_SCHED_CTX_LEN 416 139 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 140 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 141 #define IWN5000_SCHED_CTX_OFF 0x600 142 #define IWN5000_SCHED_CTX_LEN 520 143 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 144 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 145 146 /* 147 * NIC internal memory offsets. 148 */ 149 #define IWN_APMG_CLK_CTRL 0x3000 150 #define IWN_APMG_CLK_EN 0x3004 151 #define IWN_APMG_CLK_DIS 0x3008 152 #define IWN_APMG_PS 0x300c 153 #define IWN_APMG_DIGITAL_SVR 0x3058 154 #define IWN_APMG_ANALOG_SVR 0x306c 155 #define IWN_APMG_PCI_STT 0x3010 156 #define IWN_BSM_WR_CTRL 0x3400 157 #define IWN_BSM_WR_MEM_SRC 0x3404 158 #define IWN_BSM_WR_MEM_DST 0x3408 159 #define IWN_BSM_WR_DWCOUNT 0x340c 160 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 161 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 162 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 163 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 164 #define IWN_BSM_SRAM_BASE 0x3800 165 166 /* Possible flags for register IWN_HW_IF_CONFIG. */ 167 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 168 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 169 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 170 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 171 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 172 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 173 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 174 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 175 176 /* Possible values for register IWN_INT_PERIODIC. */ 177 #define IWN_INT_PERIODIC_DIS 0x00 178 #define IWN_INT_PERIODIC_ENA 0xff 179 180 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 181 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 182 183 /* Possible values for IWN_BSM_WR_MEM_DST. */ 184 #define IWN_FW_TEXT_BASE 0x00000000 185 #define IWN_FW_DATA_BASE 0x00800000 186 187 /* Possible flags for register IWN_RESET. */ 188 #define IWN_RESET_NEVO (1U << 0) 189 #define IWN_RESET_SW (1U << 7) 190 #define IWN_RESET_MASTER_DISABLED (1U << 8) 191 #define IWN_RESET_STOP_MASTER (1U << 9) 192 #define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 193 194 /* Possible flags for register IWN_GP_CNTRL. */ 195 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 196 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 197 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 198 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 199 #define IWN_GP_CNTRL_SLEEP (1 << 4) 200 #define IWN_GP_CNTRL_RFKILL (1 << 27) 201 202 /* Possible flags for register IWN_HW_REV. */ 203 #define IWN_HW_REV_TYPE_SHIFT 4 204 #define IWN_HW_REV_TYPE_MASK 0x000001f0 205 #define IWN_HW_REV_TYPE_4965 0 206 #define IWN_HW_REV_TYPE_5300 2 207 #define IWN_HW_REV_TYPE_5350 3 208 #define IWN_HW_REV_TYPE_5150 4 209 #define IWN_HW_REV_TYPE_5100 5 210 #define IWN_HW_REV_TYPE_1000 6 211 #define IWN_HW_REV_TYPE_6000 7 212 #define IWN_HW_REV_TYPE_6050 8 213 #define IWN_HW_REV_TYPE_6005 11 214 /* Types 6030 and 6035 also return 11 */ 215 #define IWN_HW_REV_TYPE_2030 12 216 #define IWN_HW_REV_TYPE_2000 16 217 #define IWN_HW_REV_TYPE_105 17 218 #define IWN_HW_REV_TYPE_135 18 219 220 /* Possible flags for register IWN_GIO_CHICKEN. */ 221 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 222 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 223 224 /* Possible flags for register IWN_GIO. */ 225 #define IWN_GIO_L0S_ENA (1 << 1) 226 227 /* Possible flags for register IWN_GP_DRIVER. */ 228 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 229 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 230 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 231 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 232 #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 233 #define IWN_GP_DRIVER_RADIO_IQ_INVERT (1 << 7) 234 235 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 236 #define IWN_UCODE_GP1_RFKILL (1 << 1) 237 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 238 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 239 240 /* Possible flags/values for register IWN_LED. */ 241 #define IWN_LED_BSM_CTRL (1 << 5) 242 #define IWN_LED_OFF 0x00000038 243 #define IWN_LED_ON 0x00000078 244 245 /* Possible flags for register IWN_DRAM_INT_TBL. */ 246 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 247 #define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 248 249 /* Possible values for register IWN_ANA_PLL. */ 250 #define IWN_ANA_PLL_INIT 0x00880300 251 252 /* Possible flags for register IWN_FH_RX_STATUS. */ 253 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 254 255 /* Possible flags for register IWN_BSM_WR_CTRL. */ 256 #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 257 #define IWN_BSM_WR_CTRL_START (1 << 31) 258 259 /* Possible flags for register IWN_INT. */ 260 #define IWN_INT_ALIVE (1 << 0) 261 #define IWN_INT_WAKEUP (1 << 1) 262 #define IWN_INT_SW_RX (1 << 3) 263 #define IWN_INT_CT_REACHED (1 << 6) 264 #define IWN_INT_RF_TOGGLED (1 << 7) 265 #define IWN_INT_SW_ERR (1 << 25) 266 #define IWN_INT_SCHED (1 << 26) 267 #define IWN_INT_FH_TX (1 << 27) 268 #define IWN_INT_RX_PERIODIC (1 << 28) 269 #define IWN_INT_HW_ERR (1 << 29) 270 #define IWN_INT_FH_RX (1U << 31) 271 272 /* Shortcut. */ 273 #define IWN_INT_MASK_DEF \ 274 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 275 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 276 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 277 278 /* Possible flags for register IWN_FH_INT. */ 279 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 280 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 281 #define IWN_FH_INT_HI_PRIOR (1 << 30) 282 /* Shortcuts for the above. */ 283 #define IWN_FH_INT_TX \ 284 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 285 #define IWN_FH_INT_RX \ 286 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 287 288 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 289 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 290 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 291 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1U << 20) 292 293 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 294 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 295 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 296 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 297 298 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 299 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 300 301 /* Possible flags for register IWN_FH_TX_STATUS. */ 302 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 303 304 /* Possible flags for register IWN_FH_RX_CONFIG. */ 305 #define IWN_FH_RX_CONFIG_ENA (1U << 31) 306 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 307 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1U << 16) 308 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1U << 15) 309 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1U << 12) 310 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 311 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1U << 2) 312 313 /* Possible flags for register IWN_FH_TX_CONFIG. */ 314 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 315 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1U << 3) 316 317 /* Possible flags for register IWN_EEPROM. */ 318 #define IWN_EEPROM_READ_VALID (1 << 0) 319 #define IWN_EEPROM_CMD (1 << 1) 320 321 /* Possible flags for register IWN_EEPROM_GP. */ 322 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 323 324 /* Possible flags for register IWN_OTP_GP. */ 325 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 326 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 327 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 328 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 329 330 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 331 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 332 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 333 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 334 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 335 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 336 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 337 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 338 339 /* Possible flags for registers IWN_APMG_CLK_*. */ 340 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 341 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 342 343 /* Possible flags for register IWN_APMG_PS. */ 344 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 345 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 346 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 347 #define IWN_APMG_PS_PWR_SRC_VAUX 2 348 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 349 #define IWN_APMG_PS_RESET_REQ (1 << 26) 350 351 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 352 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 353 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 354 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 355 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 356 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 357 358 /* Possible flags for IWN_APMG_PCI_STT. */ 359 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 360 361 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 362 #define IWN_FW_UPDATED (1U << 31) 363 364 #define IWN_SCHED_WINSZ 64 365 #define IWN_SCHED_LIMIT 64 366 #define IWN4965_SCHED_COUNT 512 367 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 368 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 369 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 370 371 struct iwn_tx_desc { 372 uint8_t reserved1[3]; 373 uint8_t nsegs; 374 struct { 375 uint32_t addr; 376 uint16_t len; 377 } __packed segs[IWN_MAX_SCATTER]; 378 /* Pad to 128 bytes. */ 379 uint32_t reserved2; 380 } __packed; 381 382 struct iwn_rx_status { 383 uint16_t closed_count; 384 uint16_t closed_rx_count; 385 uint16_t finished_count; 386 uint16_t finished_rx_count; 387 uint32_t reserved[2]; 388 } __packed; 389 390 struct iwn_rx_desc { 391 uint32_t len; 392 uint8_t type; 393 #define IWN_UC_READY 1 394 #define IWN_ADD_NODE_DONE 24 395 #define IWN_TX_DONE 28 396 #define IWN5000_CALIBRATION_RESULT 102 397 #define IWN5000_CALIBRATION_DONE 103 398 #define IWN_START_SCAN 130 399 #define IWN_STOP_SCAN 132 400 #define IWN_RX_STATISTICS 156 401 #define IWN_BEACON_STATISTICS 157 402 #define IWN_STATE_CHANGED 161 403 #define IWN_BEACON_MISSED 162 404 #define IWN_RX_PHY 192 405 #define IWN_MPDU_RX_DONE 193 406 #define IWN_RX_DONE 195 407 #define IWN_RX_COMPRESSED_BA 197 408 409 uint8_t flags; 410 uint8_t idx; 411 uint8_t qid; 412 } __packed; 413 414 /* Possible RX status flags. */ 415 #define IWN_RX_NO_CRC_ERR (1 << 0) 416 #define IWN_RX_NO_OVFL_ERR (1 << 1) 417 /* Shortcut for the above. */ 418 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 419 #define IWN_RX_MPDU_MIC_OK (1 << 6) 420 #define IWN_RX_CIPHER_MASK (7 << 8) 421 #define IWN_RX_CIPHER_CCMP (2 << 8) 422 #define IWN_RX_MPDU_DEC (1 << 11) 423 #define IWN_RX_DECRYPT_MASK (3 << 11) 424 #define IWN_RX_DECRYPT_OK (3 << 11) 425 426 struct iwn_tx_cmd { 427 uint8_t code; 428 #define IWN_CMD_RXON 16 429 #define IWN_CMD_RXON_ASSOC 17 430 #define IWN_CMD_EDCA_PARAMS 19 431 #define IWN_CMD_TIMING 20 432 #define IWN_CMD_ADD_NODE 24 433 #define IWN_CMD_TX_DATA 28 434 #define IWN_CMD_SET_LED 72 435 #define IWN_CMD_LINK_QUALITY 78 436 #define IWN5000_CMD_WIMAX_COEX 90 437 #define IWN5000_CMD_CALIB_CONFIG 101 438 #define IWN_CMD_SET_POWER_MODE 119 439 #define IWN_CMD_SCAN 128 440 #define IWN_CMD_TXPOWER_DBM 149 441 #define IWN_CMD_TXPOWER 151 442 #define IWN5000_CMD_TX_ANT_CONFIG 152 443 #define IWN_CMD_TXPOWER_DBM_V1 152 444 #define IWN_CMD_BT_COEX 155 445 #define IWN_CMD_GET_STATISTICS 156 446 #define IWN_CMD_SET_CRITICAL_TEMP 164 447 #define IWN_CMD_SET_SENSITIVITY 168 448 #define IWN_CMD_PHY_CALIB 176 449 #define IWN_CMD_BT_COEX_PRIO_TABLE 204 450 #define IWN_CMD_BT_COEX_PROT 205 451 452 uint8_t flags; 453 uint8_t idx; 454 uint8_t qid; 455 uint8_t data[136]; 456 } __packed; 457 458 /* Antenna flags, used in various commands. */ 459 #define IWN_ANT_A (1 << 0) 460 #define IWN_ANT_B (1 << 1) 461 #define IWN_ANT_C (1 << 2) 462 /* Shortcuts. */ 463 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 464 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 465 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 466 467 /* Structure for command IWN_CMD_RXON. */ 468 struct iwn_rxon { 469 uint8_t myaddr[IEEE80211_ADDR_LEN]; 470 uint16_t reserved1; 471 uint8_t bssid[IEEE80211_ADDR_LEN]; 472 uint16_t reserved2; 473 uint8_t wlap[IEEE80211_ADDR_LEN]; 474 uint16_t reserved3; 475 uint8_t mode; 476 #define IWN_MODE_HOSTAP 1 477 #define IWN_MODE_STA 3 478 #define IWN_MODE_IBSS 4 479 #define IWN_MODE_MONITOR 6 480 481 uint8_t air; 482 uint16_t rxchain; 483 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 484 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 485 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 486 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 487 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 488 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 489 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 490 491 uint8_t ofdm_mask; 492 uint8_t cck_mask; 493 uint16_t associd; 494 uint32_t flags; 495 #define IWN_RXON_24GHZ (1 << 0) 496 #define IWN_RXON_CCK (1 << 1) 497 #define IWN_RXON_AUTO (1 << 2) 498 #define IWN_RXON_SHSLOT (1 << 4) 499 #define IWN_RXON_SHPREAMBLE (1 << 5) 500 #define IWN_RXON_NODIVERSITY (1 << 7) 501 #define IWN_RXON_ANTENNA_A (1 << 8) 502 #define IWN_RXON_ANTENNA_B (1 << 9) 503 #define IWN_RXON_TSF (1 << 15) 504 #define IWN_RXON_CTS_TO_SELF (1 << 30) 505 506 uint32_t filter; 507 #define IWN_FILTER_PROMISC (1 << 0) 508 #define IWN_FILTER_CTL (1 << 1) 509 #define IWN_FILTER_MULTICAST (1 << 2) 510 #define IWN_FILTER_NODECRYPT (1 << 3) 511 #define IWN_FILTER_BSS (1 << 5) 512 #define IWN_FILTER_BEACON (1 << 6) 513 514 uint8_t chan; 515 uint8_t reserved4; 516 uint8_t ht_single_mask; 517 uint8_t ht_dual_mask; 518 /* The following fields are for >=5000 Series only. */ 519 uint8_t ht_triple_mask; 520 uint8_t reserved5; 521 uint16_t acquisition; 522 uint16_t reserved6; 523 } __packed; 524 525 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 526 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 527 528 /* Structure for command IWN_CMD_ASSOCIATE. */ 529 struct iwn_assoc { 530 uint32_t flags; 531 uint32_t filter; 532 uint8_t ofdm_mask; 533 uint8_t cck_mask; 534 uint16_t reserved; 535 } __packed; 536 537 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 538 struct iwn_edca_params { 539 uint32_t flags; 540 #define IWN_EDCA_UPDATE (1 << 0) 541 #define IWN_EDCA_TXOP (1 << 4) 542 543 struct { 544 uint16_t cwmin; 545 uint16_t cwmax; 546 uint8_t aifsn; 547 uint8_t reserved; 548 uint16_t txoplimit; 549 } __packed ac[WME_NUM_AC]; 550 } __packed; 551 552 /* Structure for command IWN_CMD_TIMING. */ 553 struct iwn_cmd_timing { 554 uint64_t tstamp; 555 uint16_t bintval; 556 uint16_t atim; 557 uint32_t binitval; 558 uint16_t lintval; 559 uint16_t reserved; 560 } __packed; 561 562 /* Structure for command IWN_CMD_ADD_NODE. */ 563 struct iwn_node_info { 564 uint8_t control; 565 #define IWN_NODE_UPDATE (1 << 0) 566 567 uint8_t reserved1[3]; 568 569 uint8_t macaddr[IEEE80211_ADDR_LEN]; 570 uint16_t reserved2; 571 uint8_t id; 572 #define IWN_ID_BSS 0 573 #define IWN5000_ID_BROADCAST 15 574 #define IWN4965_ID_BROADCAST 31 575 576 uint8_t flags; 577 #define IWN_FLAG_SET_KEY (1 << 0) 578 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 579 #define IWN_FLAG_SET_TXRATE (1 << 2) 580 #define IWN_FLAG_SET_ADDBA (1 << 3) 581 #define IWN_FLAG_SET_DELBA (1 << 4) 582 583 uint16_t reserved3; 584 uint16_t kflags; 585 #define IWN_KFLAG_CCMP (1 << 1) 586 #define IWN_KFLAG_MAP (1 << 3) 587 #define IWN_KFLAG_KID(kid) ((kid) << 8) 588 #define IWN_KFLAG_INVALID (1 << 11) 589 #define IWN_KFLAG_GROUP (1 << 14) 590 591 uint8_t tsc2; /* TKIP TSC2 */ 592 uint8_t reserved4; 593 uint16_t ttak[5]; 594 uint8_t kid; 595 uint8_t reserved5; 596 uint8_t key[16]; 597 /* The following 3 fields are for 5000 Series only. */ 598 uint64_t tsc; 599 uint8_t rxmic[IEEE80211_TKIP_MICLEN]; 600 uint8_t txmic[IEEE80211_TKIP_MICLEN]; 601 602 uint32_t htflags; 603 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 604 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 605 606 uint32_t mask; 607 uint16_t disable_tid; 608 uint16_t reserved6; 609 uint8_t addba_tid; 610 uint8_t delba_tid; 611 uint16_t addba_ssn; 612 uint32_t reserved7; 613 } __packed; 614 615 struct iwn4965_node_info { 616 uint8_t control; 617 uint8_t reserved1[3]; 618 uint8_t macaddr[IEEE80211_ADDR_LEN]; 619 uint16_t reserved2; 620 uint8_t id; 621 uint8_t flags; 622 uint16_t reserved3; 623 uint16_t kflags; 624 uint8_t tsc2; /* TKIP TSC2 */ 625 uint8_t reserved4; 626 uint16_t ttak[5]; 627 uint8_t kid; 628 uint8_t reserved5; 629 uint8_t key[16]; 630 uint32_t htflags; 631 uint32_t mask; 632 uint16_t disable_tid; 633 uint16_t reserved6; 634 uint8_t addba_tid; 635 uint8_t delba_tid; 636 uint16_t addba_ssn; 637 uint32_t reserved7; 638 } __packed; 639 640 #define IWN_RFLAG_CCK (1 << 1) 641 #define IWN_RFLAG_ANT(x) ((x) << 6) 642 643 /* Structure for command IWN_CMD_TX_DATA. */ 644 struct iwn_cmd_data { 645 uint16_t len; 646 uint16_t lnext; 647 uint32_t flags; 648 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 649 #define IWN_TX_NEED_RTS (1 << 1) 650 #define IWN_TX_NEED_CTS (1 << 2) 651 #define IWN_TX_NEED_ACK (1 << 3) 652 #define IWN_TX_LINKQ (1 << 4) 653 #define IWN_TX_IMM_BA (1 << 6) 654 #define IWN_TX_FULL_TXOP (1 << 7) 655 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 656 #define IWN_TX_AUTO_SEQ (1 << 13) 657 #define IWN_TX_MORE_FRAG (1 << 14) 658 #define IWN_TX_INSERT_TSTAMP (1 << 16) 659 #define IWN_TX_NEED_PADDING (1 << 20) 660 661 uint32_t scratch; 662 uint8_t plcp; 663 uint8_t rflags; 664 uint16_t xrflags; 665 666 uint8_t id; 667 uint8_t security; 668 #define IWN_CIPHER_WEP40 1 669 #define IWN_CIPHER_CCMP 2 670 #define IWN_CIPHER_TKIP 3 671 #define IWN_CIPHER_WEP104 9 672 673 uint8_t linkq; 674 uint8_t reserved2; 675 uint8_t key[16]; 676 uint16_t fnext; 677 uint16_t reserved3; 678 uint32_t lifetime; 679 #define IWN_LIFETIME_INFINITE 0xffffffff 680 681 uint32_t loaddr; 682 uint8_t hiaddr; 683 uint8_t rts_ntries; 684 uint8_t data_ntries; 685 uint8_t tid; 686 uint16_t timeout; 687 uint16_t txop; 688 } __packed; 689 690 /* Structure for command IWN_CMD_LINK_QUALITY. */ 691 #define IWN_MAX_TX_RETRIES 16 692 struct iwn_cmd_link_quality { 693 uint8_t id; 694 uint8_t reserved1; 695 uint16_t ctl; 696 uint8_t flags; 697 uint8_t mimo; 698 uint8_t antmsk_1stream; 699 uint8_t antmsk_2stream; 700 uint8_t ridx[WME_NUM_AC]; 701 uint16_t ampdu_limit; 702 uint8_t ampdu_threshold; 703 uint8_t ampdu_max; 704 uint32_t reserved2; 705 struct { 706 uint8_t plcp; 707 uint8_t rflags; 708 uint16_t xrflags; 709 } __packed retry[IWN_MAX_TX_RETRIES]; 710 uint32_t reserved3; 711 } __packed; 712 713 /* Structure for command IWN_CMD_SET_LED. */ 714 struct iwn_cmd_led { 715 uint32_t unit; /* multiplier (in usecs) */ 716 uint8_t which; 717 #define IWN_LED_ACTIVITY 1 718 #define IWN_LED_LINK 2 719 720 uint8_t off; 721 uint8_t on; 722 uint8_t reserved; 723 } __packed; 724 725 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 726 struct iwn5000_wimax_coex { 727 uint32_t flags; 728 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 729 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 730 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 731 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 732 733 struct iwn5000_wimax_event { 734 uint8_t request; 735 uint8_t window; 736 uint8_t reserved; 737 uint8_t flags; 738 } __packed events[16]; 739 } __packed; 740 741 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 742 struct iwn5000_calib_elem { 743 uint32_t enable; 744 uint32_t start; 745 #define IWN5000_CALIB_DC (1 << 1) 746 uint32_t send; 747 uint32_t apply; 748 uint32_t reserved; 749 } __packed; 750 751 struct iwn5000_calib_status { 752 struct iwn5000_calib_elem once; 753 struct iwn5000_calib_elem perd; 754 uint32_t flags; 755 } __packed; 756 757 struct iwn5000_calib_config { 758 struct iwn5000_calib_status ucode; 759 struct iwn5000_calib_status driver; 760 uint32_t reserved; 761 } __packed; 762 763 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 764 struct iwn_pmgt_cmd { 765 uint16_t flags; 766 #define IWN_PS_ALLOW_SLEEP (1 << 0) 767 #define IWN_PS_NOTIFY (1 << 1) 768 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 769 #define IWN_PS_PCI_PMGT (1 << 3) 770 #define IWN_PS_FAST_PD (1 << 4) 771 772 uint8_t keepalive; 773 uint8_t debug; 774 uint32_t rxtimeout; 775 uint32_t txtimeout; 776 uint32_t intval[5]; 777 uint32_t beacons; 778 } __packed; 779 780 /* Structures for command IWN_CMD_SCAN. */ 781 struct iwn_scan_essid { 782 uint8_t id; 783 uint8_t len; 784 uint8_t data[IEEE80211_NWID_LEN]; 785 } __packed; 786 787 struct iwn_scan_hdr { 788 uint16_t len; 789 uint8_t reserved1; 790 uint8_t nchan; 791 uint16_t quiet_time; 792 uint16_t quiet_threshold; 793 uint16_t crc_threshold; 794 uint16_t rxchain; 795 uint32_t max_svc; /* background scans */ 796 uint32_t pause_svc; /* background scans */ 797 uint32_t flags; 798 uint32_t filter; 799 800 /* Followed by a struct iwn_cmd_data. */ 801 /* Followed by an array of 20 structs iwn_scan_essid. */ 802 /* Followed by probe request body. */ 803 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 804 } __packed; 805 806 struct iwn_scan_chan { 807 uint32_t flags; 808 #define IWN_CHAN_ACTIVE (1 << 0) 809 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 810 811 uint16_t chan; 812 uint8_t rf_gain; 813 uint8_t dsp_gain; 814 uint16_t active; /* msecs */ 815 uint16_t passive; /* msecs */ 816 } __packed; 817 818 /* Maximum size of a scan command. */ 819 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 820 821 /* 822 * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 823 * sending probe req. This should be set long enough to hear probe responses 824 * from more than one AP. 825 */ 826 #define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 827 #define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 828 #define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 829 #define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 830 831 /* 832 * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 833 * Must be set longer than active dwell time. 834 * For the most reliable scan, set > AP beacon interval (typically 100msec). 835 */ 836 #define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 837 #define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 838 #define IWN_PASSIVE_DWELL_BASE (100) 839 #define IWN_CHANNEL_TUNE_TIME (5) 840 841 /* 842 * If active scanning is requested but a certain channel is 843 * marked passive, we can do active scanning if we detect 844 * transmissions. 845 * 846 * There is an issue with some firmware versions that triggers 847 * a sysassert on a "good CRC threshold" of zero (== disabled), 848 * on a radar channel even though this means that we should NOT 849 * send probes. 850 * 851 * The "good CRC threshold" is the number of frames that we 852 * need to receive during our dwell time on a channel before 853 * sending out probes -- setting this to a huge value will 854 * mean we never reach it, but at the same time work around 855 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 856 * here instead of IWN_GOOD_CRC_TH_DISABLED. 857 * 858 * This was fixed in later versions along with some other 859 * scan changes, and the threshold behaves as a flag in those 860 * versions. 861 */ 862 #define IWN_GOOD_CRC_TH_DISABLED 0 863 #define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 864 #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 865 866 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 867 #define IWN_RIDX_MAX 32 868 struct iwn4965_cmd_txpower { 869 uint8_t band; 870 uint8_t reserved1; 871 uint8_t chan; 872 uint8_t reserved2; 873 struct { 874 uint8_t rf_gain[2]; 875 uint8_t dsp_gain[2]; 876 } __packed power[IWN_RIDX_MAX + 1]; 877 } __packed; 878 879 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 880 struct iwn5000_cmd_txpower { 881 int8_t global_limit; /* in half-dBm */ 882 #define IWN5000_TXPOWER_AUTO 0x7f 883 #define IWN5000_TXPOWER_MAX_DBM 16 884 885 uint8_t flags; 886 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 887 888 int8_t srv_limit; /* in half-dBm */ 889 uint8_t reserved; 890 } __packed; 891 892 /* Structure for command IWN_CMD_BT_COEX. */ 893 struct iwn_bluetooth { 894 uint8_t flags; 895 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 896 #define IWN_BT_COEX_BT_PRIO (1 << 1) 897 #define IWN_BT_COEX_2_WIRE (1 << 2) 898 #define IWN_BT_COEX_ENABLE (IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO) 899 uint8_t lead_time; 900 #define IWN_BT_LEAD_TIME_DEF 30 901 uint8_t max_kill; 902 #define IWN_BT_MAX_KILL_DEF 5 903 uint8_t bt3_timer_t7_value; 904 #define IWN_BT_BT3_T7_DEF 1 905 uint32_t kill_ack_mask; 906 #define IWN_BT_KILL_ACK_MASK_DEF htole32(0xffff0000) 907 uint32_t kill_cts_mask; 908 #define IWN_BT_KILL_CTS_MASK_DEF htole32(0xffff0000) 909 } __packed; 910 911 struct iwn_bt_basic { 912 struct iwn_bluetooth bt; 913 #define IWN_BT_BASIC_CHAN_INHIBITION 1 914 #define IWN_BT_BASIC_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5)) 915 #define IWN_BT_BASIC_MODE_SHIFT 3 916 #define IWN_BT_BASIC_MODE_DISABLED 0 917 #define IWN_BT_BASIC_MODE_LEGACY_2W 1 918 #define IWN_BT_BASIC_MODE_3W 2 919 #define IWN_BT_BASIC_MODE_4W 3 920 #define IWN_BT_UCODE_DEFAULT (1 << 6) 921 #define IWN_BT_SYNC_2_BT_DISABLE (1 << 7) 922 uint8_t bt3_prio_sample_time; 923 #define IWN_BT_BT3_PRIO_SAMPLE_DEF 2 924 uint8_t bt3_timer_t2_value; 925 #define IWN_BT_BT3_T2_DEF 12 926 uint16_t bt4_reaction_time; /* unused */ 927 uint32_t bt3_lookup_table[12]; 928 union { 929 struct { 930 uint8_t reduce_txpower; /* bit 0 */ 931 uint8_t reserved; 932 }; 933 uint16_t bt4_decision; 934 }; 935 uint16_t valid; 936 #define IWN_BT_VALID_ENABLE_FLAGS htole16(1 << 0) 937 #define IWN_BT_VALID_BOOST htole16(1 << 1) 938 #define IWN_BT_VALID_MAX_KILL htole16(1 << 2) 939 #define IWN_BT_VALID_3W_TIMERS htole16(1 << 3) 940 #define IWN_BT_VALID_KILL_ACK_MASK htole16(1 << 4) 941 #define IWN_BT_VALID_KILL_CTS_MASK htole16(1 << 5) 942 #define IWN_BT_VALID_REDUCED_TX_PWR htole16(1 << 6) 943 #define IWN_BT_VALID_3W_LUT htole16(1 << 7) 944 #define IWN_BT_ALL_VALID_MASK (IWN_BT_VALID_ENABLE_FLAGS | \ 945 IWN_BT_VALID_BOOST | \ 946 IWN_BT_VALID_MAX_KILL | \ 947 IWN_BT_VALID_3W_TIMERS | \ 948 IWN_BT_VALID_KILL_ACK_MASK | \ 949 IWN_BT_VALID_KILL_CTS_MASK | \ 950 IWN_BT_VALID_REDUCED_TX_PWR | \ 951 IWN_BT_VALID_3W_LUT) 952 } __packed; 953 954 struct iwn_bt_adv1 { 955 struct iwn_bt_basic basic; 956 uint8_t prio_boost; 957 #define IWN_BT_PRIO_BOOST_DEF 0xf0 958 /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */ 959 uint8_t tx_prio_boost; 960 uint16_t rx_prio_boost; 961 } __packed; 962 963 struct iwn_bt_adv2 { 964 struct iwn_bt_basic basic; 965 uint32_t prio_boost; 966 #define IWN_BT_PRIO_BOOST_DEF32 0xf0f0f0 967 uint8_t reserved; 968 /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */ 969 uint8_t tx_prio_boost; 970 uint16_t rx_prio_boost; 971 } __packed; 972 973 /* Structure for command IWN_CMD_BT_COEX_PRIOTABLE */ 974 struct iwn_btcoex_priotable { 975 uint8_t calib_init1; 976 uint8_t calib_init2; 977 uint8_t calib_periodic_low1; 978 uint8_t calib_periodic_low2; 979 uint8_t calib_periodic_high1; 980 uint8_t calib_periodic_high2; 981 uint8_t dtim; 982 uint8_t scan52; 983 uint8_t scan24; 984 uint8_t reserved[7]; 985 } __packed; 986 987 /* Structure for command IWN_CMD_BT_COEX_PROT */ 988 struct iwn_btcoex_prot { 989 uint8_t open; 990 uint8_t type; 991 uint8_t reserved[2]; 992 } __packed; 993 994 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 995 struct iwn_critical_temp { 996 uint32_t reserved; 997 uint32_t tempM; 998 uint32_t tempR; 999 /* degK <-> degC conversion macros. */ 1000 #define IWN_CTOK(c) ((c) + 273) 1001 #define IWN_KTOC(k) ((k) - 273) 1002 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1003 } __packed; 1004 1005 /* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1006 struct iwn_sensitivity_cmd { 1007 uint16_t which; 1008 #define IWN_SENSITIVITY_DEFAULTTBL 0 1009 #define IWN_SENSITIVITY_WORKTBL 1 1010 1011 uint16_t energy_cck; 1012 uint16_t energy_ofdm; 1013 uint16_t corr_ofdm_x1; 1014 uint16_t corr_ofdm_mrc_x1; 1015 uint16_t corr_cck_mrc_x4; 1016 uint16_t corr_ofdm_x4; 1017 uint16_t corr_ofdm_mrc_x4; 1018 uint16_t corr_barker; 1019 uint16_t corr_barker_mrc; 1020 uint16_t corr_cck_x4; 1021 uint16_t energy_ofdm_th; 1022 } __packed; 1023 1024 struct iwn_enhanced_sensitivity_cmd { 1025 uint16_t which; 1026 uint16_t energy_cck; 1027 uint16_t energy_ofdm; 1028 uint16_t corr_ofdm_x1; 1029 uint16_t corr_ofdm_mrc_x1; 1030 uint16_t corr_cck_mrc_x4; 1031 uint16_t corr_ofdm_x4; 1032 uint16_t corr_ofdm_mrc_x4; 1033 uint16_t corr_barker; 1034 uint16_t corr_barker_mrc; 1035 uint16_t corr_cck_x4; 1036 uint16_t energy_ofdm_th; 1037 /* "Enhanced" part. */ 1038 uint16_t ina_det_ofdm; 1039 uint16_t ina_det_cck; 1040 uint16_t corr_11_9_en; 1041 uint16_t ofdm_det_slope_mrc; 1042 uint16_t ofdm_det_icept_mrc; 1043 uint16_t ofdm_det_slope; 1044 uint16_t ofdm_det_icept; 1045 uint16_t cck_det_slope_mrc; 1046 uint16_t cck_det_icept_mrc; 1047 uint16_t cck_det_slope; 1048 uint16_t cck_det_icept; 1049 uint16_t reserved; 1050 } __packed; 1051 1052 /* Structures for command IWN_CMD_PHY_CALIB. */ 1053 struct iwn_phy_calib { 1054 uint8_t code; 1055 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 1056 #define IWN5000_PHY_CALIB_DC 8 1057 #define IWN5000_PHY_CALIB_LO 9 1058 #define IWN5000_PHY_CALIB_TX_IQ 11 1059 #define IWN5000_PHY_CALIB_CRYSTAL 15 1060 #define IWN5000_PHY_CALIB_BASE_BAND 16 1061 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1062 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1063 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 1064 1065 #define IWN6000_PHY_CALIB_TEMP_OFFSET 18 1066 #define IWN2000_PHY_CALIB_TEMP_OFFSET 18 1067 1068 #define IWN5000_PHY_CALIB_MAX 253 1069 1070 uint8_t group; 1071 uint8_t ngroups; 1072 uint8_t isvalid; 1073 } __packed; 1074 1075 struct iwn5000_phy_calib_crystal { 1076 uint8_t code; 1077 uint8_t group; 1078 uint8_t ngroups; 1079 uint8_t isvalid; 1080 1081 uint8_t cap_pin[2]; 1082 uint8_t reserved[2]; 1083 } __packed; 1084 1085 struct iwn6000_phy_calib_temp_offset { 1086 uint8_t code; 1087 uint8_t group; 1088 uint8_t ngroups; 1089 uint8_t isvalid; 1090 int16_t offset; 1091 #define IWN_DEFAULT_TEMP_OFFSET 2700 1092 1093 uint16_t reserved; 1094 } __packed; 1095 1096 struct iwn2000_phy_calib_temp_offset { 1097 uint8_t code; 1098 uint8_t group; 1099 uint8_t ngroups; 1100 uint8_t isvalid; 1101 int16_t offset_high; 1102 int16_t offset_low; 1103 int16_t burnt_voltage_ref; 1104 int16_t reserved; 1105 } __packed; 1106 1107 struct iwn_phy_calib_gain { 1108 uint8_t code; 1109 uint8_t group; 1110 uint8_t ngroups; 1111 uint8_t isvalid; 1112 1113 int8_t gain[3]; 1114 uint8_t reserved; 1115 } __packed; 1116 1117 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1118 struct iwn_spectrum_cmd { 1119 uint16_t len; 1120 uint8_t token; 1121 uint8_t id; 1122 uint8_t origin; 1123 uint8_t periodic; 1124 uint16_t timeout; 1125 uint32_t start; 1126 uint32_t reserved1; 1127 uint32_t flags; 1128 uint32_t filter; 1129 uint16_t nchan; 1130 uint16_t reserved2; 1131 struct { 1132 uint32_t duration; 1133 uint8_t chan; 1134 uint8_t type; 1135 #define IWN_MEASUREMENT_BASIC (1 << 0) 1136 #define IWN_MEASUREMENT_CCA (1 << 1) 1137 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1138 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1139 #define IWN_MEASUREMENT_FRAME (1 << 4) 1140 #define IWN_MEASUREMENT_IDLE (1 << 7) 1141 1142 uint16_t reserved; 1143 } __packed chan[10]; 1144 } __packed; 1145 1146 /* Structure for IWN_UC_READY notification. */ 1147 #define IWN_NATTEN_GROUPS 5 1148 struct iwn_ucode_info { 1149 uint8_t minor; 1150 uint8_t major; 1151 uint16_t reserved1; 1152 uint8_t revision[8]; 1153 uint8_t type; 1154 uint8_t subtype; 1155 #define IWN_UCODE_RUNTIME 0 1156 #define IWN_UCODE_INIT 9 1157 1158 uint16_t reserved2; 1159 uint32_t logptr; 1160 uint32_t errptr; 1161 uint32_t tstamp; 1162 uint32_t valid; 1163 1164 /* The following fields are for UCODE_INIT only. */ 1165 int32_t volt; 1166 struct { 1167 int32_t chan20MHz; 1168 int32_t chan40MHz; 1169 } __packed temp[4]; 1170 int32_t atten[IWN_NATTEN_GROUPS][2]; 1171 } __packed; 1172 1173 /* Structures for IWN_TX_DONE notification. */ 1174 struct iwn4965_tx_stat { 1175 uint8_t nframes; 1176 uint8_t btkillcnt; 1177 uint8_t rtsfailcnt; 1178 uint8_t ackfailcnt; 1179 uint8_t rate; 1180 uint8_t rflags; 1181 uint16_t xrflags; 1182 uint16_t duration; 1183 uint16_t reserved; 1184 uint32_t power[2]; 1185 uint32_t status; 1186 } __packed; 1187 1188 struct iwn5000_tx_stat { 1189 uint8_t nframes; 1190 uint8_t btkillcnt; 1191 uint8_t rtsfailcnt; 1192 uint8_t ackfailcnt; 1193 uint8_t rate; 1194 uint8_t rflags; 1195 uint16_t xrflags; 1196 uint16_t duration; 1197 uint16_t reserved; 1198 uint32_t power[2]; 1199 uint32_t info; 1200 uint16_t seq; 1201 uint16_t len; 1202 uint8_t tlc; 1203 uint8_t ratid; 1204 uint8_t fc[2]; 1205 uint16_t status; 1206 uint16_t sequence; 1207 } __packed; 1208 1209 /* Structure for IWN_BEACON_MISSED notification. */ 1210 struct iwn_beacon_missed { 1211 uint32_t consecutive; 1212 uint32_t total; 1213 uint32_t expected; 1214 uint32_t received; 1215 } __packed; 1216 1217 /* Structure for IWN_MPDU_RX_DONE notification. */ 1218 struct iwn_rx_mpdu { 1219 uint16_t len; 1220 uint16_t reserved; 1221 } __packed; 1222 1223 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1224 struct iwn4965_rx_phystat { 1225 uint16_t antenna; 1226 uint16_t agc; 1227 uint8_t rssi[6]; 1228 } __packed; 1229 1230 struct iwn5000_rx_phystat { 1231 uint32_t reserved1; 1232 uint32_t agc; 1233 uint16_t rssi[3]; 1234 } __packed; 1235 1236 struct iwn_rx_stat { 1237 uint8_t phy_len; 1238 uint8_t cfg_phy_len; 1239 #define IWN_STAT_MAXLEN 20 1240 1241 uint8_t id; 1242 uint8_t reserved1; 1243 uint64_t tstamp; 1244 uint32_t beacon; 1245 uint16_t flags; 1246 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1247 1248 uint16_t chan; 1249 uint8_t phybuf[32]; 1250 uint8_t rate; 1251 uint8_t rflags; 1252 uint16_t xrflags; 1253 uint16_t len; 1254 uint16_t reserve3; 1255 } __packed; 1256 1257 #define IWN_RSSI_TO_DBM 44 1258 1259 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1260 struct iwn_compressed_ba { 1261 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1262 uint16_t reserved; 1263 uint8_t id; 1264 uint8_t tid; 1265 uint16_t seq; 1266 uint64_t bitmap; 1267 uint16_t qid; 1268 uint16_t ssn; 1269 } __packed; 1270 1271 /* Structure for IWN_START_SCAN notification. */ 1272 struct iwn_start_scan { 1273 uint64_t tstamp; 1274 uint32_t tbeacon; 1275 uint8_t chan; 1276 uint8_t band; 1277 uint16_t reserved; 1278 uint32_t status; 1279 } __packed; 1280 1281 /* Structure for IWN_STOP_SCAN notification. */ 1282 struct iwn_stop_scan { 1283 uint8_t nchan; 1284 uint8_t status; 1285 uint8_t reserved; 1286 uint8_t chan; 1287 uint64_t tsf; 1288 } __packed; 1289 1290 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1291 struct iwn_spectrum_notif { 1292 uint8_t id; 1293 uint8_t token; 1294 uint8_t idx; 1295 uint8_t state; 1296 #define IWN_MEASUREMENT_START 0 1297 #define IWN_MEASUREMENT_STOP 1 1298 1299 uint32_t start; 1300 uint8_t band; 1301 uint8_t chan; 1302 uint8_t type; 1303 uint8_t reserved1; 1304 uint32_t cca_ofdm; 1305 uint32_t cca_cck; 1306 uint32_t cca_time; 1307 uint8_t basic; 1308 uint8_t reserved2[3]; 1309 uint32_t ofdm[8]; 1310 uint32_t cck[8]; 1311 uint32_t stop; 1312 uint32_t status; 1313 #define IWN_MEASUREMENT_OK 0 1314 #define IWN_MEASUREMENT_CONCURRENT 1 1315 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1316 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1317 #define IWN_MEASUREMENT_STOPPED 6 1318 #define IWN_MEASUREMENT_TIMEOUT 7 1319 #define IWN_MEASUREMENT_FAILED 8 1320 } __packed; 1321 1322 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1323 struct iwn_rx_phy_stats { 1324 uint32_t ina; 1325 uint32_t fina; 1326 uint32_t bad_plcp; 1327 uint32_t bad_crc32; 1328 uint32_t overrun; 1329 uint32_t eoverrun; 1330 uint32_t good_crc32; 1331 uint32_t fa; 1332 uint32_t bad_fina_sync; 1333 uint32_t sfd_timeout; 1334 uint32_t fina_timeout; 1335 uint32_t no_rts_ack; 1336 uint32_t rxe_limit; 1337 uint32_t ack; 1338 uint32_t cts; 1339 uint32_t ba_resp; 1340 uint32_t dsp_kill; 1341 uint32_t bad_mh; 1342 uint32_t rssi_sum; 1343 uint32_t reserved; 1344 } __packed; 1345 1346 struct iwn_rx_general_stats { 1347 uint32_t bad_cts; 1348 uint32_t bad_ack; 1349 uint32_t not_bss; 1350 uint32_t filtered; 1351 uint32_t bad_chan; 1352 uint32_t beacons; 1353 uint32_t missed_beacons; 1354 uint32_t adc_saturated; /* time in 0.8us */ 1355 uint32_t ina_searched; /* time in 0.8us */ 1356 uint32_t noise[3]; 1357 uint32_t flags; 1358 uint32_t load; 1359 uint32_t fa; 1360 uint32_t rssi[3]; 1361 uint32_t energy[3]; 1362 } __packed; 1363 1364 struct iwn_rx_ht_phy_stats { 1365 uint32_t bad_plcp; 1366 uint32_t overrun; 1367 uint32_t eoverrun; 1368 uint32_t good_crc32; 1369 uint32_t bad_crc32; 1370 uint32_t bad_mh; 1371 uint32_t good_ampdu_crc32; 1372 uint32_t ampdu; 1373 uint32_t fragment; 1374 uint32_t reserved; 1375 } __packed; 1376 1377 struct iwn_rx_stats { 1378 struct iwn_rx_phy_stats ofdm; 1379 struct iwn_rx_phy_stats cck; 1380 struct iwn_rx_general_stats general; 1381 struct iwn_rx_ht_phy_stats ht; 1382 } __packed; 1383 1384 struct iwn_tx_stats { 1385 uint32_t preamble; 1386 uint32_t rx_detected; 1387 uint32_t bt_defer; 1388 uint32_t bt_kill; 1389 uint32_t short_len; 1390 uint32_t cts_timeout; 1391 uint32_t ack_timeout; 1392 uint32_t exp_ack; 1393 uint32_t ack; 1394 uint32_t msdu; 1395 uint32_t busrt_err1; 1396 uint32_t burst_err2; 1397 uint32_t cts_collision; 1398 uint32_t ack_collision; 1399 uint32_t ba_timeout; 1400 uint32_t ba_resched; 1401 uint32_t query_ampdu; 1402 uint32_t query; 1403 uint32_t query_ampdu_frag; 1404 uint32_t query_mismatch; 1405 uint32_t not_ready; 1406 uint32_t underrun; 1407 uint32_t bt_ht_kill; 1408 uint32_t rx_ba_resp; 1409 uint32_t reserved[2]; 1410 } __packed; 1411 1412 struct iwn_general_stats { 1413 uint32_t temp; 1414 uint32_t temp_m; 1415 uint32_t burst_check; 1416 uint32_t burst; 1417 uint32_t reserved1[4]; 1418 uint32_t sleep; 1419 uint32_t slot_out; 1420 uint32_t slot_idle; 1421 uint32_t ttl_tstamp; 1422 uint32_t tx_ant_a; 1423 uint32_t tx_ant_b; 1424 uint32_t exec; 1425 uint32_t probe; 1426 uint32_t reserved2[2]; 1427 uint32_t rx_enabled; 1428 uint32_t reserved3[3]; 1429 } __packed; 1430 1431 struct iwn_stats { 1432 uint32_t flags; 1433 struct iwn_rx_stats rx; 1434 struct iwn_tx_stats tx; 1435 struct iwn_general_stats general; 1436 } __packed; 1437 1438 1439 /* Firmware error dump. */ 1440 struct iwn_fw_dump { 1441 uint32_t valid; 1442 uint32_t id; 1443 uint32_t pc; 1444 uint32_t branch_link[2]; 1445 uint32_t interrupt_link[2]; 1446 uint32_t error_data[2]; 1447 uint32_t src_line; 1448 uint32_t tsf; 1449 uint32_t time[2]; 1450 } __packed; 1451 1452 /* TLV firmware header. */ 1453 struct iwn_fw_tlv_hdr { 1454 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1455 uint32_t signature; 1456 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1457 1458 uint8_t descr[64]; 1459 uint32_t rev; 1460 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1461 1462 uint32_t build; 1463 uint64_t altmask; 1464 } __packed; 1465 1466 /* TLV header. */ 1467 struct iwn_fw_tlv { 1468 uint16_t type; 1469 #define IWN_FW_TLV_MAIN_TEXT 1 1470 #define IWN_FW_TLV_MAIN_DATA 2 1471 #define IWN_FW_TLV_INIT_TEXT 3 1472 #define IWN_FW_TLV_INIT_DATA 4 1473 #define IWN_FW_TLV_BOOT_TEXT 5 1474 #define IWN_FW_TLV_PBREQ_MAXLEN 6 1475 #define IWN_FW_TLV_ENH_SENS 14 1476 #define IWN_FW_TLV_PHY_CALIB 15 1477 #define IWN_FW_TLV_FLAGS 18 1478 1479 uint16_t alt; 1480 uint32_t len; 1481 } __packed; 1482 1483 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1484 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1485 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1486 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1487 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1488 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1489 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1490 1491 /** 1492 * enum iwn_ucode_tlv_flag - ucode API flags 1493 * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1494 * was a separate TLV but moved here to save space. 1495 * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1496 * treats good CRC threshold as a boolean 1497 * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1498 * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1499 * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1500 * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1501 * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1502 * offload profile config command. 1503 * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 1504 * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 1505 * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1506 * (rather than two) IPv6 addresses 1507 * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 1508 * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1509 * from the probe request template. 1510 * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 1511 * connection when going back to D0 1512 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1513 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1514 * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 1515 * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 1516 * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 1517 * containing CAM (Continuous Active Mode) indication. 1518 */ 1519 enum iwn_ucode_tlv_flag { 1520 IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 1521 IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 1522 IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 1523 IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 1524 IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 1525 IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 1526 IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 1527 IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 1528 IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 1529 IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 1530 IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 1531 IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 1532 IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 1533 IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 1534 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 1535 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 1536 IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 1537 IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 1538 IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 1539 }; 1540 1541 /* 1542 * Offsets into EEPROM. 1543 */ 1544 #define IWN_EEPROM_MAC 0x015 1545 #define IWN_EEPROM_SKU_CAP 0x045 1546 #define IWN_EEPROM_RFCFG 0x048 1547 #define IWN4965_EEPROM_DOMAIN 0x060 1548 #define IWN4965_EEPROM_BAND1 0x063 1549 #define IWN5000_EEPROM_REG 0x066 1550 #define IWN5000_EEPROM_CAL 0x067 1551 #define IWN4965_EEPROM_BAND2 0x072 1552 #define IWN4965_EEPROM_BAND3 0x080 1553 #define IWN4965_EEPROM_BAND4 0x08d 1554 #define IWN4965_EEPROM_BAND5 0x099 1555 #define IWN4965_EEPROM_BAND6 0x0a0 1556 #define IWN4965_EEPROM_BAND7 0x0a8 1557 #define IWN4965_EEPROM_MAXPOW 0x0e8 1558 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1559 #define IWN4965_EEPROM_BANDS 0x0ea 1560 /* Indirect offsets. */ 1561 #define IWN5000_EEPROM_DOMAIN 0x001 1562 #define IWN5000_EEPROM_BAND1 0x004 1563 #define IWN5000_EEPROM_BAND2 0x013 1564 #define IWN5000_EEPROM_BAND3 0x021 1565 #define IWN5000_EEPROM_BAND4 0x02e 1566 #define IWN5000_EEPROM_BAND5 0x03a 1567 #define IWN5000_EEPROM_BAND6 0x041 1568 #define IWN5000_EEPROM_BAND7 0x049 1569 #define IWN6000_EEPROM_ENHINFO 0x054 1570 #define IWN5000_EEPROM_CRYSTAL 0x128 1571 #define IWN5000_EEPROM_TEMP 0x12a 1572 #define IWN5000_EEPROM_VOLT 0x12b 1573 #define IWN2000_EEPROM_RAWTEMP 0x12b 1574 1575 /* Possible flags for IWN_EEPROM_SKU_CAP. */ 1576 #define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1577 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1578 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1579 1580 /* Possible flags for IWN_EEPROM_RFCFG. */ 1581 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1582 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1583 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1584 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1585 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1586 1587 struct iwn_eeprom_chan { 1588 uint8_t flags; 1589 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1590 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1591 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1592 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1593 1594 int8_t maxpwr; 1595 } __packed; 1596 1597 struct iwn_eeprom_enhinfo { 1598 uint8_t flags; 1599 #define IWN_ENHINFO_VALID (1 << 0) 1600 #define IWN_ENHINFO_5GHZ (1 << 1) 1601 #define IWN_ENHINFO_OFDM (1 << 2) 1602 #define IWN_ENHINFO_HT40 (1 << 3) 1603 #define IWN_ENHINFO_HTAP (1 << 4) 1604 #define IWN_ENHINFO_RES1 (1 << 5) 1605 #define IWN_ENHINFO_RES2 (1 << 6) 1606 #define IWN_ENHINFO_COMMON (1 << 7) 1607 1608 uint8_t chan; 1609 int8_t chain[3]; /* max power in half-dBm */ 1610 uint8_t reserved; 1611 int8_t mimo2; /* max power in half-dBm */ 1612 int8_t mimo3; /* max power in half-dBm */ 1613 } __packed; 1614 1615 struct iwn5000_eeprom_calib_hdr { 1616 uint8_t version; 1617 uint8_t pa_type; 1618 uint16_t volt; 1619 } __packed; 1620 1621 #define IWN_NSAMPLES 3 1622 struct iwn4965_eeprom_chan_samples { 1623 uint8_t num; 1624 struct { 1625 uint8_t temp; 1626 uint8_t gain; 1627 uint8_t power; 1628 int8_t pa_det; 1629 } samples[2][IWN_NSAMPLES]; 1630 } __packed; 1631 1632 #define IWN_NBANDS 8 1633 struct iwn4965_eeprom_band { 1634 uint8_t lo; /* low channel number */ 1635 uint8_t hi; /* high channel number */ 1636 struct iwn4965_eeprom_chan_samples chans[2]; 1637 } __packed; 1638 1639 /* 1640 * Offsets of channels descriptions in EEPROM. 1641 */ 1642 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1643 IWN4965_EEPROM_BAND1, 1644 IWN4965_EEPROM_BAND2, 1645 IWN4965_EEPROM_BAND3, 1646 IWN4965_EEPROM_BAND4, 1647 IWN4965_EEPROM_BAND5, 1648 IWN4965_EEPROM_BAND6, 1649 IWN4965_EEPROM_BAND7 1650 }; 1651 1652 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1653 IWN5000_EEPROM_BAND1, 1654 IWN5000_EEPROM_BAND2, 1655 IWN5000_EEPROM_BAND3, 1656 IWN5000_EEPROM_BAND4, 1657 IWN5000_EEPROM_BAND5, 1658 IWN5000_EEPROM_BAND6, 1659 IWN5000_EEPROM_BAND7 1660 }; 1661 1662 #define IWN_CHAN_BANDS_COUNT 7 1663 #define IWN_MAX_CHAN_PER_BAND 14 1664 static const struct iwn_chan_band { 1665 uint8_t nchan; 1666 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1667 } iwn_bands[] = { 1668 /* 20MHz channels, 2GHz band. */ 1669 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1670 /* 20MHz channels, 5GHz band. */ 1671 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1672 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1673 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1674 { 6, { 145, 149, 153, 157, 161, 165 } }, 1675 /* 40MHz channels (primary channels), 2GHz band. */ 1676 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1677 /* 40MHz channels (primary channels), 5GHz band. */ 1678 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1679 }; 1680 1681 #define IWN1000_OTP_NBLOCKS 3 1682 #define IWN6000_OTP_NBLOCKS 4 1683 #define IWN6050_OTP_NBLOCKS 7 1684 1685 /* HW rate indices. */ 1686 #define IWN_RIDX_CCK1 0 1687 #define IWN_RIDX_OFDM6 4 1688 1689 static const struct iwn_rate { 1690 uint8_t rate; 1691 uint8_t plcp; 1692 uint8_t flags; 1693 } iwn_rates[IWN_RIDX_MAX + 1] = { 1694 { 2, 10, IWN_RFLAG_CCK }, 1695 { 4, 20, IWN_RFLAG_CCK }, 1696 { 11, 55, IWN_RFLAG_CCK }, 1697 { 22, 110, IWN_RFLAG_CCK }, 1698 { 12, 0xd, 0 }, 1699 { 18, 0xf, 0 }, 1700 { 24, 0x5, 0 }, 1701 { 36, 0x7, 0 }, 1702 { 48, 0x9, 0 }, 1703 { 72, 0xb, 0 }, 1704 { 96, 0x1, 0 }, 1705 { 108, 0x3, 0 }, 1706 { 120, 0x3, 0 } 1707 }; 1708 1709 #define IWN4965_MAX_PWR_INDEX 107 1710 1711 /* 1712 * RF Tx gain values from highest to lowest power (values obtained from 1713 * the reference driver.) 1714 */ 1715 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1716 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1717 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1718 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1719 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1720 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1721 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1722 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1723 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1724 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1725 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1726 }; 1727 1728 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1729 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1730 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1731 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1732 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1733 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1734 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1735 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1736 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1737 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1738 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1739 }; 1740 1741 /* 1742 * DSP pre-DAC gain values from highest to lowest power (values obtained 1743 * from the reference driver.) 1744 */ 1745 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1746 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1747 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1748 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1749 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1750 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1751 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1752 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1753 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1754 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1755 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1756 }; 1757 1758 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1759 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1760 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1761 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1762 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1763 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1764 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1765 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1766 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1767 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1768 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1769 }; 1770 1771 /* 1772 * Power saving settings (values obtained from the reference driver.) 1773 */ 1774 #define IWN_NDTIMRANGES 3 1775 #define IWN_NPOWERLEVELS 6 1776 static const struct iwn_pmgt { 1777 uint32_t rxtimeout; 1778 uint32_t txtimeout; 1779 uint32_t intval[5]; 1780 int skip_dtim; 1781 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1782 /* DTIM <= 2 */ 1783 { 1784 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1785 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1786 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1787 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1788 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1789 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1790 }, 1791 /* 3 <= DTIM <= 10 */ 1792 { 1793 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1794 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1795 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1796 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1797 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1798 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1799 }, 1800 /* DTIM >= 11 */ 1801 { 1802 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1803 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1804 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1805 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1806 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1807 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1808 } 1809 }; 1810 1811 struct iwn_sensitivity_limits { 1812 uint32_t min_ofdm_x1; 1813 uint32_t max_ofdm_x1; 1814 uint32_t min_ofdm_mrc_x1; 1815 uint32_t max_ofdm_mrc_x1; 1816 uint32_t min_ofdm_x4; 1817 uint32_t max_ofdm_x4; 1818 uint32_t min_ofdm_mrc_x4; 1819 uint32_t max_ofdm_mrc_x4; 1820 uint32_t min_cck_x4; 1821 uint32_t max_cck_x4; 1822 uint32_t min_cck_mrc_x4; 1823 uint32_t max_cck_mrc_x4; 1824 uint32_t min_energy_cck; 1825 uint32_t energy_cck; 1826 uint32_t energy_ofdm; 1827 uint32_t barker_mrc; 1828 }; 1829 1830 /* 1831 * RX sensitivity limits (values obtained from the reference driver.) 1832 */ 1833 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1834 105, 140, 1835 220, 270, 1836 85, 120, 1837 170, 210, 1838 125, 200, 1839 200, 400, 1840 97, 1841 100, 1842 100, 1843 390 1844 }; 1845 1846 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1847 120, 120, /* min = max for performance bug in DSP. */ 1848 240, 240, /* min = max for performance bug in DSP. */ 1849 90, 120, 1850 170, 210, 1851 125, 200, 1852 170, 400, 1853 95, 1854 95, 1855 95, 1856 390 1857 }; 1858 1859 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1860 105, 105, /* min = max for performance bug in DSP. */ 1861 220, 220, /* min = max for performance bug in DSP. */ 1862 90, 120, 1863 170, 210, 1864 125, 200, 1865 170, 400, 1866 95, 1867 95, 1868 95, 1869 390 1870 }; 1871 1872 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1873 120, 155, 1874 240, 290, 1875 90, 120, 1876 170, 210, 1877 125, 200, 1878 170, 400, 1879 95, 1880 95, 1881 95, 1882 390 1883 }; 1884 1885 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1886 105, 110, 1887 192, 232, 1888 80, 145, 1889 128, 232, 1890 125, 175, 1891 160, 310, 1892 97, 1893 97, 1894 100, 1895 390 1896 }; 1897 1898 static const struct iwn_sensitivity_limits iwn6235_sensitivity_limits = { 1899 105, 110, 1900 192, 232, 1901 80, 145, 1902 128, 232, 1903 125, 175, 1904 160, 310, 1905 100, 1906 110, 1907 110, 1908 336 1909 }; 1910 1911 static const struct iwn_sensitivity_limits iwn2000_sensitivity_limits = { 1912 105, 110, 1913 192, 232, 1914 80, 145, 1915 128, 232, 1916 125, 175, 1917 160, 310, 1918 97, 1919 97, 1920 100, 1921 336 1922 }; 1923 1924 static const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = { 1925 105,110, 1926 128,232, 1927 80,145, 1928 128,232, 1929 125,175, 1930 160,310, 1931 97, 1932 97, 1933 110, 1934 390 1935 }; 1936 1937 /* Map TID to TX scheduler's FIFO. */ 1938 static const uint8_t iwn_tid2fifo[] = { 1939 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1940 }; 1941 1942 /* WiFi/WiMAX coexist event priority table for 6050. */ 1943 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1944 { 0x04, 0x03, 0x00, 0x00 }, 1945 { 0x04, 0x03, 0x00, 0x03 }, 1946 { 0x04, 0x03, 0x00, 0x03 }, 1947 { 0x04, 0x03, 0x00, 0x03 }, 1948 { 0x04, 0x03, 0x00, 0x00 }, 1949 { 0x04, 0x03, 0x00, 0x07 }, 1950 { 0x04, 0x03, 0x00, 0x00 }, 1951 { 0x04, 0x03, 0x00, 0x03 }, 1952 { 0x04, 0x03, 0x00, 0x03 }, 1953 { 0x04, 0x03, 0x00, 0x00 }, 1954 { 0x06, 0x03, 0x00, 0x07 }, 1955 { 0x04, 0x03, 0x00, 0x00 }, 1956 { 0x06, 0x06, 0x00, 0x03 }, 1957 { 0x04, 0x03, 0x00, 0x07 }, 1958 { 0x04, 0x03, 0x00, 0x00 }, 1959 { 0x04, 0x03, 0x00, 0x00 } 1960 }; 1961 1962 /* Firmware errors. */ 1963 static const char * const iwn_fw_errmsg[] = { 1964 "OK", 1965 "FAIL", 1966 "BAD_PARAM", 1967 "BAD_CHECKSUM", 1968 "NMI_INTERRUPT_WDG", 1969 "SYSASSERT", 1970 "FATAL_ERROR", 1971 "BAD_COMMAND", 1972 "HW_ERROR_TUNE_LOCK", 1973 "HW_ERROR_TEMPERATURE", 1974 "ILLEGAL_CHAN_FREQ", 1975 "VCC_NOT_STABLE", 1976 "FH_ERROR", 1977 "NMI_INTERRUPT_HOST", 1978 "NMI_INTERRUPT_ACTION_PT", 1979 "NMI_INTERRUPT_UNKNOWN", 1980 "UCODE_VERSION_MISMATCH", 1981 "HW_ERROR_ABS_LOCK", 1982 "HW_ERROR_CAL_LOCK_FAIL", 1983 "NMI_INTERRUPT_INST_ACTION_PT", 1984 "NMI_INTERRUPT_DATA_ACTION_PT", 1985 "NMI_TRM_HW_ER", 1986 "NMI_INTERRUPT_TRM", 1987 "NMI_INTERRUPT_BREAKPOINT", 1988 "DEBUG_0", 1989 "DEBUG_1", 1990 "DEBUG_2", 1991 "DEBUG_3", 1992 "ADVANCED_SYSASSERT" 1993 }; 1994 1995 /* Find least significant bit that is set. */ 1996 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1997 1998 #define IWN_READ(sc, reg) \ 1999 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2000 2001 #define IWN_WRITE(sc, reg, val) \ 2002 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2003 2004 #define IWN_WRITE_1(sc, reg, val) \ 2005 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2006 2007 #define IWN_SETBITS(sc, reg, mask) \ 2008 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2009 2010 #define IWN_CLRBITS(sc, reg, mask) \ 2011 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2012 2013 #define IWN_BARRIER_WRITE(sc) \ 2014 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2015 BUS_SPACE_BARRIER_WRITE) 2016 2017 #define IWN_BARRIER_READ_WRITE(sc) \ 2018 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2019 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2020 2021