1 /* $NetBSD: eppcic.c,v 1.12 2022/09/27 06:32:53 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: eppcic.c,v 1.12 2022/09/27 06:32:53 skrll Exp $");
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/kmem.h>
35 #include <sys/device.h>
36 #include <sys/kthread.h>
37 #include <uvm/uvm_param.h>
38 #include <sys/bus.h>
39 #include <dev/pcmcia/pcmciareg.h>
40 #include <dev/pcmcia/pcmciavar.h>
41 #include <dev/pcmcia/pcmciachip.h>
42 #include <arm/ep93xx/epsocvar.h>
43 #include <arm/ep93xx/epgpiovar.h>
44 #include <arm/ep93xx/eppcicvar.h>
45 #include <arm/ep93xx/ep93xxreg.h>
46 #include <arm/ep93xx/epsmcreg.h>
47 #include "epled.h"
48 #if NEPLED > 0
49 #include <arm/ep93xx/epledvar.h>
50 #endif
51
52 #include "epgpio.h"
53 #if NEPGPIO == 0
54 #error "epgpio requires in eppcic"
55 #endif
56
57 #ifdef EPPCIC_DEBUG
58 int eppcic_debug = EPPCIC_DEBUG;
59 #define DPRINTFN(n,x) if (eppcic_debug>(n)) printf x;
60 #else
61 #define DPRINTFN(n,x)
62 #endif
63
64 /* Mem & I/O */
65 #define SOCKET0_MCCD1 1 /* pin36/pin26 (negative) Card Detect 1 */
66 #define SOCKET0_MCCD2 2 /* pin67/pin25 (negative) Card Detect 2 */
67 #define SOCKET0_VS1 5 /* pin33/pin43 (negative) Voltage Sense 1 */
68 #define SOCKET0_VS2 7 /* pin57/pin40 (negative) Voltage Sense 2 */
69 /* Memory */
70 #define SOCKET0_WP 0 /* pin33/pin24 Write Protect */
71 #define SOCKET0_MCBVD1 3 /* pin63/pin46 Battery Voltage Detect 1 */
72 #define SOCKET0_MCBVD2 4 /* pin62/pin45 Battery Voltage Detect 2 */
73 #define SOCKET0_READY 6 /* pin16/pin37 Ready */
74 /* I/O */
75 #define SOCKET0_STSCHG 3 /* pin63/pin46 (negative) Status Change */
76 #define SOCKET0_SPKR 4 /* pin62/pin45 (negative) Speaker */
77 #define SOCKET0_IREQ 6 /* pin16/pin37 Interrupt Request */
78
79 struct eppcic_handle {
80 int ph_socket; /* socket number */
81 struct eppcic_softc *ph_sc;
82 device_t ph_card;
83 int (*ph_ih_func)(void *);
84 void *ph_ih_arg;
85 lwp_t *ph_event_thread;
86 int ph_run; /* ktread running */
87 int ph_width; /* 8 or 16 */
88 int ph_vcc; /* 3 or 5 */
89 int ph_status[2]; /* cd1 and cd2 */
90 int ph_port; /* GPIO port */
91 int ph_cd[2]; /* card detect */
92 int ph_vs[2]; /* voltage sense */
93 int ph_ireq; /* interrupt request */
94 struct {
95 bus_size_t reg;
96 bus_addr_t base;
97 bus_size_t size;
98 } ph_space[3];
99 #define IO 0
100 #define COMMON 1
101 #define ATTRIBUTE 2
102 };
103
104 static int eppcic_intr_carddetect(void *);
105 static int eppcic_intr_socket(void *);
106 static int eppcic_print(void *, const char *);
107 static void eppcic_event_thread(void *);
108 void eppcic_shutdown(void *);
109
110 static int eppcic_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
111 struct pcmcia_mem_handle *);
112 static void eppcic_mem_free(pcmcia_chipset_handle_t,
113 struct pcmcia_mem_handle *);
114 static int eppcic_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t,
115 struct pcmcia_mem_handle *, bus_size_t *, int *);
116 static void eppcic_mem_unmap(pcmcia_chipset_handle_t, int);
117 static int eppcic_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t,
118 bus_size_t, struct pcmcia_io_handle *);
119 static void eppcic_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *);
120 static int eppcic_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t,
121 struct pcmcia_io_handle *, int *);
122 static void eppcic_io_unmap(pcmcia_chipset_handle_t, int);
123 static void *eppcic_intr_establish(pcmcia_chipset_handle_t,
124 struct pcmcia_function *,
125 int, int (*)(void *), void *);
126 static void eppcic_intr_disestablish(pcmcia_chipset_handle_t, void *);
127 static void eppcic_socket_enable(pcmcia_chipset_handle_t);
128 static void eppcic_socket_disable(pcmcia_chipset_handle_t);
129 static void eppcic_socket_settype(pcmcia_chipset_handle_t, int);
130
131 static void eppcic_attach_socket(struct eppcic_handle *);
132 static void eppcic_config_socket(struct eppcic_handle *);
133 static int eppcic_get_voltage(struct eppcic_handle *);
134 static void eppcic_set_pcreg(struct eppcic_handle *, int);
135
136 static struct pcmcia_chip_functions eppcic_functions = {
137 eppcic_mem_alloc, eppcic_mem_free,
138 eppcic_mem_map, eppcic_mem_unmap,
139 eppcic_io_alloc, eppcic_io_free,
140 eppcic_io_map, eppcic_io_unmap,
141 eppcic_intr_establish, eppcic_intr_disestablish,
142 eppcic_socket_enable, eppcic_socket_disable,
143 eppcic_socket_settype
144 };
145
146 void
eppcic_attach_common(device_t parent,device_t self,void * aux,eppcic_chipset_tag_t pcic)147 eppcic_attach_common(device_t parent, device_t self, void *aux,
148 eppcic_chipset_tag_t pcic)
149 {
150 struct eppcic_softc *sc = device_private(self);
151 struct epsoc_attach_args *sa = aux;
152 struct eppcic_handle *ph;
153 int reg;
154 int i;
155
156 if (!sa->sa_gpio) {
157 printf("%s: epgpio requires\n", device_xname(self));
158 return;
159 }
160 sc->sc_dev = self;
161 sc->sc_gpio = sa->sa_gpio;
162 sc->sc_iot = sa->sa_iot;
163 sc->sc_hclk = sa->sa_hclk;
164 sc->sc_pcic = pcic;
165 sc->sc_enable = 0;
166 if (bus_space_map(sa->sa_iot, sa->sa_addr,
167 sa->sa_size, 0, &sc->sc_ioh)){
168 printf("%s: Cannot map registers\n", device_xname(self));
169 return;
170 }
171 printf("\n");
172
173 #if NEPLED > 0
174 epled_green_on();
175 epled_red_off();
176 #endif
177 /* socket 0 */
178 ph = kmem_alloc(sizeof(*ph), KM_SLEEP);
179 sc->sc_ph[0] = ph;
180 ph->ph_sc = sc;
181 ph->ph_socket = 0;
182 ph->ph_port = PORT_F;
183 ph->ph_cd[0] = SOCKET0_MCCD1;
184 ph->ph_cd[1] = SOCKET0_MCCD2;
185 ph->ph_vs[0] = SOCKET0_VS1;
186 ph->ph_vs[1] = SOCKET0_VS2;
187 ph->ph_ireq = SOCKET0_IREQ;
188 ph->ph_space[IO].reg = EP93XX_PCMCIA0_IO;
189 ph->ph_space[IO].base = EP93XX_PCMCIA0_HWBASE + EP93XX_PCMCIA_IO;
190 ph->ph_space[IO].size = EP93XX_PCMCIA_IO_SIZE;
191 ph->ph_space[COMMON].reg = EP93XX_PCMCIA0_Common;
192 ph->ph_space[COMMON].base = EP93XX_PCMCIA0_HWBASE
193 + EP93XX_PCMCIA_COMMON;
194 ph->ph_space[COMMON].size = EP93XX_PCMCIA_COMMON_SIZE;
195 ph->ph_space[ATTRIBUTE].reg = EP93XX_PCMCIA0_Attribute;
196 ph->ph_space[ATTRIBUTE].base = EP93XX_PCMCIA0_HWBASE
197 + EP93XX_PCMCIA_ATTRIBUTE;
198 ph->ph_space[ATTRIBUTE].size = EP93XX_PCMCIA_ATTRIBUTE_SIZE;
199 eppcic_attach_socket(ph);
200
201 reg = EP93XX_PCMCIA_WEN | (pcic->socket_type)(sc, 0);
202 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EP93XX_PCMCIA_Ctrl,
203 EP93XX_PCMCIA_RST | reg);
204 delay(10);
205 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EP93XX_PCMCIA_Ctrl, reg);
206 delay(500);
207
208 for (i = 0; i < EP93XX_PCMCIA_NSOCKET; i++)
209 eppcic_config_socket(sc->sc_ph[i]);
210 #if NEPLED > 0
211 epled_green_off();
212 #endif
213 }
214
215 static void
eppcic_attach_socket(struct eppcic_handle * ph)216 eppcic_attach_socket(struct eppcic_handle *ph)
217 {
218 struct eppcic_softc *sc = ph->ph_sc;
219
220 ph->ph_width = 16;
221 ph->ph_vcc = 3;
222 ph->ph_event_thread = NULL;
223 ph->ph_run = 0;
224 ph->ph_ih_func = NULL;
225 ph->ph_ih_arg = NULL;
226 epgpio_in(sc->sc_gpio, ph->ph_port, ph->ph_cd[0]);
227 epgpio_in(sc->sc_gpio, ph->ph_port, ph->ph_cd[1]);
228 epgpio_in(sc->sc_gpio, ph->ph_port, ph->ph_vs[0]);
229 epgpio_in(sc->sc_gpio, ph->ph_port, ph->ph_vs[1]);
230 ph->ph_status[0] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[0]);
231 ph->ph_status[1] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[1]);
232 }
233
234 static void
eppcic_config_socket(struct eppcic_handle * ph)235 eppcic_config_socket(struct eppcic_handle *ph)
236 {
237 struct eppcic_softc *sc = ph->ph_sc;
238 eppcic_chipset_tag_t pcic = sc->sc_pcic;
239 struct pcmciabus_attach_args paa;
240 int wait;
241
242 paa.paa_busname = "pcmcia";
243 paa.pct = (pcmcia_chipset_tag_t)&eppcic_functions;
244 paa.pch = (pcmcia_chipset_handle_t)ph;
245 ph->ph_card = config_found(sc->sc_dev, &paa, eppcic_print, CFARGS_NONE);
246
247 epgpio_intr_establish(sc->sc_gpio, ph->ph_port, ph->ph_cd[0],
248 EDGE_TRIGGER | FALLING_EDGE | DEBOUNCE,
249 IPL_TTY, eppcic_intr_carddetect, ph);
250 epgpio_intr_establish(sc->sc_gpio, ph->ph_port, ph->ph_cd[1],
251 EDGE_TRIGGER | RISING_EDGE | DEBOUNCE,
252 IPL_TTY, eppcic_intr_carddetect, ph);
253 wait = (pcic->power_ctl)(sc, ph->ph_socket, POWER_OFF);
254 delay(wait);
255
256
257 ph->ph_status[0] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[0]);
258 ph->ph_status[1] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[1]);
259
260 DPRINTFN(1, ("eppcic_config_socket: cd1=%d, cd2=%d\n",ph->ph_status[0],ph->ph_status[1]));
261
262 ph->ph_run = 1;
263 kthread_create(PRI_NONE, 0, NULL, eppcic_event_thread, ph,
264 &ph->ph_event_thread, "%s,%d", device_xname(sc->sc_dev),
265 ph->ph_socket);
266 }
267
268 static int
eppcic_print(void * arg,const char * pnp)269 eppcic_print(void *arg, const char *pnp)
270 {
271 return (UNCONF);
272 }
273
274 static void
eppcic_event_thread(void * arg)275 eppcic_event_thread(void *arg)
276 {
277 struct eppcic_handle *ph = arg;
278
279 if (!(ph->ph_status[0] | ph->ph_status[1]))
280 pcmcia_card_attach(ph->ph_card);
281
282 for (;;) {
283 tsleep(ph, PWAIT, "CSC wait", 0);
284 if (!ph->ph_run)
285 break;
286
287 DPRINTFN(1, ("eppcic_event_thread: cd1=%d, cd2=%d\n",ph->ph_status[0],ph->ph_status[1]));
288
289 if (!ph->ph_status[0] && !ph->ph_status[1])
290 pcmcia_card_attach(ph->ph_card);
291 else if (ph->ph_status[0] && ph->ph_status[1])
292 pcmcia_card_detach(ph->ph_card, DETACH_FORCE);
293 }
294
295 DPRINTFN(1, ("eppcic_event_thread: run=%d\n",ph->ph_run));
296 ph->ph_event_thread = NULL;
297 kthread_exit(0);
298 }
299
300 void
eppcic_shutdown(void * arg)301 eppcic_shutdown(void *arg)
302 {
303 struct eppcic_handle *ph = arg;
304
305 DPRINTFN(1, ("eppcic_shutdown\n"));
306 ph->ph_run = 0;
307 wakeup(ph);
308 }
309
310 static int
eppcic_intr_carddetect(void * arg)311 eppcic_intr_carddetect(void *arg)
312 {
313 struct eppcic_handle *ph = arg;
314 struct eppcic_softc *sc = ph->ph_sc;
315 int nstatus[2];
316
317 nstatus[0] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[0]);
318 nstatus[1] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[1]);
319
320 DPRINTFN(1, ("eppcic_intr: cd1=%#x, cd2=%#x\n",nstatus[0],nstatus[1]));
321
322 if (nstatus[0] != ph->ph_status[0] || nstatus[1] != ph->ph_status[1]) {
323 ph->ph_status[0] = nstatus[0];
324 ph->ph_status[1] = nstatus[1];
325 wakeup(ph);
326 }
327 return 0;
328 }
329
330 static int
eppcic_mem_alloc(pcmcia_chipset_handle_t pch,bus_size_t size,struct pcmcia_mem_handle * pmh)331 eppcic_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size,
332 struct pcmcia_mem_handle *pmh)
333 {
334 struct eppcic_handle *ph = (struct eppcic_handle *)pch;
335 struct eppcic_softc *sc = ph->ph_sc;
336
337 DPRINTFN(1, ("eppcic_mem_alloc: size=%#x\n",(unsigned)size));
338
339 pmh->memt = sc->sc_iot;
340 return 0;
341 }
342
343 static void
eppcic_mem_free(pcmcia_chipset_handle_t pch,struct pcmcia_mem_handle * pmh)344 eppcic_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pmh)
345 {
346 DPRINTFN(1, ("eppcic_mem_free\n"));
347 }
348
349 static int
eppcic_mem_map(pcmcia_chipset_handle_t pch,int kind,bus_addr_t addr,bus_size_t size,struct pcmcia_mem_handle * pmh,bus_size_t * offsetp,int * windowp)350 eppcic_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t addr,
351 bus_size_t size, struct pcmcia_mem_handle *pmh,
352 bus_size_t *offsetp, int *windowp)
353 {
354 struct eppcic_handle *ph = (struct eppcic_handle *)pch;
355 struct eppcic_softc *sc = ph->ph_sc;
356 bus_addr_t pa;
357 int err;
358
359 DPRINTFN(1, ("eppcic_mem_map: kind=%d, addr=%#x, size=%#x\n",kind,(unsigned)addr,(unsigned)size));
360
361 pa = addr;
362 *offsetp = 0;
363 size = round_page(size);
364 pmh->realsize = size;
365 if (kind & PCMCIA_WIDTH_MEM8)
366 ph->ph_width = 8;
367 else
368 ph->ph_width = 16;
369 switch (kind & ~PCMCIA_WIDTH_MEM_MASK) {
370 case PCMCIA_MEM_ATTR:
371 eppcic_set_pcreg(ph, ATTRIBUTE);
372 pa += ph->ph_space[ATTRIBUTE].base;
373 break;
374 case PCMCIA_MEM_COMMON:
375 eppcic_set_pcreg(ph, COMMON);
376 pa += ph->ph_space[COMMON].base;
377 break;
378 default:
379 return -1;
380 }
381
382 DPRINTFN(1, ("eppcic_mem_map: pa=%#x, *offsetp=%#x, size=%#x\n",(unsigned)pa,(unsigned)addr,(unsigned)size));
383
384 if (!(err = bus_space_map(sc->sc_iot, pa, size, 0, &pmh->memh)))
385 *windowp = (int)pmh->memh;
386 return err;
387 }
388
389 static void
eppcic_mem_unmap(pcmcia_chipset_handle_t pch,int window)390 eppcic_mem_unmap(pcmcia_chipset_handle_t pch, int window)
391 {
392 struct eppcic_handle *ph = (struct eppcic_handle *)pch;
393 struct eppcic_softc *sc = ph->ph_sc;
394
395 DPRINTFN(1, ("eppcic_mem_unmap: window=%#x\n",window));
396
397 bus_space_unmap(sc->sc_iot, (bus_addr_t)window, 0x400);
398 }
399
400 static int
eppcic_io_alloc(pcmcia_chipset_handle_t pch,bus_addr_t start,bus_size_t size,bus_size_t align,struct pcmcia_io_handle * pih)401 eppcic_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size,
402 bus_size_t align, struct pcmcia_io_handle *pih)
403 {
404 struct eppcic_handle *ph = (struct eppcic_handle *)pch;
405 struct eppcic_softc *sc = ph->ph_sc;
406 bus_addr_t pa;
407
408 DPRINTFN(1, ("eppcic_io_alloc: start=%#x, size=%#x, align=%#x\n",(unsigned)start,(unsigned)size,(unsigned)align));
409
410 pih->iot = sc->sc_iot;
411 pih->addr = start;
412 pih->size = size;
413 pa = pih->addr + ph->ph_space[IO].base;
414 return bus_space_map(sc->sc_iot, pa, size, 0, &pih->ioh);
415 }
416
417 static void
eppcic_io_free(pcmcia_chipset_handle_t pch,struct pcmcia_io_handle * pih)418 eppcic_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pih)
419 {
420 struct eppcic_handle *ph = (struct eppcic_handle *)pch;
421 struct eppcic_softc *sc = ph->ph_sc;
422
423 DPRINTFN(1, ("eppcic_io_free\n"));
424
425 bus_space_unmap(sc->sc_iot, pih->ioh, pih->size);
426 }
427
428 static int
eppcic_io_map(pcmcia_chipset_handle_t pch,int width,bus_addr_t offset,bus_size_t size,struct pcmcia_io_handle * pih,int * windowp)429 eppcic_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset,
430 bus_size_t size, struct pcmcia_io_handle *pih, int *windowp)
431 {
432 struct eppcic_handle *ph = (struct eppcic_handle *)pch;
433
434 DPRINTFN(1, ("eppcic_io_map: offset=%#x, size=%#x, width=%d",(unsigned)offset,(unsigned)size,width));
435
436 switch (width) {
437 case PCMCIA_WIDTH_IO8:
438 DPRINTFN(1, ("(8bit)\n"));
439 ph->ph_width = 8;
440 break;
441 case PCMCIA_WIDTH_IO16:
442 case PCMCIA_WIDTH_AUTO: /* I don't understand how I check it */
443 DPRINTFN(1, ("(16bit)\n"));
444 ph->ph_width = 16;
445 break;
446 default:
447 DPRINTFN(1, ("(unknown)\n"));
448 return -1;
449 }
450 eppcic_set_pcreg(ph, IO);
451 *windowp = 0; /* unused */
452 return 0;
453 }
454
455 static void
eppcic_io_unmap(pcmcia_chipset_handle_t pch,int window)456 eppcic_io_unmap(pcmcia_chipset_handle_t pch, int window)
457 {
458 DPRINTFN(1, ("eppcic_io_unmap: window=%#x\n",window));
459 }
460
461 static void *
eppcic_intr_establish(pcmcia_chipset_handle_t pch,struct pcmcia_function * pf,int ipl,int (* ih_func)(void *),void * ih_arg)462 eppcic_intr_establish(pcmcia_chipset_handle_t pch, struct pcmcia_function *pf,
463 int ipl, int (*ih_func)(void *), void *ih_arg)
464 {
465 struct eppcic_handle *ph = (struct eppcic_handle *)pch;
466 struct eppcic_softc *sc = ph->ph_sc;
467
468 DPRINTFN(1, ("eppcic_intr_establish\n"));
469
470 if (ph->ph_ih_func)
471 return 0;
472
473 ph->ph_ih_func = ih_func;
474 ph->ph_ih_arg = ih_arg;
475 return epgpio_intr_establish(sc->sc_gpio, ph->ph_port, ph->ph_ireq,
476 LEVEL_SENSE | LOW_LEVEL,
477 ipl, eppcic_intr_socket, ph);
478 }
479
480 static void
eppcic_intr_disestablish(pcmcia_chipset_handle_t pch,void * ih)481 eppcic_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih)
482 {
483 struct eppcic_handle *ph = (struct eppcic_handle *)pch;
484 struct eppcic_softc *sc = ph->ph_sc;
485
486 DPRINTFN(1, ("eppcic_intr_disestablish\n"));
487
488 ph->ph_ih_func = NULL;
489 ph->ph_ih_arg = NULL;
490 epgpio_intr_disestablish(sc->sc_gpio, ph->ph_port, ph->ph_ireq);
491 }
492
493 static int
eppcic_intr_socket(void * arg)494 eppcic_intr_socket(void *arg)
495 {
496 struct eppcic_handle *ph = arg;
497 int err = 0;
498
499 if (ph->ph_ih_func) {
500 #if NEPLED > 0
501 epled_red_on();
502 #endif
503 err = (*ph->ph_ih_func)(ph->ph_ih_arg);
504 #if NEPLED > 0
505 epled_red_off();
506 #endif
507 }
508 return err;
509 }
510
511
512 static void
eppcic_socket_enable(pcmcia_chipset_handle_t pch)513 eppcic_socket_enable(pcmcia_chipset_handle_t pch)
514 {
515 struct eppcic_handle *ph = (struct eppcic_handle *)pch;
516 struct eppcic_softc *sc = ph->ph_sc;
517 eppcic_chipset_tag_t pcic = sc->sc_pcic;
518 int wait;
519
520 DPRINTFN(1, ("eppcic_socket_enable\n"));
521
522 wait = (pcic->power_ctl)(sc, ph->ph_socket, POWER_ON);
523 delay(wait);
524 #if NEPLED > 0
525 if (!sc->sc_enable++)
526 epled_green_on();
527 #endif
528 ph->ph_vcc = eppcic_get_voltage(ph);
529 }
530
531 static void
eppcic_socket_disable(pcmcia_chipset_handle_t pch)532 eppcic_socket_disable(pcmcia_chipset_handle_t pch)
533 {
534 struct eppcic_handle *ph = (struct eppcic_handle *)pch;
535 struct eppcic_softc *sc = ph->ph_sc;
536 eppcic_chipset_tag_t pcic = sc->sc_pcic;
537 int wait;
538
539 DPRINTFN(1, ("eppcic_socket_disable\n"));
540
541 wait = (pcic->power_ctl)(sc, ph->ph_socket, POWER_OFF);
542 delay(wait);
543 #if NEPLED > 0
544 if (!--sc->sc_enable)
545 epled_green_off();
546 #endif
547 }
548
549 static void
eppcic_socket_settype(pcmcia_chipset_handle_t pch,int type)550 eppcic_socket_settype(pcmcia_chipset_handle_t pch, int type)
551 {
552 DPRINTFN(1, ("eppcic_socket_settype: type=%d",type));
553
554 switch (type) {
555 case PCMCIA_IFTYPE_MEMORY:
556 DPRINTFN(1, ("(Memory)\n"));
557 break;
558 case PCMCIA_IFTYPE_IO:
559 DPRINTFN(1, ("(I/O)\n"));
560 break;
561 default:
562 DPRINTFN(1, ("(unknown)\n"));
563 return;
564 }
565 }
566
567 static int
eppcic_get_voltage(struct eppcic_handle * ph)568 eppcic_get_voltage(struct eppcic_handle *ph)
569 {
570 struct eppcic_softc *sc = ph->ph_sc;
571 eppcic_chipset_tag_t pcic = sc->sc_pcic;
572 int cap, vcc = 0;
573
574 cap = (pcic->power_capability)(sc, ph->ph_socket);
575 if (epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_vs[0])) {
576 if (cap | VCC_5V)
577 vcc = 5;
578 else
579 printf("%s: unsupported Vcc 5 Volts",
580 device_xname(sc->sc_dev));
581 } else {
582 if (cap | VCC_3V)
583 vcc = 3;
584 else
585 printf("%s: unsupported Vcc 3.3 Volts",
586 device_xname(sc->sc_dev));
587 }
588 DPRINTFN(1, ("eppcic_get_voltage: vs1=%d, vs2=%d (%dV)\n",epgpio_read_bit(sc->sc_gpio, ph->ph_port, ph->ph_vs[0]),epgpio_read_bit(sc->sc_gpio, ph->ph_port, ph->ph_vs[1]),vcc));
589 return vcc;
590 }
591
592 #define EXTRA_DELAY 40
593
594 static void
eppcic_set_pcreg(struct eppcic_handle * ph,int kind)595 eppcic_set_pcreg(struct eppcic_handle *ph, int kind)
596 {
597 struct eppcic_softc *sc = ph->ph_sc;
598 int atiming, htiming, ptiming;
599 int period = 1000000000 / sc->sc_hclk;
600 int width;
601
602 switch (ph->ph_width) {
603 case 8:
604 width = 0;
605 break;
606 case 16:
607 width = EP93XX_PCMCIA_WIDTH_16;
608 break;
609 default:
610 return;
611 }
612 switch (kind) {
613 case IO:
614 atiming = 165; htiming = 20; ptiming = 70;
615 break;
616 case COMMON:
617 #if linux_timing!=hamajima20050816
618 switch (ph->ph_vcc) {
619 case 3:
620 atiming = 465; htiming = 35; ptiming = 100;
621 break;
622 case 5:
623 atiming = 200; htiming = 20; ptiming = 30;
624 break;
625 default:
626 return;
627 }
628 break;
629 #endif
630 case ATTRIBUTE:
631 switch (ph->ph_vcc) {
632 case 3:
633 #if linux_timing!=hamajima20050816
634 atiming = 465; htiming = 35; ptiming = 100;
635 #else
636 atiming = 600; htiming = 35; ptiming = 100;
637 #endif
638 break;
639 case 5:
640 #if linux_timing!=hamajima20050816
641 atiming = 250; htiming = 20; ptiming = 30;
642 #else
643 atiming = 300; htiming = 20; ptiming = 30;
644 #endif
645 break;
646 default:
647 return;
648 }
649 break;
650 default:
651 return;
652 }
653
654 #if linux_timing!=hamajima20050816
655 period = 1000000000 / 50000000;
656 width = EP93XX_PCMCIA_WIDTH_16;
657 #endif
658
659 atiming = (atiming + EXTRA_DELAY) / period;
660 if (atiming>0xff)
661 atiming = 0xff;
662 htiming = ((htiming + EXTRA_DELAY) / period) + 1;
663 if (htiming>0xf)
664 htiming = 0xf;
665 ptiming = (ptiming + EXTRA_DELAY) / period;
666 if (ptiming>0xff)
667 ptiming = 0xff;
668
669 DPRINTFN(1, ("eppcic_set_pcreg: width=%d, access=%d, hold=%d, pre-charge=%d\n",ph->ph_width,atiming,htiming,ptiming));
670
671 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ph->ph_space[kind].reg,
672 width
673 | (atiming<<EP93XX_PCMCIA_ACCESS_SHIFT)
674 | (htiming<<EP93XX_PCMCIA_HOLD_SHIFT)
675 | (ptiming<<EP93XX_PCMCIA_PRECHARGE_SHIFT));
676 tsleep(ph->ph_space, PWAIT, "eppcic_set_pcreg", hz / 4);
677 }
678