1 /* $NetBSD: pcihost_fdt.c,v 1.33 2024/01/12 11:24:48 skrll Exp $ */
2
3 /*-
4 * Copyright (c) 2018 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.33 2024/01/12 11:24:48 skrll Exp $");
31
32 #include <sys/param.h>
33
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/intr.h>
37 #include <sys/kernel.h>
38 #include <sys/kmem.h>
39 #include <sys/lwp.h>
40 #include <sys/mutex.h>
41 #include <sys/queue.h>
42 #include <sys/systm.h>
43
44 #include <machine/cpu.h>
45
46 #include <arm/cpufunc.h>
47
48 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pciconf.h>
51
52 #include <dev/fdt/fdtvar.h>
53
54 #include <arm/pci/pci_msi_machdep.h>
55 #include <arm/fdt/pcihost_fdtvar.h>
56
57 #define PCIHOST_DEFAULT_BUS_MIN 0
58 #define PCIHOST_DEFAULT_BUS_MAX 255
59
60 #define PCIHOST_CACHELINE_SIZE arm_dcache_align
61
62 int pcihost_segment = 0;
63
64 static int pcihost_match(device_t, cfdata_t, void *);
65 static void pcihost_attach(device_t, device_t, void *);
66
67 static int pcihost_config(struct pcihost_softc *);
68
69 static void pcihost_attach_hook(device_t, device_t,
70 struct pcibus_attach_args *);
71 static int pcihost_bus_maxdevs(void *, int);
72 static pcitag_t pcihost_make_tag(void *, int, int, int);
73 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *);
74 static u_int pcihost_get_segment(void *);
75 static pcireg_t pcihost_conf_read(void *, pcitag_t, int);
76 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t);
77 static int pcihost_conf_hook(void *, int, int, int, pcireg_t);
78 static void pcihost_conf_interrupt(void *, int, int, int, int, int *);
79
80 static int pcihost_intr_map(const struct pci_attach_args *,
81 pci_intr_handle_t *);
82 static const char *pcihost_intr_string(void *, pci_intr_handle_t,
83 char *, size_t);
84 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t);
85 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int,
86 uint64_t);
87 static void * pcihost_intr_establish(void *, pci_intr_handle_t,
88 int, int (*)(void *), void *,
89 const char *);
90 static void pcihost_intr_disestablish(void *, void *);
91
92 static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t,
93 int, bus_space_handle_t *);
94
95 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc),
96 pcihost_match, pcihost_attach, NULL, NULL);
97
98 static const struct device_compatible_entry compat_data[] = {
99 { .compat = "pci-host-cam-generic", .value = PCIHOST_CAM },
100 { .compat = "pci-host-ecam-generic", .value = PCIHOST_ECAM },
101 DEVICE_COMPAT_EOL
102 };
103
104 struct pcihost_msi_handler {
105 LIST_ENTRY(pcihost_msi_handler) pmh_next;
106 void *pmh_ih;
107 };
108
109
110 static int
pcihost_match(device_t parent,cfdata_t cf,void * aux)111 pcihost_match(device_t parent, cfdata_t cf, void *aux)
112 {
113 struct fdt_attach_args * const faa = aux;
114
115 return of_compatible_match(faa->faa_phandle, compat_data);
116 }
117
118 static void
pcihost_attach(device_t parent,device_t self,void * aux)119 pcihost_attach(device_t parent, device_t self, void *aux)
120 {
121 struct pcihost_softc * const sc = device_private(self);
122 struct fdt_attach_args * const faa = aux;
123 bus_addr_t cs_addr;
124 bus_size_t cs_size;
125 int error;
126
127 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) {
128 aprint_error(": couldn't get registers\n");
129 return;
130 }
131
132 sc->sc_dev = self;
133 sc->sc_dmat = faa->faa_dmat;
134 sc->sc_bst = faa->faa_bst;
135 sc->sc_pci_bst = faa->faa_bst;
136 sc->sc_phandle = faa->faa_phandle;
137 error = bus_space_map(sc->sc_bst, cs_addr, cs_size,
138 BUS_SPACE_MAP_NONPOSTED, &sc->sc_bsh);
139 if (error) {
140 aprint_error(": couldn't map registers: %d\n", error);
141 return;
142 }
143 sc->sc_type = of_compatible_lookup(sc->sc_phandle, compat_data)->value;
144
145 #ifdef __HAVE_PCI_MSI_MSIX
146 if (sc->sc_type == PCIHOST_ECAM) {
147 sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY;
148 sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY;
149 }
150 #endif
151
152 aprint_naive("\n");
153 aprint_normal(": Generic PCI host controller\n");
154
155 pcihost_init(&sc->sc_pc, sc);
156 pcihost_init2(sc);
157 }
158
159 void
pcihost_init2(struct pcihost_softc * sc)160 pcihost_init2(struct pcihost_softc *sc)
161 {
162 struct pcibus_attach_args pba;
163 const u_int *data;
164 int len;
165
166 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) {
167 if (len != 8) {
168 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n");
169 return;
170 }
171 sc->sc_bus_min = be32toh(data[0]);
172 sc->sc_bus_max = be32toh(data[1]);
173 } else {
174 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN;
175 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX;
176 }
177
178 /*
179 * Assign a fixed PCI segment ("domain") number. If the property is not
180 * present, assign one. The binding spec says if this property is used to
181 * assign static segment numbers, all host bridges should have segments
182 * astatic assigned to prevent overlaps.
183 */
184 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg))
185 sc->sc_seg = pcihost_segment++;
186
187 mutex_init(&sc->sc_msi_handlers_mutex, MUTEX_DEFAULT, IPL_NONE);
188
189 if (pcihost_config(sc) != 0)
190 return;
191
192 memset(&pba, 0, sizeof(pba));
193 pba.pba_flags = PCI_FLAGS_MRL_OKAY |
194 PCI_FLAGS_MRM_OKAY |
195 PCI_FLAGS_MWI_OKAY |
196 sc->sc_pci_flags;
197 pba.pba_iot = &sc->sc_io.bst;
198 pba.pba_memt = &sc->sc_mem.bst;
199 pba.pba_dmat = sc->sc_dmat;
200 #ifdef _PCI_HAVE_DMA64
201 pba.pba_dmat64 = sc->sc_dmat;
202 #endif
203 pba.pba_pc = &sc->sc_pc;
204 pba.pba_bus = sc->sc_bus_min;
205
206 config_found(sc->sc_dev, &pba, pcibusprint,
207 CFARGS(.devhandle = device_handle(sc->sc_dev)));
208 }
209
210 void
pcihost_init(pci_chipset_tag_t pc,void * priv)211 pcihost_init(pci_chipset_tag_t pc, void *priv)
212 {
213 pc->pc_conf_v = priv;
214 pc->pc_attach_hook = pcihost_attach_hook;
215 pc->pc_bus_maxdevs = pcihost_bus_maxdevs;
216 pc->pc_make_tag = pcihost_make_tag;
217 pc->pc_decompose_tag = pcihost_decompose_tag;
218 pc->pc_get_segment = pcihost_get_segment;
219 pc->pc_conf_read = pcihost_conf_read;
220 pc->pc_conf_write = pcihost_conf_write;
221 pc->pc_conf_hook = pcihost_conf_hook;
222 pc->pc_conf_interrupt = pcihost_conf_interrupt;
223
224 pc->pc_intr_v = priv;
225 pc->pc_intr_map = pcihost_intr_map;
226 pc->pc_intr_string = pcihost_intr_string;
227 pc->pc_intr_evcnt = pcihost_intr_evcnt;
228 pc->pc_intr_setattr = pcihost_intr_setattr;
229 pc->pc_intr_establish = pcihost_intr_establish;
230 pc->pc_intr_disestablish = pcihost_intr_disestablish;
231 }
232
233 static int
pcihost_config(struct pcihost_softc * sc)234 pcihost_config(struct pcihost_softc *sc)
235 {
236 const u_int *ranges;
237 u_int probe_only;
238 int error, len, type;
239 bool swap;
240
241 struct pcih_bus_space * const pibs = &sc->sc_io;
242 pibs->bst = *sc->sc_pci_bst;
243 pibs->bst.bs_cookie = pibs;
244 pibs->map = pibs->bst.bs_map;
245 pibs->flags = PCI_FLAGS_IO_OKAY;
246 pibs->bst.bs_map = pcihost_bus_space_map;
247
248 struct pcih_bus_space * const pmbs = &sc->sc_mem;
249 pmbs->bst = *sc->sc_pci_bst;
250 pmbs->bst.bs_cookie = pmbs;
251 pmbs->map = pmbs->bst.bs_map;
252 pmbs->flags = PCI_FLAGS_MEM_OKAY;
253 pmbs->bst.bs_map = pcihost_bus_space_map;
254
255 /*
256 * If this flag is set, skip configuration of the PCI bus and use existing config.
257 */
258 const int chosen = OF_finddevice("/chosen");
259 if (chosen <= 0 || of_getprop_uint32(chosen, "linux,pci-probe-only", &probe_only))
260 probe_only = 0;
261
262 if (sc->sc_pci_ranges != NULL) {
263 ranges = sc->sc_pci_ranges;
264 len = sc->sc_pci_ranges_cells * 4;
265 swap = false;
266 } else {
267 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len);
268 if (ranges == NULL) {
269 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n");
270 return EINVAL;
271 }
272 swap = true;
273 }
274
275 struct pciconf_resources *pcires = pciconf_resource_init();
276
277 /*
278 * Each entry in the ranges table contains:
279 * - bus address (3 cells)
280 * - cpu physical address (2 cells)
281 * - size (2 cells)
282 * Total size for each entry is 28 bytes (7 cells).
283 */
284 while (len >= 28) {
285 #define DECODE32(x,o) (swap ? be32dec(&(x)[o]) : (x)[o])
286 #define DECODE64(x,o) (swap ? be64dec(&(x)[o]) : (((uint64_t)((x)[(o)+0]) << 32) + (x)[(o)+1]))
287 const uint32_t phys_hi = DECODE32(ranges, 0);
288 uint64_t bus_phys = DECODE64(ranges, 1);
289 const uint64_t cpu_phys = DECODE64(ranges, 3);
290 uint64_t size = DECODE64(ranges, 5);
291 #undef DECODE32
292 #undef DECODE64
293
294 len -= 28;
295 ranges += 7;
296
297 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) ==
298 PHYS_HI_SPACE_MEM64) ? true : false;
299 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) {
300 case PHYS_HI_SPACE_IO:
301 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) {
302 aprint_error_dev(sc->sc_dev, "too many IO ranges\n");
303 continue;
304 }
305 pibs->ranges[pibs->nranges].bpci = bus_phys;
306 pibs->ranges[pibs->nranges].bbus = cpu_phys;
307 pibs->ranges[pibs->nranges].size = size;
308 ++pibs->nranges;
309 aprint_verbose_dev(sc->sc_dev,
310 "IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n",
311 bus_phys, size, cpu_phys);
312 /*
313 * Reserve a PC-like legacy IO ports range, perhaps
314 * for access to VGA registers.
315 */
316 if (bus_phys == 0 && size >= 0x10000) {
317 bus_phys += 0x1000;
318 size -= 0x1000;
319 }
320 error = pciconf_resource_add(pcires,
321 PCICONF_RESOURCE_IO, bus_phys, size);
322 if (error == 0)
323 sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY;
324 break;
325 case PHYS_HI_SPACE_MEM64:
326 /* FALLTHROUGH */
327 case PHYS_HI_SPACE_MEM32:
328 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) {
329 aprint_error_dev(sc->sc_dev, "too many mem ranges\n");
330 continue;
331 }
332 /* both pmem and mem spaces are in the same tag */
333 pmbs->ranges[pmbs->nranges].bpci = bus_phys;
334 pmbs->ranges[pmbs->nranges].bbus = cpu_phys;
335 pmbs->ranges[pmbs->nranges].size = size;
336 ++pmbs->nranges;
337 if ((phys_hi & PHYS_HI_PREFETCH) != 0 ||
338 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) {
339 type = PCICONF_RESOURCE_PREFETCHABLE_MEM;
340 aprint_verbose_dev(sc->sc_dev,
341 "MMIO (%d-bit prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n",
342 is64 ? 64 : 32, bus_phys, size, cpu_phys);
343 } else {
344 type = PCICONF_RESOURCE_MEM;
345 aprint_verbose_dev(sc->sc_dev,
346 "MMIO (%d-bit non-prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n",
347 is64 ? 64 : 32, bus_phys, size, cpu_phys);
348 }
349 error = pciconf_resource_add(pcires, type, bus_phys,
350 size);
351 if (error == 0)
352 sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY;
353 break;
354 default:
355 break;
356 }
357 }
358
359 if (probe_only) {
360 error = 0;
361 } else {
362 error = pci_configure_bus(&sc->sc_pc, pcires, sc->sc_bus_min,
363 PCIHOST_CACHELINE_SIZE);
364 }
365
366 pciconf_resource_fini(pcires);
367
368 if (error) {
369 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error);
370 return error;
371 }
372
373 return 0;
374 }
375
376 static void
pcihost_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)377 pcihost_attach_hook(device_t parent, device_t self,
378 struct pcibus_attach_args *pba)
379 {
380 }
381
382 static int
pcihost_bus_maxdevs(void * v,int busno)383 pcihost_bus_maxdevs(void *v, int busno)
384 {
385 return 32;
386 }
387
388 static pcitag_t
pcihost_make_tag(void * v,int b,int d,int f)389 pcihost_make_tag(void *v, int b, int d, int f)
390 {
391 return (b << 16) | (d << 11) | (f << 8);
392 }
393
394 static void
pcihost_decompose_tag(void * v,pcitag_t tag,int * bp,int * dp,int * fp)395 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
396 {
397 if (bp)
398 *bp = (tag >> 16) & 0xff;
399 if (dp)
400 *dp = (tag >> 11) & 0x1f;
401 if (fp)
402 *fp = (tag >> 8) & 0x7;
403 }
404
405 static u_int
pcihost_get_segment(void * v)406 pcihost_get_segment(void *v)
407 {
408 struct pcihost_softc *sc = v;
409
410 return sc->sc_seg;
411 }
412
413 static pcireg_t
pcihost_conf_read(void * v,pcitag_t tag,int offset)414 pcihost_conf_read(void *v, pcitag_t tag, int offset)
415 {
416 struct pcihost_softc *sc = v;
417 int b, d, f;
418 u_int reg;
419
420 pcihost_decompose_tag(v, tag, &b, &d, &f);
421
422 if (b < sc->sc_bus_min || b > sc->sc_bus_max)
423 return (pcireg_t) -1;
424
425 if (sc->sc_type == PCIHOST_CAM) {
426 if (offset & ~0xff)
427 return (pcireg_t) -1;
428 reg = (b << 16) | (d << 11) | (f << 8) | offset;
429 } else if (sc->sc_type == PCIHOST_ECAM) {
430 if (offset & ~0xfff)
431 return (pcireg_t) -1;
432 reg = (b << 20) | (d << 15) | (f << 12) | offset;
433 } else {
434 return (pcireg_t) -1;
435 }
436
437 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg);
438 }
439
440 static void
pcihost_conf_write(void * v,pcitag_t tag,int offset,pcireg_t val)441 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
442 {
443 struct pcihost_softc *sc = v;
444 int b, d, f;
445 u_int reg;
446
447 pcihost_decompose_tag(v, tag, &b, &d, &f);
448
449 if (b < sc->sc_bus_min || b > sc->sc_bus_max)
450 return;
451
452 if (sc->sc_type == PCIHOST_CAM) {
453 if (offset & ~0xff)
454 return;
455 reg = (b << 16) | (d << 11) | (f << 8) | offset;
456 } else if (sc->sc_type == PCIHOST_ECAM) {
457 if (offset & ~0xfff)
458 return;
459 reg = (b << 20) | (d << 15) | (f << 12) | offset;
460 } else {
461 return;
462 }
463
464 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val);
465 }
466
467 static int
pcihost_conf_hook(void * v,int b,int d,int f,pcireg_t id)468 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id)
469 {
470 return PCI_CONF_DEFAULT;
471 }
472
473 static void
pcihost_conf_interrupt(void * v,int bus,int dev,int ipin,int swiz,int * ilinep)474 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep)
475 {
476 }
477
478 static int
pcihost_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ih)479 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih)
480 {
481 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v;
482 u_int addr_cells, interrupt_cells;
483 const u_int *imap, *imask;
484 int imaplen, imasklen;
485 u_int match[4];
486 int index;
487
488 if (pa->pa_intrpin == 0)
489 return EINVAL;
490
491 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen);
492 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen);
493 if (imap == NULL || imask == NULL || imasklen != 16)
494 return EINVAL;
495
496 /* Convert attach args to specifier */
497 match[0] = htobe32(
498 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) |
499 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) |
500 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION)
501 ) & imask[0];
502 match[1] = htobe32(0) & imask[1];
503 match[2] = htobe32(0) & imask[2];
504 match[3] = htobe32(pa->pa_intrpin) & imask[3];
505
506 index = 0;
507 while (imaplen >= 20) {
508 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4]));
509 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells))
510 addr_cells = 2;
511 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells))
512 interrupt_cells = 0;
513 if (imaplen < (addr_cells + interrupt_cells) * 4)
514 return ENXIO;
515
516 if ((imap[0] & imask[0]) == match[0] &&
517 (imap[1] & imask[1]) == match[1] &&
518 (imap[2] & imask[2]) == match[2] &&
519 (imap[3] & imask[3]) == match[3]) {
520 *ih = index;
521 return 0;
522 }
523
524 imap += (5 + addr_cells + interrupt_cells);
525 imaplen -= (5 + addr_cells + interrupt_cells) * 4;
526 index++;
527 }
528
529 return EINVAL;
530 }
531
532 static const u_int *
pcihost_find_intr(struct pcihost_softc * sc,pci_intr_handle_t ih,int * pihandle)533 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle)
534 {
535 u_int addr_cells, interrupt_cells;
536 int imaplen, index;
537 const u_int *imap;
538
539 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen);
540 KASSERT(imap != NULL);
541
542 index = 0;
543 while (imaplen >= 20) {
544 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4]));
545 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells))
546 addr_cells = 2;
547 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells))
548 interrupt_cells = 0;
549 if (imaplen < (addr_cells + interrupt_cells) * 4)
550 return NULL;
551
552 if (index == ih) {
553 *pihandle = map_ihandle;
554 return imap + 5 + addr_cells;
555 }
556
557 imap += (5 + addr_cells + interrupt_cells);
558 imaplen -= (5 + addr_cells + interrupt_cells) * 4;
559 index++;
560 }
561
562 return NULL;
563 }
564
565 static const char *
pcihost_intr_string(void * v,pci_intr_handle_t ih,char * buf,size_t len)566 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
567 {
568 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);
569 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC);
570 struct pcihost_softc *sc = v;
571 const u_int *specifier;
572 int ihandle;
573
574 if (ih & ARM_PCI_INTR_MSIX) {
575 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec);
576 } else if (ih & ARM_PCI_INTR_MSI) {
577 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec);
578 } else {
579 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle);
580 if (specifier == NULL)
581 return NULL;
582
583 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len))
584 return NULL;
585 }
586
587 return buf;
588 }
589
590 const struct evcnt *
pcihost_intr_evcnt(void * v,pci_intr_handle_t ih)591 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih)
592 {
593 return NULL;
594 }
595
596 static int
pcihost_intr_setattr(void * v,pci_intr_handle_t * ih,int attr,uint64_t data)597 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data)
598 {
599 switch (attr) {
600 case PCI_INTR_MPSAFE:
601 if (data)
602 *ih |= ARM_PCI_INTR_MPSAFE;
603 else
604 *ih &= ~ARM_PCI_INTR_MPSAFE;
605 return 0;
606 default:
607 return ENODEV;
608 }
609 }
610
611 static void *
pcihost_intr_establish(void * v,pci_intr_handle_t pih,int ipl,int (* callback)(void *),void * arg,const char * xname)612 pcihost_intr_establish(void *v, pci_intr_handle_t pih, int ipl,
613 int (*callback)(void *), void *arg, const char *xname)
614 {
615 struct pcihost_softc *sc = v;
616 const int flags = (pih & ARM_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0;
617 const u_int *specifier;
618 int ihandle;
619
620 if ((pih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) {
621 void *ih = arm_pci_msi_intr_establish(&sc->sc_pc, pih, ipl,
622 callback, arg, xname);
623
624 if (ih) {
625 struct pcihost_msi_handler * const pmh =
626 kmem_alloc(sizeof(*pmh), KM_SLEEP);
627 pmh->pmh_ih = ih;
628 mutex_enter(&sc->sc_msi_handlers_mutex);
629 LIST_INSERT_HEAD(&sc->sc_msi_handlers, pmh, pmh_next);
630 mutex_exit(&sc->sc_msi_handlers_mutex);
631 }
632 return ih;
633 }
634
635 specifier = pcihost_find_intr(sc, pih & ARM_PCI_INTR_IRQ, &ihandle);
636 if (specifier == NULL)
637 return NULL;
638
639 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags,
640 callback, arg, xname);
641 }
642
643 static void
pcihost_intr_disestablish(void * v,void * vih)644 pcihost_intr_disestablish(void *v, void *vih)
645 {
646 struct pcihost_softc *sc = v;
647
648 mutex_enter(&sc->sc_msi_handlers_mutex);
649 struct pcihost_msi_handler *pmh;
650 LIST_FOREACH(pmh, &sc->sc_msi_handlers, pmh_next) {
651 if (pmh->pmh_ih == vih) {
652 LIST_REMOVE(pmh, pmh_next);
653 mutex_exit(&sc->sc_msi_handlers_mutex);
654 kmem_free(pmh, sizeof(*pmh));
655 return;
656 }
657 }
658 mutex_exit(&sc->sc_msi_handlers_mutex);
659
660 fdtbus_intr_disestablish(sc->sc_phandle, vih);
661 }
662
663 static int
pcihost_bus_space_map(void * t,bus_addr_t bpa,bus_size_t size,int flag,bus_space_handle_t * bshp)664 pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag,
665 bus_space_handle_t *bshp)
666 {
667 struct pcih_bus_space * const pbs = t;
668
669 if ((pbs->flags & PCI_FLAGS_IO_OKAY) != 0) {
670 /* Force strongly ordered mapping for all I/O space */
671 flag = BUS_SPACE_MAP_NONPOSTED;
672 }
673
674 for (size_t i = 0; i < pbs->nranges; i++) {
675 const bus_addr_t rmin = pbs->ranges[i].bpci;
676 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size;
677 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) {
678 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp);
679 }
680 }
681
682 return ERANGE;
683 }
684