1 /* $NetBSD: amdgpu_dce112_compressor.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */
2
3 /*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce112_compressor.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $");
30
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33
34 #include "dm_services.h"
35
36 #include "dce/dce_11_2_d.h"
37 #include "dce/dce_11_2_sh_mask.h"
38 #include "gmc/gmc_8_1_sh_mask.h"
39 #include "gmc/gmc_8_1_d.h"
40
41 #include "include/logger_interface.h"
42
43 #include "dce112_compressor.h"
44 #define DC_LOGGER \
45 cp110->base.ctx->logger
46 #define DCP_REG(reg)\
47 (reg + cp110->offsets.dcp_offset)
48 #define DMIF_REG(reg)\
49 (reg + cp110->offsets.dmif_offset)
50
51 static const struct dce112_compressor_reg_offsets reg_offsets[] = {
52 {
53 .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
54 .dmif_offset =
55 (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
56 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
57 },
58 {
59 .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
60 .dmif_offset =
61 (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
62 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
63 },
64 {
65 .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
66 .dmif_offset =
67 (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
68 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
69 }
70 };
71
72 static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
73
74 enum fbc_idle_force {
75 /* Bit 0 - Display registers updated */
76 FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
77
78 /* Bit 2 - FBC_GRPH_COMP_EN register updated */
79 FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
80 /* Bit 3 - FBC_SRC_SEL register updated */
81 FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
82 /* Bit 4 - FBC_MIN_COMPRESSION register updated */
83 FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
84 /* Bit 5 - FBC_ALPHA_COMP_EN register updated */
85 FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
86 /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
87 FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
88 /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
89 FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
90
91 /* Bit 24 - Memory write to region 0 defined by MC registers. */
92 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
93 /* Bit 25 - Memory write to region 1 defined by MC registers */
94 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
95 /* Bit 26 - Memory write to region 2 defined by MC registers */
96 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
97 /* Bit 27 - Memory write to region 3 defined by MC registers. */
98 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
99
100 /* Bit 28 - Memory write from any client other than MCIF */
101 FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
102 /* Bit 29 - CG statics screen signal is inactive */
103 FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
104 };
105
lpt_size_alignment(struct dce112_compressor * cp110)106 static uint32_t lpt_size_alignment(struct dce112_compressor *cp110)
107 {
108 /*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */
109 return cp110->base.raw_size * cp110->base.banks_num *
110 cp110->base.dram_channels_num;
111 }
112
lpt_memory_control_config(struct dce112_compressor * cp110,uint32_t lpt_control)113 static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
114 uint32_t lpt_control)
115 {
116 /*LPT MC Config */
117 if (cp110->base.options.bits.LPT_MC_CONFIG == 1) {
118 /* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS):
119 * 00 - 1 CHANNEL
120 * 01 - 2 CHANNELS
121 * 02 - 4 OR 6 CHANNELS
122 * (Only for discrete GPU, N/A for CZ)
123 * 03 - 8 OR 12 CHANNELS
124 * (Only for discrete GPU, N/A for CZ) */
125 switch (cp110->base.dram_channels_num) {
126 case 2:
127 set_reg_field_value(
128 lpt_control,
129 1,
130 LOW_POWER_TILING_CONTROL,
131 LOW_POWER_TILING_NUM_PIPES);
132 break;
133 case 1:
134 set_reg_field_value(
135 lpt_control,
136 0,
137 LOW_POWER_TILING_CONTROL,
138 LOW_POWER_TILING_NUM_PIPES);
139 break;
140 default:
141 DC_LOG_WARNING(
142 "%s: Invalid LPT NUM_PIPES!!!",
143 __func__);
144 break;
145 }
146
147 /* The mapping for LPT NUM_BANKS is in
148 * GRPH_CONTROL.GRPH_NUM_BANKS register field
149 * Specifies the number of memory banks for tiling
150 * purposes. Only applies to 2D and 3D tiling modes.
151 * POSSIBLE VALUES:
152 * 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK
153 * 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK
154 * 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK
155 * 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */
156 switch (cp110->base.banks_num) {
157 case 16:
158 set_reg_field_value(
159 lpt_control,
160 3,
161 LOW_POWER_TILING_CONTROL,
162 LOW_POWER_TILING_NUM_BANKS);
163 break;
164 case 8:
165 set_reg_field_value(
166 lpt_control,
167 2,
168 LOW_POWER_TILING_CONTROL,
169 LOW_POWER_TILING_NUM_BANKS);
170 break;
171 case 4:
172 set_reg_field_value(
173 lpt_control,
174 1,
175 LOW_POWER_TILING_CONTROL,
176 LOW_POWER_TILING_NUM_BANKS);
177 break;
178 case 2:
179 set_reg_field_value(
180 lpt_control,
181 0,
182 LOW_POWER_TILING_CONTROL,
183 LOW_POWER_TILING_NUM_BANKS);
184 break;
185 default:
186 DC_LOG_WARNING(
187 "%s: Invalid LPT NUM_BANKS!!!",
188 __func__);
189 break;
190 }
191
192 /* The mapping is in DMIF_ADDR_CALC.
193 * ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for
194 * Carrizo specifies the memory interleave per pipe.
195 * It effectively specifies the location of pipe bits in
196 * the memory address.
197 * POSSIBLE VALUES:
198 * 00 - ADDR_CONFIG_PIPE_INTERLEAVE_256B: 256 byte
199 * interleave
200 * 01 - ADDR_CONFIG_PIPE_INTERLEAVE_512B: 512 byte
201 * interleave
202 */
203 switch (cp110->base.channel_interleave_size) {
204 case 256: /*256B */
205 set_reg_field_value(
206 lpt_control,
207 0,
208 LOW_POWER_TILING_CONTROL,
209 LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
210 break;
211 case 512: /*512B */
212 set_reg_field_value(
213 lpt_control,
214 1,
215 LOW_POWER_TILING_CONTROL,
216 LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
217 break;
218 default:
219 DC_LOG_WARNING(
220 "%s: Invalid LPT INTERLEAVE_SIZE!!!",
221 __func__);
222 break;
223 }
224
225 /* The mapping for LOW_POWER_TILING_ROW_SIZE is in
226 * DMIF_ADDR_CALC.ADDR_CONFIG_ROW_SIZE register field
227 * for Carrizo. Specifies the size of dram row in bytes.
228 * This should match up with NOOFCOLS field in
229 * MC_ARB_RAMCFG (ROW_SIZE = 4 * 2 ^^ columns).
230 * This register DMIF_ADDR_CALC is not used by the
231 * hardware as it is only used for addrlib assertions.
232 * POSSIBLE VALUES:
233 * 00 - ADDR_CONFIG_1KB_ROW: Treat 1KB as DRAM row
234 * boundary
235 * 01 - ADDR_CONFIG_2KB_ROW: Treat 2KB as DRAM row
236 * boundary
237 * 02 - ADDR_CONFIG_4KB_ROW: Treat 4KB as DRAM row
238 * boundary */
239 switch (cp110->base.raw_size) {
240 case 4096: /*4 KB */
241 set_reg_field_value(
242 lpt_control,
243 2,
244 LOW_POWER_TILING_CONTROL,
245 LOW_POWER_TILING_ROW_SIZE);
246 break;
247 case 2048:
248 set_reg_field_value(
249 lpt_control,
250 1,
251 LOW_POWER_TILING_CONTROL,
252 LOW_POWER_TILING_ROW_SIZE);
253 break;
254 case 1024:
255 set_reg_field_value(
256 lpt_control,
257 0,
258 LOW_POWER_TILING_CONTROL,
259 LOW_POWER_TILING_ROW_SIZE);
260 break;
261 default:
262 DC_LOG_WARNING(
263 "%s: Invalid LPT ROW_SIZE!!!",
264 __func__);
265 break;
266 }
267 } else {
268 DC_LOG_WARNING(
269 "%s: LPT MC Configuration is not provided",
270 __func__);
271 }
272
273 return lpt_control;
274 }
275
is_source_bigger_than_epanel_size(struct dce112_compressor * cp110,uint32_t source_view_width,uint32_t source_view_height)276 static bool is_source_bigger_than_epanel_size(
277 struct dce112_compressor *cp110,
278 uint32_t source_view_width,
279 uint32_t source_view_height)
280 {
281 if (cp110->base.embedded_panel_h_size != 0 &&
282 cp110->base.embedded_panel_v_size != 0 &&
283 ((source_view_width * source_view_height) >
284 (cp110->base.embedded_panel_h_size *
285 cp110->base.embedded_panel_v_size)))
286 return true;
287
288 return false;
289 }
290
align_to_chunks_number_per_line(struct dce112_compressor * cp110,uint32_t pixels)291 static uint32_t align_to_chunks_number_per_line(
292 struct dce112_compressor *cp110,
293 uint32_t pixels)
294 {
295 return 256 * ((pixels + 255) / 256);
296 }
297
wait_for_fbc_state_changed(struct dce112_compressor * cp110,bool enabled)298 static void wait_for_fbc_state_changed(
299 struct dce112_compressor *cp110,
300 bool enabled)
301 {
302 uint8_t counter = 0;
303 uint32_t addr = mmFBC_STATUS;
304 uint32_t value;
305
306 while (counter < 10) {
307 value = dm_read_reg(cp110->base.ctx, addr);
308 if (get_reg_field_value(
309 value,
310 FBC_STATUS,
311 FBC_ENABLE_STATUS) == enabled)
312 break;
313 udelay(10);
314 counter++;
315 }
316
317 if (counter == 10) {
318 DC_LOG_WARNING(
319 "%s: wait counter exceeded, changes to HW not applied",
320 __func__);
321 }
322 }
323
dce112_compressor_power_up_fbc(struct compressor * compressor)324 void dce112_compressor_power_up_fbc(struct compressor *compressor)
325 {
326 uint32_t value;
327 uint32_t addr;
328
329 addr = mmFBC_CNTL;
330 value = dm_read_reg(compressor->ctx, addr);
331 set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
332 set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
333 set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
334 if (compressor->options.bits.CLK_GATING_DISABLED == 1) {
335 /* HW needs to do power measurement comparison. */
336 set_reg_field_value(
337 value,
338 0,
339 FBC_CNTL,
340 FBC_COMP_CLK_GATE_EN);
341 }
342 dm_write_reg(compressor->ctx, addr, value);
343
344 addr = mmFBC_COMP_MODE;
345 value = dm_read_reg(compressor->ctx, addr);
346 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
347 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
348 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
349 dm_write_reg(compressor->ctx, addr, value);
350
351 addr = mmFBC_COMP_CNTL;
352 value = dm_read_reg(compressor->ctx, addr);
353 set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
354 dm_write_reg(compressor->ctx, addr, value);
355 /*FBC_MIN_COMPRESSION 0 ==> 2:1 */
356 /* 1 ==> 4:1 */
357 /* 2 ==> 8:1 */
358 /* 0xF ==> 1:1 */
359 set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
360 dm_write_reg(compressor->ctx, addr, value);
361 compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
362
363 value = 0;
364 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
365
366 value = 0xFFFFFF;
367 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
368 }
369
dce112_compressor_enable_fbc(struct compressor * compressor,uint32_t paths_num,struct compr_addr_and_pitch_params * params)370 void dce112_compressor_enable_fbc(
371 struct compressor *compressor,
372 uint32_t paths_num,
373 struct compr_addr_and_pitch_params *params)
374 {
375 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
376
377 if (compressor->options.bits.FBC_SUPPORT &&
378 (compressor->options.bits.DUMMY_BACKEND == 0) &&
379 (!dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) &&
380 (!is_source_bigger_than_epanel_size(
381 cp110,
382 params->source_view_width,
383 params->source_view_height))) {
384
385 uint32_t addr;
386 uint32_t value;
387
388 /* Before enabling FBC first need to enable LPT if applicable
389 * LPT state should always be changed (enable/disable) while FBC
390 * is disabled */
391 if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) &&
392 (params->source_view_width *
393 params->source_view_height <=
394 dce11_one_lpt_channel_max_resolution)) {
395 dce112_compressor_enable_lpt(compressor);
396 }
397
398 addr = mmFBC_CNTL;
399 value = dm_read_reg(compressor->ctx, addr);
400 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
401 set_reg_field_value(
402 value,
403 params->inst,
404 FBC_CNTL, FBC_SRC_SEL);
405 dm_write_reg(compressor->ctx, addr, value);
406
407 /* Keep track of enum controller_id FBC is attached to */
408 compressor->is_enabled = true;
409 compressor->attached_inst = params->inst;
410 cp110->offsets = reg_offsets[params->inst];
411
412 /*Toggle it as there is bug in HW */
413 set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
414 dm_write_reg(compressor->ctx, addr, value);
415 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
416 dm_write_reg(compressor->ctx, addr, value);
417
418 wait_for_fbc_state_changed(cp110, true);
419 }
420 }
421
dce112_compressor_disable_fbc(struct compressor * compressor)422 void dce112_compressor_disable_fbc(struct compressor *compressor)
423 {
424 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
425
426 if (compressor->options.bits.FBC_SUPPORT &&
427 dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
428 uint32_t reg_data;
429 /* Turn off compression */
430 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
431 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
432 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
433
434 /* Reset enum controller_id to undefined */
435 compressor->attached_inst = 0;
436 compressor->is_enabled = false;
437
438 /* Whenever disabling FBC make sure LPT is disabled if LPT
439 * supported */
440 if (compressor->options.bits.LPT_SUPPORT)
441 dce112_compressor_disable_lpt(compressor);
442
443 wait_for_fbc_state_changed(cp110, false);
444 }
445 }
446
dce112_compressor_is_fbc_enabled_in_hw(struct compressor * compressor,uint32_t * inst)447 bool dce112_compressor_is_fbc_enabled_in_hw(
448 struct compressor *compressor,
449 uint32_t *inst)
450 {
451 /* Check the hardware register */
452 uint32_t value;
453
454 value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
455 if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
456 if (inst != NULL)
457 *inst = compressor->attached_inst;
458 return true;
459 }
460
461 value = dm_read_reg(compressor->ctx, mmFBC_MISC);
462 if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
463 value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
464
465 if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
466 if (inst != NULL)
467 *inst =
468 compressor->attached_inst;
469 return true;
470 }
471 }
472 return false;
473 }
474
dce112_compressor_is_lpt_enabled_in_hw(struct compressor * compressor)475 bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *compressor)
476 {
477 /* Check the hardware register */
478 uint32_t value = dm_read_reg(compressor->ctx,
479 mmLOW_POWER_TILING_CONTROL);
480
481 return get_reg_field_value(
482 value,
483 LOW_POWER_TILING_CONTROL,
484 LOW_POWER_TILING_ENABLE);
485 }
486
dce112_compressor_program_compressed_surface_address_and_pitch(struct compressor * compressor,struct compr_addr_and_pitch_params * params)487 void dce112_compressor_program_compressed_surface_address_and_pitch(
488 struct compressor *compressor,
489 struct compr_addr_and_pitch_params *params)
490 {
491 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
492 uint32_t value = 0;
493 uint32_t fbc_pitch = 0;
494 uint32_t compressed_surf_address_low_part =
495 compressor->compr_surface_address.addr.low_part;
496
497 /* Clear content first. */
498 dm_write_reg(
499 compressor->ctx,
500 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
501 0);
502 dm_write_reg(compressor->ctx,
503 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
504
505 if (compressor->options.bits.LPT_SUPPORT) {
506 uint32_t lpt_alignment = lpt_size_alignment(cp110);
507
508 if (lpt_alignment != 0) {
509 compressed_surf_address_low_part =
510 ((compressed_surf_address_low_part
511 + (lpt_alignment - 1)) / lpt_alignment)
512 * lpt_alignment;
513 }
514 }
515
516 /* Write address, HIGH has to be first. */
517 dm_write_reg(compressor->ctx,
518 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
519 compressor->compr_surface_address.addr.high_part);
520 dm_write_reg(compressor->ctx,
521 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
522 compressed_surf_address_low_part);
523
524 fbc_pitch = align_to_chunks_number_per_line(
525 cp110,
526 params->source_view_width);
527
528 if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
529 fbc_pitch = fbc_pitch / 8;
530 else
531 DC_LOG_WARNING(
532 "%s: Unexpected DCE11 compression ratio",
533 __func__);
534
535 /* Clear content first. */
536 dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
537
538 /* Write FBC Pitch. */
539 set_reg_field_value(
540 value,
541 fbc_pitch,
542 GRPH_COMPRESS_PITCH,
543 GRPH_COMPRESS_PITCH);
544 dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
545
546 }
547
dce112_compressor_disable_lpt(struct compressor * compressor)548 void dce112_compressor_disable_lpt(struct compressor *compressor)
549 {
550 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
551 uint32_t value;
552 uint32_t addr;
553 uint32_t inx;
554
555 /* Disable all pipes LPT Stutter */
556 for (inx = 0; inx < 3; inx++) {
557 value =
558 dm_read_reg(
559 compressor->ctx,
560 DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
561 set_reg_field_value(
562 value,
563 0,
564 DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
565 STUTTER_ENABLE_NONLPTCH);
566 dm_write_reg(
567 compressor->ctx,
568 DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH),
569 value);
570 }
571 /* Disable Underlay pipe LPT Stutter */
572 addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
573 value = dm_read_reg(compressor->ctx, addr);
574 set_reg_field_value(
575 value,
576 0,
577 DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
578 STUTTER_ENABLE_NONLPTCH);
579 dm_write_reg(compressor->ctx, addr, value);
580
581 /* Disable LPT */
582 addr = mmLOW_POWER_TILING_CONTROL;
583 value = dm_read_reg(compressor->ctx, addr);
584 set_reg_field_value(
585 value,
586 0,
587 LOW_POWER_TILING_CONTROL,
588 LOW_POWER_TILING_ENABLE);
589 dm_write_reg(compressor->ctx, addr, value);
590
591 /* Clear selection of Channel(s) containing Compressed Surface */
592 addr = mmGMCON_LPT_TARGET;
593 value = dm_read_reg(compressor->ctx, addr);
594 set_reg_field_value(
595 value,
596 0xFFFFFFFF,
597 GMCON_LPT_TARGET,
598 STCTRL_LPT_TARGET);
599 dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value);
600 }
601
dce112_compressor_enable_lpt(struct compressor * compressor)602 void dce112_compressor_enable_lpt(struct compressor *compressor)
603 {
604 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
605 uint32_t value;
606 uint32_t addr;
607 uint32_t value_control;
608 uint32_t channels;
609
610 /* Enable LPT Stutter from Display pipe */
611 value = dm_read_reg(compressor->ctx,
612 DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
613 set_reg_field_value(
614 value,
615 1,
616 DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
617 STUTTER_ENABLE_NONLPTCH);
618 dm_write_reg(compressor->ctx,
619 DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value);
620
621 /* Enable Underlay pipe LPT Stutter */
622 addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
623 value = dm_read_reg(compressor->ctx, addr);
624 set_reg_field_value(
625 value,
626 1,
627 DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
628 STUTTER_ENABLE_NONLPTCH);
629 dm_write_reg(compressor->ctx, addr, value);
630
631 /* Selection of Channel(s) containing Compressed Surface: 0xfffffff
632 * will disable LPT.
633 * STCTRL_LPT_TARGETn corresponds to channel n. */
634 addr = mmLOW_POWER_TILING_CONTROL;
635 value_control = dm_read_reg(compressor->ctx, addr);
636 channels = get_reg_field_value(value_control,
637 LOW_POWER_TILING_CONTROL,
638 LOW_POWER_TILING_MODE);
639
640 addr = mmGMCON_LPT_TARGET;
641 value = dm_read_reg(compressor->ctx, addr);
642 set_reg_field_value(
643 value,
644 channels + 1, /* not mentioned in programming guide,
645 but follow DCE8.1 */
646 GMCON_LPT_TARGET,
647 STCTRL_LPT_TARGET);
648 dm_write_reg(compressor->ctx, addr, value);
649
650 /* Enable LPT */
651 addr = mmLOW_POWER_TILING_CONTROL;
652 value = dm_read_reg(compressor->ctx, addr);
653 set_reg_field_value(
654 value,
655 1,
656 LOW_POWER_TILING_CONTROL,
657 LOW_POWER_TILING_ENABLE);
658 dm_write_reg(compressor->ctx, addr, value);
659 }
660
dce112_compressor_program_lpt_control(struct compressor * compressor,struct compr_addr_and_pitch_params * params)661 void dce112_compressor_program_lpt_control(
662 struct compressor *compressor,
663 struct compr_addr_and_pitch_params *params)
664 {
665 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
666 uint32_t rows_per_channel;
667 uint32_t lpt_alignment;
668 uint32_t source_view_width;
669 uint32_t source_view_height;
670 uint32_t lpt_control = 0;
671
672 if (!compressor->options.bits.LPT_SUPPORT)
673 return;
674
675 lpt_control = dm_read_reg(compressor->ctx,
676 mmLOW_POWER_TILING_CONTROL);
677
678 /* POSSIBLE VALUES for Low Power Tiling Mode:
679 * 00 - Use channel 0
680 * 01 - Use Channel 0 and 1
681 * 02 - Use Channel 0,1,2,3
682 * 03 - reserved */
683 switch (compressor->lpt_channels_num) {
684 /* case 2:
685 * Use Channel 0 & 1 / Not used for DCE 11 */
686 case 1:
687 /*Use Channel 0 for LPT for DCE 11 */
688 set_reg_field_value(
689 lpt_control,
690 0,
691 LOW_POWER_TILING_CONTROL,
692 LOW_POWER_TILING_MODE);
693 break;
694 default:
695 DC_LOG_WARNING(
696 "%s: Invalid selected DRAM channels for LPT!!!",
697 __func__);
698 break;
699 }
700
701 lpt_control = lpt_memory_control_config(cp110, lpt_control);
702
703 /* Program LOW_POWER_TILING_ROWS_PER_CHAN field which depends on
704 * FBC compressed surface pitch.
705 * LOW_POWER_TILING_ROWS_PER_CHAN = Roundup ((Surface Height *
706 * Surface Pitch) / (Row Size * Number of Channels *
707 * Number of Banks)). */
708 rows_per_channel = 0;
709 lpt_alignment = lpt_size_alignment(cp110);
710 source_view_width =
711 align_to_chunks_number_per_line(
712 cp110,
713 params->source_view_width);
714 source_view_height = (params->source_view_height + 1) & (~0x1);
715
716 if (lpt_alignment != 0) {
717 rows_per_channel = source_view_width * source_view_height * 4;
718 rows_per_channel =
719 (rows_per_channel % lpt_alignment) ?
720 (rows_per_channel / lpt_alignment + 1) :
721 rows_per_channel / lpt_alignment;
722 }
723
724 set_reg_field_value(
725 lpt_control,
726 rows_per_channel,
727 LOW_POWER_TILING_CONTROL,
728 LOW_POWER_TILING_ROWS_PER_CHAN);
729
730 dm_write_reg(compressor->ctx,
731 mmLOW_POWER_TILING_CONTROL, lpt_control);
732 }
733
734 /*
735 * DCE 11 Frame Buffer Compression Implementation
736 */
737
dce112_compressor_set_fbc_invalidation_triggers(struct compressor * compressor,uint32_t fbc_trigger)738 void dce112_compressor_set_fbc_invalidation_triggers(
739 struct compressor *compressor,
740 uint32_t fbc_trigger)
741 {
742 /* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
743 * for DCE 11 regions cannot be used - does not work with S/G
744 */
745 uint32_t addr = mmFBC_CLIENT_REGION_MASK;
746 uint32_t value = dm_read_reg(compressor->ctx, addr);
747
748 set_reg_field_value(
749 value,
750 0,
751 FBC_CLIENT_REGION_MASK,
752 FBC_MEMORY_REGION_MASK);
753 dm_write_reg(compressor->ctx, addr, value);
754
755 /* Setup events when to clear all CSM entries (effectively marking
756 * current compressed data invalid)
757 * For DCE 11 CSM metadata 11111 means - "Not Compressed"
758 * Used as the initial value of the metadata sent to the compressor
759 * after invalidation, to indicate that the compressor should attempt
760 * to compress all chunks on the current pass. Also used when the chunk
761 * is not successfully written to memory.
762 * When this CSM value is detected, FBC reads from the uncompressed
763 * buffer. Set events according to passed in value, these events are
764 * valid for DCE11:
765 * - bit 0 - display register updated
766 * - bit 28 - memory write from any client except from MCIF
767 * - bit 29 - CG static screen signal is inactive
768 * In addition, DCE11.1 also needs to set new DCE11.1 specific events
769 * that are used to trigger invalidation on certain register changes,
770 * for example enabling of Alpha Compression may trigger invalidation of
771 * FBC once bit is set. These events are as follows:
772 * - Bit 2 - FBC_GRPH_COMP_EN register updated
773 * - Bit 3 - FBC_SRC_SEL register updated
774 * - Bit 4 - FBC_MIN_COMPRESSION register updated
775 * - Bit 5 - FBC_ALPHA_COMP_EN register updated
776 * - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
777 * - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
778 */
779 addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
780 value = dm_read_reg(compressor->ctx, addr);
781 set_reg_field_value(
782 value,
783 fbc_trigger |
784 FBC_IDLE_FORCE_GRPH_COMP_EN |
785 FBC_IDLE_FORCE_SRC_SEL_CHANGE |
786 FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
787 FBC_IDLE_FORCE_ALPHA_COMP_EN |
788 FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
789 FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
790 FBC_IDLE_FORCE_CLEAR_MASK,
791 FBC_IDLE_FORCE_CLEAR_MASK);
792 dm_write_reg(compressor->ctx, addr, value);
793 }
794
dce112_compressor_construct(struct dce112_compressor * compressor,struct dc_context * ctx)795 void dce112_compressor_construct(struct dce112_compressor *compressor,
796 struct dc_context *ctx)
797 {
798 struct dc_bios *bp = ctx->dc_bios;
799 struct embedded_panel_info panel_info;
800
801 compressor->base.options.raw = 0;
802 compressor->base.options.bits.FBC_SUPPORT = true;
803 compressor->base.options.bits.LPT_SUPPORT = true;
804 /* For DCE 11 always use one DRAM channel for LPT */
805 compressor->base.lpt_channels_num = 1;
806 compressor->base.options.bits.DUMMY_BACKEND = false;
807
808 /* Check if this system has more than 1 DRAM channel; if only 1 then LPT
809 * should not be supported */
810 if (compressor->base.memory_bus_width == 64)
811 compressor->base.options.bits.LPT_SUPPORT = false;
812
813 compressor->base.options.bits.CLK_GATING_DISABLED = false;
814
815 compressor->base.ctx = ctx;
816 compressor->base.embedded_panel_h_size = 0;
817 compressor->base.embedded_panel_v_size = 0;
818 compressor->base.memory_bus_width = ctx->asic_id.vram_width;
819 compressor->base.allocated_size = 0;
820 compressor->base.preferred_requested_size = 0;
821 compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
822 compressor->base.banks_num = 0;
823 compressor->base.raw_size = 0;
824 compressor->base.channel_interleave_size = 0;
825 compressor->base.dram_channels_num = 0;
826 compressor->base.lpt_channels_num = 0;
827 compressor->base.attached_inst = 0;
828 compressor->base.is_enabled = false;
829
830 if (BP_RESULT_OK ==
831 bp->funcs->get_embedded_panel_info(bp, &panel_info)) {
832 compressor->base.embedded_panel_h_size =
833 panel_info.lcd_timing.horizontal_addressable;
834 compressor->base.embedded_panel_v_size =
835 panel_info.lcd_timing.vertical_addressable;
836 }
837 }
838
dce112_compressor_create(struct dc_context * ctx)839 struct compressor *dce112_compressor_create(struct dc_context *ctx)
840 {
841 struct dce112_compressor *cp110 =
842 kzalloc(sizeof(struct dce112_compressor), GFP_KERNEL);
843
844 if (!cp110)
845 return NULL;
846
847 dce112_compressor_construct(cp110, ctx);
848 return &cp110->base;
849 }
850
dce112_compressor_destroy(struct compressor ** compressor)851 void dce112_compressor_destroy(struct compressor **compressor)
852 {
853 kfree(TO_DCE112_COMPRESSOR(*compressor));
854 *compressor = NULL;
855 }
856