1 /* $NetBSD: octeon_pow.c,v 1.10 2020/06/23 05:15:33 simonb Exp $ */
2
3 /*
4 * Copyright (c) 2007 Internet Initiative Japan, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: octeon_pow.c,v 1.10 2020/06/23 05:15:33 simonb Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34
35 #include <mips/include/locore.h>
36 #include <mips/cavium/octeonvar.h>
37 #include <mips/cavium/include/iobusvar.h>
38 #include <mips/cavium/dev/octeon_powreg.h>
39 #include <mips/cavium/dev/octeon_powvar.h>
40
41 void octpow_bootstrap(struct octeon_config *);
42
43 static void octpow_init(struct octpow_softc *);
44 static void octpow_init_regs(struct octpow_softc *);
45 static inline void octpow_config_int(struct octpow_softc *, int,
46 uint64_t, uint64_t, uint64_t);
47
48 struct octpow_softc octpow_softc;
49
50 /* -------------------------------------------------------------------------- */
51
52 /* ---- initialization and configuration */
53
54 void
octpow_bootstrap(struct octeon_config * mcp)55 octpow_bootstrap(struct octeon_config *mcp)
56 {
57 struct octpow_softc *sc = &octpow_softc;
58
59 sc->sc_regt = &mcp->mc_iobus_bust;
60 /* XXX */
61
62 octpow_init(sc);
63 }
64
65 static inline void
octpow_config_int(struct octpow_softc * sc,int group,uint64_t tc_thr,uint64_t ds_thr,uint64_t iq_thr)66 octpow_config_int(struct octpow_softc *sc, int group, uint64_t tc_thr,
67 uint64_t ds_thr, uint64_t iq_thr)
68 {
69 uint64_t wq_int_thr =
70 POW_WQ_INT_THRX_TC_EN |
71 __SHIFTIN(tc_thr, POW_WQ_INT_THRX_TC_THR) |
72 __SHIFTIN(ds_thr, POW_WQ_INT_THRX_DS_THR) |
73 __SHIFTIN(iq_thr, POW_WQ_INT_THRX_IQ_THR);
74
75 _POW_WR8(sc, POW_WQ_INT_THR0_OFFSET + (group * 8), wq_int_thr);
76 }
77
78 /*
79 * interrupt threshold configuration
80 *
81 * => DS / IQ
82 * => ...
83 * => time counter threshold
84 * => unit is 1msec
85 * => each group can set timeout
86 * => temporary disable bit
87 * => use CIU generic timer
88 */
89
90 void
octpow_config(struct octpow_softc * sc,int group)91 octpow_config(struct octpow_softc *sc, int group)
92 {
93
94 octpow_config_int(sc, group,
95 0x0f, /* TC */
96 0x00, /* DS */
97 0x00); /* IQ */
98 }
99
100 void
octpow_init(struct octpow_softc * sc)101 octpow_init(struct octpow_softc *sc)
102 {
103 octpow_init_regs(sc);
104
105 sc->sc_int_pc_base = 10000;
106 octpow_config_int_pc(sc, sc->sc_int_pc_base);
107 }
108
109 void
octpow_init_regs(struct octpow_softc * sc)110 octpow_init_regs(struct octpow_softc *sc)
111 {
112 int status;
113
114 status = bus_space_map(sc->sc_regt, POW_BASE, POW_SIZE, 0,
115 &sc->sc_regh);
116 if (status != 0)
117 panic("can't map %s space", "pow register");
118 }
119