1 /* $NetBSD: nouveau_nvkm_engine_mpeg_nv31.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $ */
2
3 /*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_mpeg_nv31.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $");
28
29 #include "nv31.h"
30
31 #include <core/client.h>
32 #include <core/gpuobj.h>
33 #include <subdev/fb.h>
34 #include <subdev/timer.h>
35 #include <engine/fifo.h>
36
37 #include <nvif/class.h>
38
39 /*******************************************************************************
40 * MPEG object classes
41 ******************************************************************************/
42
43 static int
nv31_mpeg_object_bind(struct nvkm_object * object,struct nvkm_gpuobj * parent,int align,struct nvkm_gpuobj ** pgpuobj)44 nv31_mpeg_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
45 int align, struct nvkm_gpuobj **pgpuobj)
46 {
47 int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, align,
48 false, parent, pgpuobj);
49 if (ret == 0) {
50 nvkm_kmap(*pgpuobj);
51 nvkm_wo32(*pgpuobj, 0x00, object->oclass);
52 nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
53 nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
54 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
55 nvkm_done(*pgpuobj);
56 }
57 return ret;
58 }
59
60 const struct nvkm_object_func
61 nv31_mpeg_object = {
62 .bind = nv31_mpeg_object_bind,
63 };
64
65 /*******************************************************************************
66 * PMPEG context
67 ******************************************************************************/
68
69 static void *
nv31_mpeg_chan_dtor(struct nvkm_object * object)70 nv31_mpeg_chan_dtor(struct nvkm_object *object)
71 {
72 struct nv31_mpeg_chan *chan = nv31_mpeg_chan(object);
73 struct nv31_mpeg *mpeg = chan->mpeg;
74 unsigned long flags;
75
76 spin_lock_irqsave(&mpeg->engine.lock, flags);
77 if (mpeg->chan == chan)
78 mpeg->chan = NULL;
79 spin_unlock_irqrestore(&mpeg->engine.lock, flags);
80 return chan;
81 }
82
83 static const struct nvkm_object_func
84 nv31_mpeg_chan = {
85 .dtor = nv31_mpeg_chan_dtor,
86 };
87
88 int
nv31_mpeg_chan_new(struct nvkm_fifo_chan * fifoch,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)89 nv31_mpeg_chan_new(struct nvkm_fifo_chan *fifoch,
90 const struct nvkm_oclass *oclass,
91 struct nvkm_object **pobject)
92 {
93 struct nv31_mpeg *mpeg = nv31_mpeg(oclass->engine);
94 struct nv31_mpeg_chan *chan;
95 unsigned long flags;
96 int ret = -EBUSY;
97
98 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
99 return -ENOMEM;
100 nvkm_object_ctor(&nv31_mpeg_chan, oclass, &chan->object);
101 chan->mpeg = mpeg;
102 chan->fifo = fifoch;
103 *pobject = &chan->object;
104
105 spin_lock_irqsave(&mpeg->engine.lock, flags);
106 if (!mpeg->chan) {
107 mpeg->chan = chan;
108 ret = 0;
109 }
110 spin_unlock_irqrestore(&mpeg->engine.lock, flags);
111 return ret;
112 }
113
114 /*******************************************************************************
115 * PMPEG engine/subdev functions
116 ******************************************************************************/
117
118 void
nv31_mpeg_tile(struct nvkm_engine * engine,int i,struct nvkm_fb_tile * tile)119 nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile)
120 {
121 struct nv31_mpeg *mpeg = nv31_mpeg(engine);
122 struct nvkm_device *device = mpeg->engine.subdev.device;
123
124 nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch);
125 nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit);
126 nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr);
127 }
128
129 static bool
nv31_mpeg_mthd_dma(struct nvkm_device * device,u32 mthd,u32 data)130 nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
131 {
132 struct nv31_mpeg *mpeg = nv31_mpeg(device->mpeg);
133 struct nvkm_subdev *subdev = &mpeg->engine.subdev;
134 u32 inst = data << 4;
135 u32 dma0 = nvkm_rd32(device, 0x700000 + inst);
136 u32 dma1 = nvkm_rd32(device, 0x700004 + inst);
137 u32 dma2 = nvkm_rd32(device, 0x700008 + inst);
138 u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
139 u32 size = dma1 + 1;
140
141 /* only allow linear DMA objects */
142 if (!(dma0 & 0x00002000)) {
143 nvkm_error(subdev, "inst %08x dma0 %08x dma1 %08x dma2 %08x\n",
144 inst, dma0, dma1, dma2);
145 return false;
146 }
147
148 if (mthd == 0x0190) {
149 /* DMA_CMD */
150 nvkm_mask(device, 0x00b300, 0x00010000,
151 (dma0 & 0x00030000) ? 0x00010000 : 0);
152 nvkm_wr32(device, 0x00b334, base);
153 nvkm_wr32(device, 0x00b324, size);
154 } else
155 if (mthd == 0x01a0) {
156 /* DMA_DATA */
157 nvkm_mask(device, 0x00b300, 0x00020000,
158 (dma0 & 0x00030000) ? 0x00020000 : 0);
159 nvkm_wr32(device, 0x00b360, base);
160 nvkm_wr32(device, 0x00b364, size);
161 } else {
162 /* DMA_IMAGE, VRAM only */
163 if (dma0 & 0x00030000)
164 return false;
165
166 nvkm_wr32(device, 0x00b370, base);
167 nvkm_wr32(device, 0x00b374, size);
168 }
169
170 return true;
171 }
172
173 static bool
nv31_mpeg_mthd(struct nv31_mpeg * mpeg,u32 mthd,u32 data)174 nv31_mpeg_mthd(struct nv31_mpeg *mpeg, u32 mthd, u32 data)
175 {
176 struct nvkm_device *device = mpeg->engine.subdev.device;
177 switch (mthd) {
178 case 0x190:
179 case 0x1a0:
180 case 0x1b0:
181 return mpeg->func->mthd_dma(device, mthd, data);
182 default:
183 break;
184 }
185 return false;
186 }
187
188 static void
nv31_mpeg_intr(struct nvkm_engine * engine)189 nv31_mpeg_intr(struct nvkm_engine *engine)
190 {
191 struct nv31_mpeg *mpeg = nv31_mpeg(engine);
192 struct nvkm_subdev *subdev = &mpeg->engine.subdev;
193 struct nvkm_device *device = subdev->device;
194 u32 stat = nvkm_rd32(device, 0x00b100);
195 u32 type = nvkm_rd32(device, 0x00b230);
196 u32 mthd = nvkm_rd32(device, 0x00b234);
197 u32 data = nvkm_rd32(device, 0x00b238);
198 u32 show = stat;
199 unsigned long flags;
200
201 spin_lock_irqsave(&mpeg->engine.lock, flags);
202
203 if (stat & 0x01000000) {
204 /* happens on initial binding of the object */
205 if (type == 0x00000020 && mthd == 0x0000) {
206 nvkm_mask(device, 0x00b308, 0x00000000, 0x00000000);
207 show &= ~0x01000000;
208 }
209
210 if (type == 0x00000010) {
211 if (nv31_mpeg_mthd(mpeg, mthd, data))
212 show &= ~0x01000000;
213 }
214 }
215
216 nvkm_wr32(device, 0x00b100, stat);
217 nvkm_wr32(device, 0x00b230, 0x00000001);
218
219 if (show) {
220 nvkm_error(subdev, "ch %d [%s] %08x %08x %08x %08x\n",
221 mpeg->chan ? mpeg->chan->fifo->chid : -1,
222 mpeg->chan ? mpeg->chan->object.client->name :
223 "unknown", stat, type, mthd, data);
224 }
225
226 spin_unlock_irqrestore(&mpeg->engine.lock, flags);
227 }
228
229 int
nv31_mpeg_init(struct nvkm_engine * mpeg)230 nv31_mpeg_init(struct nvkm_engine *mpeg)
231 {
232 struct nvkm_subdev *subdev = &mpeg->subdev;
233 struct nvkm_device *device = subdev->device;
234
235 /* VPE init */
236 nvkm_wr32(device, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
237 nvkm_wr32(device, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
238
239 /* PMPEG init */
240 nvkm_wr32(device, 0x00b32c, 0x00000000);
241 nvkm_wr32(device, 0x00b314, 0x00000100);
242 nvkm_wr32(device, 0x00b220, 0x00000031);
243 nvkm_wr32(device, 0x00b300, 0x02001ec1);
244 nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001);
245
246 nvkm_wr32(device, 0x00b100, 0xffffffff);
247 nvkm_wr32(device, 0x00b140, 0xffffffff);
248
249 if (nvkm_msec(device, 2000,
250 if (!(nvkm_rd32(device, 0x00b200) & 0x00000001))
251 break;
252 ) < 0) {
253 nvkm_error(subdev, "timeout %08x\n",
254 nvkm_rd32(device, 0x00b200));
255 return -EBUSY;
256 }
257
258 return 0;
259 }
260
261 static void *
nv31_mpeg_dtor(struct nvkm_engine * engine)262 nv31_mpeg_dtor(struct nvkm_engine *engine)
263 {
264 return nv31_mpeg(engine);
265 }
266
267 static const struct nvkm_engine_func
268 nv31_mpeg_ = {
269 .dtor = nv31_mpeg_dtor,
270 .init = nv31_mpeg_init,
271 .intr = nv31_mpeg_intr,
272 .tile = nv31_mpeg_tile,
273 .fifo.cclass = nv31_mpeg_chan_new,
274 .sclass = {
275 { -1, -1, NV31_MPEG, &nv31_mpeg_object },
276 {}
277 }
278 };
279
280 int
nv31_mpeg_new_(const struct nv31_mpeg_func * func,struct nvkm_device * device,int index,struct nvkm_engine ** pmpeg)281 nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device,
282 int index, struct nvkm_engine **pmpeg)
283 {
284 struct nv31_mpeg *mpeg;
285
286 if (!(mpeg = kzalloc(sizeof(*mpeg), GFP_KERNEL)))
287 return -ENOMEM;
288 mpeg->func = func;
289 *pmpeg = &mpeg->engine;
290
291 return nvkm_engine_ctor(&nv31_mpeg_, device, index,
292 true, &mpeg->engine);
293 }
294
295 static const struct nv31_mpeg_func
296 nv31_mpeg = {
297 .mthd_dma = nv31_mpeg_mthd_dma,
298 };
299
300 int
nv31_mpeg_new(struct nvkm_device * device,int index,struct nvkm_engine ** pmpeg)301 nv31_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
302 {
303 return nv31_mpeg_new_(&nv31_mpeg, device, index, pmpeg);
304 }
305