1 /* $NetBSD: nouveau_dispnv04_dfp.c,v 1.3 2021/12/18 23:45:32 riastradh Exp $ */
2
3 /*
4 * Copyright 2003 NVIDIA, Corporation
5 * Copyright 2006 Dave Airlie
6 * Copyright 2007 Maarten Maathuis
7 * Copyright 2007-2009 Stuart Bennett
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv04_dfp.c,v 1.3 2021/12/18 23:45:32 riastradh Exp $");
31
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fourcc.h>
34
35 #include "nouveau_drv.h"
36 #include "nouveau_reg.h"
37 #include "nouveau_encoder.h"
38 #include "nouveau_connector.h"
39 #include "nouveau_crtc.h"
40 #include "hw.h"
41 #include "nvreg.h"
42
43 #include <drm/i2c/sil164.h>
44
45 #include <subdev/i2c.h>
46
47 #define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \
48 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \
49 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
50 #define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE | \
51 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE | \
52 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
53
is_fpc_off(uint32_t fpc)54 static inline bool is_fpc_off(uint32_t fpc)
55 {
56 return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) ==
57 FP_TG_CONTROL_OFF);
58 }
59
nv04_dfp_get_bound_head(struct drm_device * dev,struct dcb_output * dcbent)60 int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent)
61 {
62 /* special case of nv_read_tmds to find crtc associated with an output.
63 * this does not give a correct answer for off-chip dvi, but there's no
64 * use for such an answer anyway
65 */
66 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
67
68 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
69 NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
70 return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
71 }
72
nv04_dfp_bind_head(struct drm_device * dev,struct dcb_output * dcbent,int head,bool dl)73 void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
74 int head, bool dl)
75 {
76 /* The BIOS scripts don't do this for us, sadly
77 * Luckily we do know the values ;-)
78 *
79 * head < 0 indicates we wish to force a setting with the overrideval
80 * (for VT restore etc.)
81 */
82
83 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
84 uint8_t tmds04 = 0x80;
85
86 if (head != ramdac)
87 tmds04 = 0x88;
88
89 if (dcbent->type == DCB_OUTPUT_LVDS)
90 tmds04 |= 0x01;
91
92 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
93
94 if (dl) /* dual link */
95 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
96 }
97
nv04_dfp_disable(struct drm_device * dev,int head)98 void nv04_dfp_disable(struct drm_device *dev, int head)
99 {
100 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
101
102 if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
103 FP_TG_CONTROL_ON) {
104 /* digital remnants must be cleaned before new crtc
105 * values programmed. delay is time for the vga stuff
106 * to realise it's in control again
107 */
108 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
109 FP_TG_CONTROL_OFF);
110 msleep(50);
111 }
112 /* don't inadvertently turn it on when state written later */
113 crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
114 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &=
115 ~NV_CIO_CRE_LCD_ROUTE_MASK;
116 }
117
nv04_dfp_update_fp_control(struct drm_encoder * encoder,int mode)118 void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
119 {
120 struct drm_device *dev = encoder->dev;
121 struct drm_crtc *crtc;
122 struct nouveau_crtc *nv_crtc;
123 uint32_t *fpc;
124
125 if (mode == DRM_MODE_DPMS_ON) {
126 nv_crtc = nouveau_crtc(encoder->crtc);
127 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
128
129 if (is_fpc_off(*fpc)) {
130 /* using saved value is ok, as (is_digital && dpms_on &&
131 * fp_control==OFF) is (at present) *only* true when
132 * fpc's most recent change was by below "off" code
133 */
134 *fpc = nv_crtc->dpms_saved_fp_control;
135 }
136
137 nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
138 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
139 } else {
140 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
141 nv_crtc = nouveau_crtc(crtc);
142 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
143
144 nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
145 if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
146 nv_crtc->dpms_saved_fp_control = *fpc;
147 /* cut the FP output */
148 *fpc &= ~FP_TG_CONTROL_ON;
149 *fpc |= FP_TG_CONTROL_OFF;
150 NVWriteRAMDAC(dev, nv_crtc->index,
151 NV_PRAMDAC_FP_TG_CONTROL, *fpc);
152 }
153 }
154 }
155 }
156
get_tmds_slave(struct drm_encoder * encoder)157 static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder)
158 {
159 struct drm_device *dev = encoder->dev;
160 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
161 struct drm_encoder *slave;
162
163 if (dcb->type != DCB_OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP)
164 return NULL;
165
166 /* Some BIOSes (e.g. the one in a Quadro FX1000) report several
167 * TMDS transmitters at the same I2C address, in the same I2C
168 * bus. This can still work because in that case one of them is
169 * always hard-wired to a reasonable configuration using straps,
170 * and the other one needs to be programmed.
171 *
172 * I don't think there's a way to know which is which, even the
173 * blob programs the one exposed via I2C for *both* heads, so
174 * let's do the same.
175 */
176 list_for_each_entry(slave, &dev->mode_config.encoder_list, head) {
177 struct dcb_output *slave_dcb = nouveau_encoder(slave)->dcb;
178
179 if (slave_dcb->type == DCB_OUTPUT_TMDS && get_slave_funcs(slave) &&
180 slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr)
181 return slave;
182 }
183
184 return NULL;
185 }
186
nv04_dfp_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)187 static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
188 const struct drm_display_mode *mode,
189 struct drm_display_mode *adjusted_mode)
190 {
191 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
192 struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
193
194 if (!nv_connector->native_mode ||
195 nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
196 mode->hdisplay > nv_connector->native_mode->hdisplay ||
197 mode->vdisplay > nv_connector->native_mode->vdisplay) {
198 nv_encoder->mode = *adjusted_mode;
199
200 } else {
201 nv_encoder->mode = *nv_connector->native_mode;
202 adjusted_mode->clock = nv_connector->native_mode->clock;
203 }
204
205 return true;
206 }
207
nv04_dfp_prepare_sel_clk(struct drm_device * dev,struct nouveau_encoder * nv_encoder,int head)208 static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
209 struct nouveau_encoder *nv_encoder, int head)
210 {
211 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
212 uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000;
213
214 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
215 return;
216
217 /* SEL_CLK is only used on the primary ramdac
218 * It toggles spread spectrum PLL output and sets the bindings of PLLs
219 * to heads on digital outputs
220 */
221 if (head)
222 state->sel_clk |= bits1618;
223 else
224 state->sel_clk &= ~bits1618;
225
226 /* nv30:
227 * bit 0 NVClk spread spectrum on/off
228 * bit 2 MemClk spread spectrum on/off
229 * bit 4 PixClk1 spread spectrum on/off toggle
230 * bit 6 PixClk2 spread spectrum on/off toggle
231 *
232 * nv40 (observations from bios behaviour and mmio traces):
233 * bits 4&6 as for nv30
234 * bits 5&7 head dependent as for bits 4&6, but do not appear with 4&6;
235 * maybe a different spread mode
236 * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
237 * The logic behind turning spread spectrum on/off in the first place,
238 * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
239 * entry has the necessary info)
240 */
241 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
242 int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
243
244 state->sel_clk &= ~0xf0;
245 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
246 }
247 }
248
nv04_dfp_prepare(struct drm_encoder * encoder)249 static void nv04_dfp_prepare(struct drm_encoder *encoder)
250 {
251 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
252 const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
253 struct drm_device *dev = encoder->dev;
254 int head = nouveau_crtc(encoder->crtc)->index;
255 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
256 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
257 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
258
259 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
260
261 nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
262
263 *cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3;
264
265 if (nv_two_heads(dev)) {
266 if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
267 *cr_lcd |= head ? 0x0 : 0x8;
268 else {
269 *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
270 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
271 *cr_lcd |= 0x30;
272 if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
273 /* avoid being connected to both crtcs */
274 *cr_lcd_oth &= ~0x30;
275 NVWriteVgaCrtc(dev, head ^ 1,
276 NV_CIO_CRE_LCD__INDEX,
277 *cr_lcd_oth);
278 }
279 }
280 }
281 }
282
283
nv04_dfp_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)284 static void nv04_dfp_mode_set(struct drm_encoder *encoder,
285 struct drm_display_mode *mode,
286 struct drm_display_mode *adjusted_mode)
287 {
288 struct drm_device *dev = encoder->dev;
289 struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
290 struct nouveau_drm *drm = nouveau_drm(dev);
291 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
292 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
293 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
294 struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
295 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
296 struct drm_display_mode *output_mode = &nv_encoder->mode;
297 struct drm_connector *connector = &nv_connector->base;
298 const struct drm_framebuffer *fb = encoder->crtc->primary->fb;
299 uint32_t mode_ratio, panel_ratio;
300
301 NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index);
302 drm_mode_debug_printmodeline(output_mode);
303
304 /* Initialize the FP registers in this CRTC. */
305 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
306 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
307 if (!nv_gf4_disp_arch(dev) ||
308 (output_mode->hsync_start - output_mode->hdisplay) >=
309 drm->vbios.digital_min_front_porch)
310 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
311 else
312 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1;
313 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
314 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
315 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
316 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
317
318 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
319 regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
320 regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
321 regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
322 regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
323 regp->fp_vert_regs[FP_VALID_START] = 0;
324 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
325
326 /* bit26: a bit seen on some g7x, no as yet discernable purpose */
327 regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
328 (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
329 /* Deal with vsync/hsync polarity */
330 /* LVDS screens do set this, but modes with +ve syncs are very rare */
331 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
332 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
333 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
334 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
335 /* panel scaling first, as native would get set otherwise */
336 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
337 nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER) /* panel handles it */
338 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
339 else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
340 adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
341 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
342 else /* gpu needs to scale */
343 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
344 if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
345 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
346 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
347 output_mode->clock > 165000)
348 regp->fp_control |= (2 << 24);
349 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
350 bool duallink = false, dummy;
351 if (nv_connector->edid &&
352 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
353 duallink = (((u8 *)nv_connector->edid)[121] == 2);
354 } else {
355 nouveau_bios_parse_lvds_table(dev, output_mode->clock,
356 &duallink, &dummy);
357 }
358
359 if (duallink)
360 regp->fp_control |= (8 << 28);
361 } else
362 if (output_mode->clock > 165000)
363 regp->fp_control |= (8 << 28);
364
365 regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
366 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
367 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
368 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
369 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
370 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
371 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
372
373 /* We want automatic scaling */
374 regp->fp_debug_1 = 0;
375 /* This can override HTOTAL and VTOTAL */
376 regp->fp_debug_2 = 0;
377
378 /* Use 20.12 fixed point format to avoid floats */
379 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
380 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
381 /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
382 * get treated the same as SCALE_FULLSCREEN */
383 if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
384 mode_ratio != panel_ratio) {
385 uint32_t diff, scale;
386 bool divide_by_2 = nv_gf4_disp_arch(dev);
387
388 if (mode_ratio < panel_ratio) {
389 /* vertical needs to expand to glass size (automatic)
390 * horizontal needs to be scaled at vertical scale factor
391 * to maintain aspect */
392
393 scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
394 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
395 XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE);
396
397 /* restrict area of screen used, horizontally */
398 diff = output_mode->hdisplay -
399 output_mode->vdisplay * mode_ratio / (1 << 12);
400 regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
401 regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
402 }
403
404 if (mode_ratio > panel_ratio) {
405 /* horizontal needs to expand to glass size (automatic)
406 * vertical needs to be scaled at horizontal scale factor
407 * to maintain aspect */
408
409 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
410 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
411 XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE);
412
413 /* restrict area of screen used, vertically */
414 diff = output_mode->vdisplay -
415 (1 << 12) * output_mode->hdisplay / mode_ratio;
416 regp->fp_vert_regs[FP_VALID_START] += diff / 2;
417 regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
418 }
419 }
420
421 /* Output property. */
422 if ((nv_connector->dithering_mode == DITHERING_MODE_ON) ||
423 (nv_connector->dithering_mode == DITHERING_MODE_AUTO &&
424 fb->format->depth > connector->display_info.bpc * 3)) {
425 if (drm->client.device.info.chipset == 0x11)
426 regp->dither = savep->dither | 0x00010000;
427 else {
428 int i;
429 regp->dither = savep->dither | 0x00000001;
430 for (i = 0; i < 3; i++) {
431 regp->dither_regs[i] = 0xe4e4e4e4;
432 regp->dither_regs[i + 3] = 0x44444444;
433 }
434 }
435 } else {
436 if (drm->client.device.info.chipset != 0x11) {
437 /* reset them */
438 int i;
439 for (i = 0; i < 3; i++) {
440 regp->dither_regs[i] = savep->dither_regs[i];
441 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
442 }
443 }
444 regp->dither = savep->dither;
445 }
446
447 regp->fp_margin_color = 0;
448 }
449
nv04_dfp_commit(struct drm_encoder * encoder)450 static void nv04_dfp_commit(struct drm_encoder *encoder)
451 {
452 struct drm_device *dev = encoder->dev;
453 struct nouveau_drm *drm = nouveau_drm(dev);
454 const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
455 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
456 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
457 struct dcb_output *dcbe = nv_encoder->dcb;
458 int head = nouveau_crtc(encoder->crtc)->index;
459 struct drm_encoder *slave_encoder;
460
461 if (dcbe->type == DCB_OUTPUT_TMDS)
462 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
463 else if (dcbe->type == DCB_OUTPUT_LVDS)
464 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
465
466 /* update fp_control state for any changes made by scripts,
467 * so correct value is written at DPMS on */
468 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
469 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
470
471 /* This could use refinement for flatpanels, but it should work this way */
472 if (drm->client.device.info.chipset < 0x44)
473 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
474 else
475 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
476
477 /* Init external transmitters */
478 slave_encoder = get_tmds_slave(encoder);
479 if (slave_encoder)
480 get_slave_funcs(slave_encoder)->mode_set(
481 slave_encoder, &nv_encoder->mode, &nv_encoder->mode);
482
483 helper->dpms(encoder, DRM_MODE_DPMS_ON);
484
485 NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n",
486 nouveau_encoder_connector_get(nv_encoder)->base.name,
487 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
488 }
489
nv04_dfp_update_backlight(struct drm_encoder * encoder,int mode)490 static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
491 {
492 #ifdef __powerpc__
493 struct drm_device *dev = encoder->dev;
494 struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
495
496 /* BIOS scripts usually take care of the backlight, thanks
497 * Apple for your consistency.
498 */
499 if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 ||
500 dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) {
501 if (mode == DRM_MODE_DPMS_ON) {
502 nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);
503 nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);
504 } else {
505 nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
506 nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 0);
507 }
508 }
509 #endif
510 }
511
is_powersaving_dpms(int mode)512 static inline bool is_powersaving_dpms(int mode)
513 {
514 return mode != DRM_MODE_DPMS_ON && mode != NV_DPMS_CLEARED;
515 }
516
nv04_lvds_dpms(struct drm_encoder * encoder,int mode)517 static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
518 {
519 struct drm_device *dev = encoder->dev;
520 struct drm_crtc *crtc = encoder->crtc;
521 struct nouveau_drm *drm = nouveau_drm(dev);
522 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
523 bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
524
525 if (nv_encoder->last_dpms == mode)
526 return;
527 nv_encoder->last_dpms = mode;
528
529 NV_DEBUG(drm, "Setting dpms mode %d on lvds encoder (output %d)\n",
530 mode, nv_encoder->dcb->index);
531
532 if (was_powersaving && is_powersaving_dpms(mode))
533 return;
534
535 if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
536 /* when removing an output, crtc may not be set, but PANEL_OFF
537 * must still be run
538 */
539 int head = crtc ? nouveau_crtc(crtc)->index :
540 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
541
542 if (mode == DRM_MODE_DPMS_ON) {
543 call_lvds_script(dev, nv_encoder->dcb, head,
544 LVDS_PANEL_ON, nv_encoder->mode.clock);
545 } else
546 /* pxclk of 0 is fine for PANEL_OFF, and for a
547 * disconnected LVDS encoder there is no native_mode
548 */
549 call_lvds_script(dev, nv_encoder->dcb, head,
550 LVDS_PANEL_OFF, 0);
551 }
552
553 nv04_dfp_update_backlight(encoder, mode);
554 nv04_dfp_update_fp_control(encoder, mode);
555
556 if (mode == DRM_MODE_DPMS_ON)
557 nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
558 else {
559 nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
560 nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
561 }
562 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
563 }
564
nv04_tmds_dpms(struct drm_encoder * encoder,int mode)565 static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
566 {
567 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
568 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
569
570 if (nv_encoder->last_dpms == mode)
571 return;
572 nv_encoder->last_dpms = mode;
573
574 NV_DEBUG(drm, "Setting dpms mode %d on tmds encoder (output %d)\n",
575 mode, nv_encoder->dcb->index);
576
577 nv04_dfp_update_backlight(encoder, mode);
578 nv04_dfp_update_fp_control(encoder, mode);
579 }
580
nv04_dfp_save(struct drm_encoder * encoder)581 static void nv04_dfp_save(struct drm_encoder *encoder)
582 {
583 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
584 struct drm_device *dev = encoder->dev;
585
586 if (nv_two_heads(dev))
587 nv_encoder->restore.head =
588 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
589 }
590
nv04_dfp_restore(struct drm_encoder * encoder)591 static void nv04_dfp_restore(struct drm_encoder *encoder)
592 {
593 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
594 struct drm_device *dev = encoder->dev;
595 int head = nv_encoder->restore.head;
596
597 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
598 struct nouveau_connector *connector =
599 nouveau_encoder_connector_get(nv_encoder);
600
601 if (connector && connector->native_mode)
602 call_lvds_script(dev, nv_encoder->dcb, head,
603 LVDS_PANEL_ON,
604 connector->native_mode->clock);
605
606 } else if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) {
607 int clock = nouveau_hw_pllvals_to_clk
608 (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);
609
610 run_tmds_table(dev, nv_encoder->dcb, head, clock);
611 }
612
613 nv_encoder->last_dpms = NV_DPMS_CLEARED;
614 }
615
nv04_dfp_destroy(struct drm_encoder * encoder)616 static void nv04_dfp_destroy(struct drm_encoder *encoder)
617 {
618 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
619
620 if (get_slave_funcs(encoder))
621 get_slave_funcs(encoder)->destroy(encoder);
622
623 drm_encoder_cleanup(encoder);
624 kfree(nv_encoder);
625 }
626
nv04_tmds_slave_init(struct drm_encoder * encoder)627 static void nv04_tmds_slave_init(struct drm_encoder *encoder)
628 {
629 struct drm_device *dev = encoder->dev;
630 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
631 struct nouveau_drm *drm = nouveau_drm(dev);
632 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
633 struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_PRI);
634 struct nvkm_i2c_bus_probe info[] = {
635 {
636 {
637 .type = "sil164",
638 .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
639 .platform_data = &(struct sil164_encoder_params) {
640 SIL164_INPUT_EDGE_RISING
641 }
642 }, 0
643 },
644 { }
645 };
646 int type;
647
648 if (!nv_gf4_disp_arch(dev) || !bus || get_tmds_slave(encoder))
649 return;
650
651 type = nvkm_i2c_bus_probe(bus, "TMDS transmitter", info, NULL, NULL);
652 if (type < 0)
653 return;
654
655 drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
656 &bus->i2c, &info[type].dev);
657 }
658
659 static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
660 .dpms = nv04_lvds_dpms,
661 .mode_fixup = nv04_dfp_mode_fixup,
662 .prepare = nv04_dfp_prepare,
663 .commit = nv04_dfp_commit,
664 .mode_set = nv04_dfp_mode_set,
665 .detect = NULL,
666 };
667
668 static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = {
669 .dpms = nv04_tmds_dpms,
670 .mode_fixup = nv04_dfp_mode_fixup,
671 .prepare = nv04_dfp_prepare,
672 .commit = nv04_dfp_commit,
673 .mode_set = nv04_dfp_mode_set,
674 .detect = NULL,
675 };
676
677 static const struct drm_encoder_funcs nv04_dfp_funcs = {
678 .destroy = nv04_dfp_destroy,
679 };
680
681 int
nv04_dfp_create(struct drm_connector * connector,struct dcb_output * entry)682 nv04_dfp_create(struct drm_connector *connector, struct dcb_output *entry)
683 {
684 const struct drm_encoder_helper_funcs *helper;
685 struct nouveau_encoder *nv_encoder = NULL;
686 struct drm_encoder *encoder;
687 int type;
688
689 switch (entry->type) {
690 case DCB_OUTPUT_TMDS:
691 type = DRM_MODE_ENCODER_TMDS;
692 helper = &nv04_tmds_helper_funcs;
693 break;
694 case DCB_OUTPUT_LVDS:
695 type = DRM_MODE_ENCODER_LVDS;
696 helper = &nv04_lvds_helper_funcs;
697 break;
698 default:
699 return -EINVAL;
700 }
701
702 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
703 if (!nv_encoder)
704 return -ENOMEM;
705
706 nv_encoder->enc_save = nv04_dfp_save;
707 nv_encoder->enc_restore = nv04_dfp_restore;
708
709 encoder = to_drm_encoder(nv_encoder);
710
711 nv_encoder->dcb = entry;
712 nv_encoder->or = ffs(entry->or) - 1;
713
714 drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type, NULL);
715 drm_encoder_helper_add(encoder, helper);
716
717 encoder->possible_crtcs = entry->heads;
718 encoder->possible_clones = 0;
719
720 if (entry->type == DCB_OUTPUT_TMDS &&
721 entry->location != DCB_LOC_ON_CHIP)
722 nv04_tmds_slave_init(encoder);
723
724 drm_connector_attach_encoder(connector, encoder);
725 return 0;
726 }
727