1 /* $NetBSD: intel_rps_types.h,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */ 2 3 /* 4 * SPDX-License-Identifier: MIT 5 * 6 * Copyright © 2019 Intel Corporation 7 */ 8 9 #ifndef INTEL_RPS_TYPES_H 10 #define INTEL_RPS_TYPES_H 11 12 #include <linux/atomic.h> 13 #include <linux/ktime.h> 14 #include <linux/mutex.h> 15 #include <linux/types.h> 16 #include <linux/workqueue.h> 17 18 struct intel_ips { 19 u64 last_count1; 20 unsigned long last_time1; 21 unsigned long chipset_power; 22 u64 last_count2; 23 u64 last_time2; 24 unsigned long gfx_power; 25 u8 corr; 26 27 int c, m; 28 }; 29 30 struct intel_rps_ei { 31 ktime_t ktime; 32 u32 render_c0; 33 u32 media_c0; 34 }; 35 36 struct intel_rps { 37 struct mutex lock; /* protects enabling and the worker */ 38 39 /* 40 * work, interrupts_enabled and pm_iir are protected by 41 * dev_priv->irq_lock 42 */ 43 struct work_struct work; 44 bool enabled; 45 bool active; 46 u32 pm_iir; 47 48 /* PM interrupt bits that should never be masked */ 49 u32 pm_intrmsk_mbz; 50 u32 pm_events; 51 52 /* Frequencies are stored in potentially platform dependent multiples. 53 * In other words, *_freq needs to be multiplied by X to be interesting. 54 * Soft limits are those which are used for the dynamic reclocking done 55 * by the driver (raise frequencies under heavy loads, and lower for 56 * lighter loads). Hard limits are those imposed by the hardware. 57 * 58 * A distinction is made for overclocking, which is never enabled by 59 * default, and is considered to be above the hard limit if it's 60 * possible at all. 61 */ 62 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 63 u8 last_freq; /* Last SWREQ frequency */ 64 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 65 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 66 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 67 u8 min_freq; /* AKA RPn. Minimum frequency */ 68 u8 boost_freq; /* Frequency to request when wait boosting */ 69 u8 idle_freq; /* Frequency to request when we are idle */ 70 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 71 u8 rp1_freq; /* "less than" RP0 power/freqency */ 72 u8 rp0_freq; /* Non-overclocked max frequency. */ 73 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ 74 75 int last_adj; 76 77 struct { 78 struct mutex mutex; 79 80 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode; 81 unsigned int interactive; 82 83 u8 up_threshold; /* Current %busy required to uplock */ 84 u8 down_threshold; /* Current %busy required to downclock */ 85 } power; 86 87 atomic_t num_waiters; 88 atomic_t boosts; 89 90 /* manual wa residency calculations */ 91 struct intel_rps_ei ei; 92 struct intel_ips ips; 93 }; 94 95 #endif /* INTEL_RPS_TYPES_H */ 96