xref: /netbsd-src/sys/arch/newsmips/newsmips/news5000.c (revision cecde1b5250be188abd1ea1de5507e00d7ddefbe)
1 /*	$NetBSD: news5000.c,v 1.23 2024/06/02 13:28:44 andvar Exp $	*/
2 
3 /*-
4  * Copyright (C) 1999 SHIMIZU Ryo.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. The name of the author may not be used to endorse or promote products
15  *    derived from this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: news5000.c,v 1.23 2024/06/02 13:28:44 andvar Exp $");
31 
32 #define __INTR_PRIVATE
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/timetc.h>
37 #include <sys/cpu.h>
38 #include <sys/intr.h>
39 
40 #include <mips/locore.h>
41 
42 #include <machine/adrsmap.h>
43 
44 #include <newsmips/apbus/apbusvar.h>
45 #include <newsmips/newsmips/machid.h>
46 
47 static void news5000_level1_intr(void);
48 static void news5000_level0_intr(void);
49 
50 static void news5000_enable_intr(void);
51 static void news5000_disable_intr(void);
52 static void news5000_enable_timer(void);
53 static void news5000_readidrom(uint8_t *);
54 static void news5000_tc_init(void);
55 static uint32_t news5000_getfreerun(struct timecounter *);
56 
57 /*
58  * This is a mask of bits to clear in the SR when we go to a
59  * given interrupt priority level.
60  */
61 static const struct ipl_sr_map news5000_ipl_sr_map = {
62     .sr_bits = {
63 	[IPL_NONE] =		0,
64 	[IPL_SOFTCLOCK] =	MIPS_SOFT_INT_MASK_0,
65 	[IPL_SOFTNET] =		MIPS_SOFT_INT_MASK,
66 	[IPL_VM] =		MIPS_SOFT_INT_MASK
67 				| MIPS_INT_MASK_0
68 				| MIPS_INT_MASK_1,
69 	[IPL_SCHED] =		MIPS_SOFT_INT_MASK
70 				| MIPS_INT_MASK_0
71 				| MIPS_INT_MASK_1
72 				| MIPS_INT_MASK_2,
73 	[IPL_DDB] =		MIPS_INT_MASK,
74 	[IPL_HIGH] =		MIPS_INT_MASK,
75     },
76 };
77 
78 /*
79  * Handle news5000 interrupts.
80  */
81 void
news5000_intr(int ppl,vaddr_t pc,uint32_t status)82 news5000_intr(int ppl, vaddr_t pc, uint32_t status)
83 {
84 	uint32_t ipending;
85 	int ipl;
86 
87 	while (ppl < (ipl = splintr(&ipending))) {
88 
89 		if (ipending & MIPS_INT_MASK_2) {
90 #ifdef DEBUG
91 			static int l2cnt = 0;
92 #endif
93 			uint32_t int2stat;
94 
95 			int2stat = *(volatile uint32_t *)NEWS5000_INTST2;
96 
97 #ifdef DEBUG
98 			l2cnt++;
99 			if (l2cnt == 50) {
100 				*(volatile uint32_t *)NEWS5000_LED_SEC = 1;
101 			}
102 			if (l2cnt == 100) {
103 				*(volatile uint32_t *)NEWS5000_LED_SEC = 0;
104 				l2cnt = 0;
105 			}
106 #endif
107 
108 			if (int2stat & NEWS5000_INT2_TIMER0) {
109 				struct clockframe cf = {
110 					.pc = pc,
111 					.sr = status,
112 					.intr = (curcpu()->ci_idepth > 1),
113 				};
114 				*(volatile uint32_t *)NEWS5000_TIMER0 = 1;
115 				hardclock(&cf);
116 				intrcnt[HARDCLOCK_INTR]++;
117 			}
118 
119 			apbus_wbflush();
120 		}
121 
122 		if (ipending & MIPS_INT_MASK_5) {
123 			uint32_t int5stat;
124 
125 			int5stat = *(volatile u_int *)NEWS5000_INTST5;
126 			printf("level5 interrupt (%08x)\n", int5stat);
127 
128 			apbus_wbflush();
129 		}
130 
131 		if (ipending & MIPS_INT_MASK_4) {
132 			uint32_t int4stat;
133 
134 			int4stat = *(volatile uint32_t *)NEWS5000_INTST4;
135 			printf("level4 interrupt (%08x)\n", int4stat);
136 			if (int4stat & NEWS5000_INT4_APBUS) {
137 				uint32_t stat;
138 
139 				stat = *(volatile uint32_t *)NEWS5000_APBUS_INTST;
140 				printf("APbus error 0x%04x\n", stat & 0xffff);
141 				if (stat & NEWS5000_APBUS_INT_DMAADDR) {
142 					printf("DMA Address Error: "
143 					    "slot=%x, addr=0x%08x\n",
144 					    *(volatile uint32_t *)NEWS5000_APBUS_DER_S,
145 					    *(volatile uint32_t *)NEWS5000_APBUS_DER_A);
146 				}
147 				if (stat & NEWS5000_APBUS_INT_RDTIMEO)
148 					printf("IO Read Timeout: addr=0x%08x\n",
149 					    *(volatile uint32_t *)NEWS5000_APBUS_BER_A);
150 				if (stat & NEWS5000_APBUS_INT_WRTIMEO)
151 					printf("IO Write Timeout: addr=0x%08x\n",
152 					    *(volatile uint32_t *)NEWS5000_APBUS_BER_A);
153 				*(volatile uint32_t *)0xb4c00014 = stat;
154 			}
155 
156 			apbus_wbflush();
157 		}
158 
159 		if (ipending & MIPS_INT_MASK_3) {
160 			uint32_t int3stat;
161 
162 			int3stat = *(volatile uint32_t *)NEWS5000_INTST3;
163 			printf("level3 interrupt (%08x)\n", int3stat);
164 
165 			apbus_wbflush();
166 		}
167 
168 		if (ipending & MIPS_INT_MASK_1) {
169 			news5000_level1_intr();
170 			apbus_wbflush();
171 		}
172 
173 		if (ipending & MIPS_INT_MASK_0) {
174 			news5000_level0_intr();
175 			apbus_wbflush();
176 		}
177 	}
178 }
179 
180 
181 static void
news5000_level1_intr(void)182 news5000_level1_intr(void)
183 {
184 	uint32_t int1stat;
185 
186 	int1stat = *(volatile uint32_t *)NEWS5000_INTST1;
187 
188 	if (int1stat) {
189 		if (apbus_intr_dispatch(1, int1stat) == 0)
190 			printf("level1_intr: no handler (mask 0x%04x)\n",
191 			       int1stat);
192 	} else
193 		printf("level1 stray interrupt?\n");
194 }
195 
196 static void
news5000_level0_intr(void)197 news5000_level0_intr(void)
198 {
199 	uint32_t int0stat;
200 
201 	int0stat = *(volatile uint32_t *)NEWS5000_INTST0;
202 
203 	if (int0stat) {
204 		if (apbus_intr_dispatch(0, int0stat) == 0)
205 			printf("level0_intr: no handler (mask 0x%04x)\n",
206 			       int0stat);
207 	} else
208 		printf("level0 stray interrupt?\n");
209 }
210 
211 static void
news5000_enable_intr(void)212 news5000_enable_intr(void)
213 {
214 
215 	/* INT0 and INT1 has been enabled at attach */
216 	/* INT2 -- It's not a time to enable timer yet. */
217 	/* INT3 -- not used for NWS-5000 */
218 
219 	*(volatile uint32_t *)NEWS5000_INTEN4 = NEWS5000_INT4_APBUS;
220 	*(volatile uint32_t *)NEWS5000_APBUS_INTMSK = 0xffff;
221 
222 	/* INT5 -- currently ignored */
223 	*(volatile uint32_t *)NEWS5000_INTEN5 = 0;
224 }
225 
226 static void
news5000_disable_intr(void)227 news5000_disable_intr(void)
228 {
229 
230 	*(volatile uint32_t *)NEWS5000_INTEN0 = 0;
231 	*(volatile uint32_t *)NEWS5000_INTEN1 = 0;
232 	*(volatile uint32_t *)NEWS5000_INTEN2 = 0;
233 	*(volatile uint32_t *)NEWS5000_INTEN3 = 0;
234 	*(volatile uint32_t *)NEWS5000_INTEN4 = 0;
235 	*(volatile uint32_t *)NEWS5000_INTEN5 = 0;
236 }
237 
238 static void
news5000_enable_timer(void)239 news5000_enable_timer(void)
240 {
241 
242 	news5000_tc_init();
243 
244 	/* enable timer interrupt */
245 	*(volatile uint32_t *)NEWS5000_INTEN2 = NEWS5000_INT2_TIMER0;
246 }
247 
248 static uint32_t
news5000_getfreerun(struct timecounter * tc)249 news5000_getfreerun(struct timecounter *tc)
250 {
251 	return *(volatile uint32_t *)NEWS5000_FREERUN;
252 }
253 
254 static void
news5000_tc_init(void)255 news5000_tc_init(void)
256 {
257 	static struct timecounter tc = {
258 		.tc_get_timecount = news5000_getfreerun,
259 		.tc_frequency = 1000000,
260 		.tc_counter_mask = ~0,
261 		.tc_name = "news5000_freerun",
262 		.tc_quality = 100,
263 	};
264 
265 	tc_init(&tc);
266 }
267 
268 
269 static void
news5000_readidrom(uint8_t * rom)270 news5000_readidrom(uint8_t *rom)
271 {
272 	uint32_t *p = (void *)NEWS5000_IDROM;
273 	int i;
274 
275 	for (i = 0; i < sizeof(struct idrom); i++, p += 2)
276 		*rom++ = ((*p & 0x0f) << 4) + (*(p + 1) & 0x0f);
277 }
278 
279 extern struct idrom idrom;
280 
281 void
news5000_init(void)282 news5000_init(void)
283 {
284 
285 	ipl_sr_map = news5000_ipl_sr_map;
286 
287 	enable_intr = news5000_enable_intr;
288 	disable_intr = news5000_disable_intr;
289 	enable_timer = news5000_enable_timer;
290 
291 	news_wbflush = (uint32_t *)NEWS5000_WBFLUSH;
292 
293 	news5000_readidrom((uint8_t *)&idrom);
294 	hostid = idrom.id_serial;
295 
296 	/* XXX reset uPD72067 FDC to avoid spurious interrupts */
297 #define NEWS5000_FDC_FDOUT 0xbed20000
298 #define FDO_FRST 0x04
299 	*(volatile uint8_t *)NEWS5000_FDC_FDOUT = FDO_FRST;
300 }
301