xref: /netbsd-src/sys/arch/mipsco/mipsco/interrupt.c (revision e5fbc36ada28f9b9a5836ecffaf4a06aa1ebb687)
1 /*	$NetBSD: interrupt.c,v 1.12 2023/12/20 15:29:05 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Wayne Knowles
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #define __INTR_PRIVATE
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.12 2023/12/20 15:29:05 thorpej Exp $");
35 
36 #include <sys/param.h>
37 #include <sys/intr.h>
38 #include <sys/lwp.h>
39 #include <sys/cpu.h>
40 
41 #include <machine/sysconf.h>
42 
43 void
cpu_intr(int ppl,vaddr_t pc,uint32_t status)44 cpu_intr(int ppl, vaddr_t pc, uint32_t status)
45 {
46 	uint32_t ipending;
47 	int ipl;
48 
49 	curcpu()->ci_data.cpu_nintr++;
50 
51 	while (ppl < (ipl = splintr(&ipending))) {
52 		/* device interrupts */
53 		(*platform.iointr)(status, pc, ipending);
54 	}
55 
56 }
57 
58 const struct ipl_sr_map mipsco_ipl_sr_map = {
59     .sr_bits = {
60 	[IPL_NONE] = 0,
61 	[IPL_SOFTCLOCK] = MIPS_INT_MASK_SPL_SOFT0,
62 	[IPL_SOFTNET] = MIPS_INT_MASK_SPL_SOFT1,
63 	[IPL_VM] = MIPS_INT_MASK_SPL2,
64 	[IPL_SCHED] = MIPS_INT_MASK_SPL2,
65 	[IPL_HIGH] = MIPS_INT_MASK,
66     },
67 };
68