xref: /netbsd-src/sys/arch/mips/mips/mips3_clock.c (revision 482eef70502290f7cbd2cb9a24a4f41e6bacd98d)
1 /*	$NetBSD: mips3_clock.c,v 1.15 2020/05/29 12:30:40 rin Exp $	*/
2 
3 /*
4  * Copyright (c) 1988 University of Utah.
5  * Copyright (c) 1992, 1993
6  *	The Regents of the University of California.  All rights reserved.
7  *
8  * This code is derived from software contributed to Berkeley by
9  * the Systems Programming Group of the University of Utah Computer
10  * Science Department and Ralph Campbell.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  * 3. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  * from: Utah Hdr: clock.c 1.18 91/01/21
37  *
38  *	@(#)clock.c	8.1 (Berkeley) 6/10/93
39  */
40 
41 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
42 
43 #include "opt_multiprocessor.h"
44 
45 __KERNEL_RCSID(0, "$NetBSD: mips3_clock.c,v 1.15 2020/05/29 12:30:40 rin Exp $");
46 
47 #include <sys/param.h>
48 #include <sys/cpu.h>
49 #include <sys/intr.h>
50 #include <sys/kernel.h>
51 #include <sys/timetc.h>
52 
53 #include <mips/mips3_clock.h>
54 
55 #include <mips/locore.h>
56 
57 /*
58  * Wait for at least "n" microseconds.
59  */
60 void
mips3_delay(int n)61 mips3_delay(int n)
62 {
63 	u_long divisor_delay;
64 	uint32_t cur, last, delta, usecs;
65 
66 	last = mips3_cp0_count_read();
67 	delta = usecs = 0;
68 
69 	divisor_delay = curcpu()->ci_divisor_delay;
70 	if (divisor_delay == 0) {
71 		/*
72 		 * Frequency values in curcpu() are not initialized.
73 		 * Assume faster frequency since longer delays are harmless.
74 		 * Note CPU_MIPS_DOUBLE_COUNT is ignored here.
75 		 */
76 #define FAST_FREQ	(300 * 1000 * 1000)	/* fast enough? */
77 		divisor_delay = FAST_FREQ / (1000 * 1000);
78 	}
79 
80 	while (n > usecs) {
81 		cur = mips3_cp0_count_read();
82 
83 		/*
84 		 * The MIPS3 CP0 counter always counts upto UINT32_MAX,
85 		 * so no need to check wrapped around case.
86 		 */
87 		delta += (cur - last);
88 
89 		last = cur;
90 
91 		while (delta >= divisor_delay) {
92 			/*
93 			 * delta is not so larger than divisor_delay here,
94 			 * and using DIV/DIVU ops could be much slower.
95 			 * (though longer delay may be harmless)
96 			 */
97 			usecs++;
98 			delta -= divisor_delay;
99 		}
100 	}
101 }
102 
103 /*
104  * Support for using the MIPS 3 clock as a timecounter.
105  */
106 
107 void
mips3_init_tc(void)108 mips3_init_tc(void)
109 {
110 #if !defined(MULTIPROCESSOR)
111 	static struct timecounter tc =  {
112 		.tc_get_timecount = (timecounter_get_t *)mips3_cp0_count_read,
113 		.tc_counter_mask = ~0u,
114 		.tc_name = "mips3_cp0_counter",
115 		.tc_quality = 100,
116 	};
117 
118 	tc.tc_frequency = curcpu()->ci_cpu_freq;
119 	if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) {
120 		tc.tc_frequency /= 2;
121 	}
122 	curcpu()->ci_cctr_freq = tc.tc_frequency;
123 
124 	tc_init(&tc);
125 #endif
126 }
127 
128 __weak_alias(delay, mips3_delay);
129