1 /* $NetBSD: amdgpu_dcn20_mmhubbub.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */
2
3 /*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn20_mmhubbub.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $");
31
32 #include "reg_helper.h"
33 #include "resource.h"
34 #include "mcif_wb.h"
35 #include "dcn20_mmhubbub.h"
36
37
38 #define REG(reg)\
39 mcif_wb20->mcif_wb_regs->reg
40
41 #define CTX \
42 mcif_wb20->base.ctx
43
44 #undef FN
45 #define FN(reg_name, field_name) \
46 mcif_wb20->mcif_wb_shift->field_name, mcif_wb20->mcif_wb_mask->field_name
47
48 #define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8
49 #define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
50
51 /* wbif programming guide:
52 * 1. set up wbif parameter:
53 * unsigned long long luma_address[4]; //4 frame buffer
54 * unsigned long long chroma_address[4];
55 * unsigned int luma_pitch;
56 * unsigned int chroma_pitch;
57 * unsigned int warmup_pitch=0x10; //256B align, the page size is 4KB when it is 0x10
58 * unsigned int slice_lines; //slice size
59 * unsigned int time_per_pixel; // time per pixel, in ns
60 * unsigned int arbitration_slice; // 0: 512 bytes 1: 1024 bytes 2: 2048 Bytes
61 * unsigned int max_scaled_time; // used for QOS generation
62 * unsigned int swlock=0x0;
63 * unsigned int cli_watermark[4]; //4 group urgent watermark
64 * unsigned int pstate_watermark[4]; //4 group pstate watermark
65 * unsigned int sw_int_en; // Software interrupt enable, frame end and overflow
66 * unsigned int sw_slice_int_en; // slice end interrupt enable
67 * unsigned int sw_overrun_int_en; // overrun error interrupt enable
68 * unsigned int vce_int_en; // VCE interrupt enable, frame end and overflow
69 * unsigned int vce_slice_int_en; // VCE slice end interrupt enable, frame end and overflow
70 *
71 * 2. configure wbif register
72 * a. call mmhubbub_config_wbif()
73 *
74 * 3. Enable wbif
75 * call set_wbif_bufmgr_enable();
76 *
77 * 4. wbif_dump_status(), option, for debug purpose
78 * the bufmgr status can show the progress of write back, can be used for debug purpose
79 */
80
mmhubbub2_config_mcif_buf(struct mcif_wb * mcif_wb,struct mcif_buf_params * params,unsigned int dest_height)81 static void mmhubbub2_config_mcif_buf(struct mcif_wb *mcif_wb,
82 struct mcif_buf_params *params,
83 unsigned int dest_height)
84 {
85 struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
86
87 /* sw lock buffer0~buffer3, default is 0 */
88 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock);
89
90 /* buffer address for packing mode or Luma in planar mode */
91 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
92 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));
93 /* right eye sub-buffer address offset for packing mode or Luma in planar mode */
94 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0);
95
96 /* buffer address for Chroma in planar mode (unused in packing mode) */
97 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));
98 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));
99 /* right eye offset for packing mode or Luma in planar mode */
100 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0);
101
102 /* buffer address for packing mode or Luma in planar mode */
103 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));
104 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));
105 /* right eye sub-buffer address offset for packing mode or Luma in planar mode */
106 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0);
107
108 /* buffer address for Chroma in planar mode (unused in packing mode) */
109 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));
110 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));
111 /* right eye offset for packing mode or Luma in planar mode */
112 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, 0);
113
114 /* buffer address for packing mode or Luma in planar mode */
115 REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));
116 REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));
117 /* right eye sub-buffer address offset for packing mode or Luma in planar mode */
118 REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, 0);
119
120 /* buffer address for Chroma in planar mode (unused in packing mode) */
121 REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));
122 REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));
123 /* right eye offset for packing mode or Luma in planar mode */
124 REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, 0);
125
126 /* buffer address for packing mode or Luma in planar mode */
127 REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));
128 REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));
129 /* right eye sub-buffer address offset for packing mode or Luma in planar mode */
130 REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, 0);
131
132 /* buffer address for Chroma in planar mode (unused in packing mode) */
133 REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));
134 REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));
135 /* right eye offset for packing mode or Luma in planar mode */
136 REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, 0);
137
138 /* setup luma & chroma size
139 * should be enough to contain a whole frame Luma data,
140 * the programmed value is frame buffer size [27:8], 256-byte aligned
141 */
142 REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height);
143 REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height);
144
145 /* enable address fence */
146 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1);
147
148 /* setup pitch, the programmed value is [15:8], 256B align */
149 REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, params->luma_pitch >> 8,
150 MCIF_WB_BUF_CHROMA_PITCH, params->chroma_pitch >> 8);
151
152 /* Set pitch for MC cache warm up mode */
153 /* Pitch is 256 bytes aligned. The default pitch is 4K */
154 /* default is 0x10 */
155 REG_UPDATE(MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, params->warmup_pitch);
156 }
157
mmhubbub2_config_mcif_arb(struct mcif_wb * mcif_wb,struct mcif_arb_params * params)158 static void mmhubbub2_config_mcif_arb(struct mcif_wb *mcif_wb,
159 struct mcif_arb_params *params)
160 {
161 struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
162
163 /* Programmed by the video driver based on the CRTC timing (for DWB) */
164 REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel);
165
166 /* Programming dwb watermark */
167 /* Watermark to generate urgent in MCIF_WB_CLI, value is determined by MCIF_WB_CLI_WATERMARK_MASK. */
168 /* Program in ns. A formula will be provided in the pseudo code to calculate the value. */
169 REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x0);
170 /* urgent_watermarkA */
171 REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[0]);
172 REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x1);
173 /* urgent_watermarkB */
174 REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[1]);
175 REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x2);
176 /* urgent_watermarkC */
177 REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[2]);
178 REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x3);
179 /* urgent_watermarkD */
180 REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[3]);
181
182 /* Programming nb pstate watermark */
183 /* nbp_state_change_watermarkA */
184 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);
185 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
186 NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[0]);
187 /* nbp_state_change_watermarkB */
188 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);
189 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
190 NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[1]);
191 /* nbp_state_change_watermarkC */
192 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);
193 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
194 NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[2]);
195 /* nbp_state_change_watermarkD */
196 REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);
197 REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
198 NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[3]);
199
200 /* max_scaled_time */
201 REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time);
202
203 /* slice_lines */
204 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);
205
206 /* Set arbitration unit for Luma/Chroma */
207 /* arb_unit=2 should be chosen for more efficiency */
208 /* Arbitration size, 0: 512 bytes 1: 1024 bytes 2: 2048 Bytes */
209 REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, params->arbitration_slice);
210 }
211
mmhubbub2_config_mcif_irq(struct mcif_wb * mcif_wb,struct mcif_irq_params * params)212 void mmhubbub2_config_mcif_irq(struct mcif_wb *mcif_wb,
213 struct mcif_irq_params *params)
214 {
215 struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
216
217 /* Set interrupt mask */
218 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, params->sw_int_en);
219 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, params->sw_slice_int_en);
220 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, params->sw_overrun_int_en);
221
222 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, params->vce_int_en);
223 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, params->vce_slice_int_en);
224 }
225
mmhubbub2_enable_mcif(struct mcif_wb * mcif_wb)226 void mmhubbub2_enable_mcif(struct mcif_wb *mcif_wb)
227 {
228 struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
229
230 /* Enable Mcifwb */
231 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 1);
232 }
233
mmhubbub2_disable_mcif(struct mcif_wb * mcif_wb)234 void mmhubbub2_disable_mcif(struct mcif_wb *mcif_wb)
235 {
236 struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
237
238 /* disable buffer manager */
239 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 0);
240 }
241
242 /* set which group of pstate watermark to use and set wbif watermark change request */
243 /*
244 static void mmhubbub2_wbif_watermark_change_req(struct mcif_wb *mcif_wb, unsigned int wm_set)
245 {
246 struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
247 uint32_t change_req;
248
249 REG_GET(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, &change_req);
250 change_req = (change_req == 0) ? 1 : 0;
251 REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, wm_set);
252 REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, change_req);
253 }
254 */
255 /* Set watermark change interrupt disable bit */
256 /*
257 static void mmhubbub2_set_wbif_watermark_change_int_disable(struct mcif_wb *mcif_wb, unsigned int ack_int_dis)
258 {
259 struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
260
261 REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, ack_int_dis);
262 }
263 */
264 /* Read watermark change interrupt status */
265 /*
266 unsigned int mmhubbub2_get_wbif_watermark_change_int_status(struct mcif_wb *mcif_wb)
267 {
268 struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
269 uint32_t irq_status;
270
271 REG_GET(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, &irq_status);
272 return irq_status;
273 }
274 */
275
mcifwb2_dump_frame(struct mcif_wb * mcif_wb,struct mcif_buf_params * mcif_params,enum dwb_scaler_mode out_format,unsigned int dest_width,unsigned int dest_height,struct mcif_wb_frame_dump_info * dump_info,unsigned char * luma_buffer,unsigned char * chroma_buffer,unsigned char * dest_luma_buffer,unsigned char * dest_chroma_buffer)276 void mcifwb2_dump_frame(struct mcif_wb *mcif_wb,
277 struct mcif_buf_params *mcif_params,
278 enum dwb_scaler_mode out_format,
279 unsigned int dest_width,
280 unsigned int dest_height,
281 struct mcif_wb_frame_dump_info *dump_info,
282 unsigned char *luma_buffer,
283 unsigned char *chroma_buffer,
284 unsigned char *dest_luma_buffer,
285 unsigned char *dest_chroma_buffer)
286 {
287 struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
288
289 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf);
290
291 memcpy(dest_luma_buffer, luma_buffer, mcif_params->luma_pitch * dest_height);
292 memcpy(dest_chroma_buffer, chroma_buffer, mcif_params->chroma_pitch * dest_height / 2);
293
294 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0);
295
296 dump_info->format = out_format;
297 dump_info->width = dest_width;
298 dump_info->height = dest_height;
299 dump_info->luma_pitch = mcif_params->luma_pitch;
300 dump_info->chroma_pitch = mcif_params->chroma_pitch;
301 dump_info->size = dest_height * (mcif_params->luma_pitch + mcif_params->chroma_pitch);
302 }
303
304 const struct mcif_wb_funcs dcn20_mmhubbub_funcs = {
305 .enable_mcif = mmhubbub2_enable_mcif,
306 .disable_mcif = mmhubbub2_disable_mcif,
307 .config_mcif_buf = mmhubbub2_config_mcif_buf,
308 .config_mcif_arb = mmhubbub2_config_mcif_arb,
309 .config_mcif_irq = mmhubbub2_config_mcif_irq,
310 .dump_frame = mcifwb2_dump_frame,
311 };
312
dcn20_mmhubbub_construct(struct dcn20_mmhubbub * mcif_wb20,struct dc_context * ctx,const struct dcn20_mmhubbub_registers * mcif_wb_regs,const struct dcn20_mmhubbub_shift * mcif_wb_shift,const struct dcn20_mmhubbub_mask * mcif_wb_mask,int inst)313 void dcn20_mmhubbub_construct(struct dcn20_mmhubbub *mcif_wb20,
314 struct dc_context *ctx,
315 const struct dcn20_mmhubbub_registers *mcif_wb_regs,
316 const struct dcn20_mmhubbub_shift *mcif_wb_shift,
317 const struct dcn20_mmhubbub_mask *mcif_wb_mask,
318 int inst)
319 {
320 mcif_wb20->base.ctx = ctx;
321
322 mcif_wb20->base.inst = inst;
323 mcif_wb20->base.funcs = &dcn20_mmhubbub_funcs;
324
325 mcif_wb20->mcif_wb_regs = mcif_wb_regs;
326 mcif_wb20->mcif_wb_shift = mcif_wb_shift;
327 mcif_wb20->mcif_wb_mask = mcif_wb_mask;
328 }
329