1 /* $NetBSD: radeonfb.c,v 1.117 2021/08/08 12:17:37 tnn Exp $ */
2
3 /*-
4 * Copyright (c) 2006 Itronix Inc.
5 * All rights reserved.
6 *
7 * Written by Garrett D'Amore for Itronix Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of Itronix Inc. may not be used to endorse
18 * or promote products derived from this software without specific
19 * prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS
22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and
36 * does not endorse, this software. ATI will not be responsible or liable
37 * for any actual or alleged damage or loss caused by or in connection with
38 * the use of or reliance on this software.
39 */
40
41 /*
42 * Portions of this code were taken from XFree86's Radeon driver, which bears
43 * this notice:
44 *
45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
46 * VA Linux Systems Inc., Fremont, California.
47 *
48 * All Rights Reserved.
49 *
50 * Permission is hereby granted, free of charge, to any person obtaining
51 * a copy of this software and associated documentation files (the
52 * "Software"), to deal in the Software without restriction, including
53 * without limitation on the rights to use, copy, modify, merge,
54 * publish, distribute, sublicense, and/or sell copies of the Software,
55 * and to permit persons to whom the Software is furnished to do so,
56 * subject to the following conditions:
57 *
58 * The above copyright notice and this permission notice (including the
59 * next paragraph) shall be included in all copies or substantial
60 * portions of the Software.
61 *
62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
69 * DEALINGS IN THE SOFTWARE.
70 */
71
72 #include <sys/cdefs.h>
73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.117 2021/08/08 12:17:37 tnn Exp $");
74
75 #include <sys/param.h>
76 #include <sys/systm.h>
77 #include <sys/device.h>
78 #include <sys/malloc.h>
79 #include <sys/bus.h>
80 #include <sys/kernel.h>
81 #include <sys/lwp.h>
82 #include <sys/kauth.h>
83 #include <sys/kmem.h>
84
85 #include <dev/wscons/wsdisplayvar.h>
86 #include <dev/wscons/wsconsio.h>
87 #include <dev/wsfont/wsfont.h>
88 #include <dev/rasops/rasops.h>
89 #include <dev/videomode/videomode.h>
90 #include <dev/videomode/edidvar.h>
91 #include <dev/wscons/wsdisplay_vconsvar.h>
92 #include <dev/pci/wsdisplay_pci.h>
93 #include <dev/wscons/wsdisplay_glyphcachevar.h>
94
95 #include <dev/pci/pcidevs.h>
96 #include <dev/pci/pcireg.h>
97 #include <dev/pci/pcivar.h>
98 #include <dev/pci/pciio.h>
99 #include <dev/pci/radeonfbreg.h>
100 #include <dev/pci/radeonfbvar.h>
101 #include "opt_radeonfb.h"
102 #include "opt_vcons.h"
103
104 #ifdef RADEONFB_DEPTH_32
105 #define RADEONFB_DEFAULT_DEPTH 32
106 #else
107 #define RADEONFB_DEFAULT_DEPTH 8
108 #endif
109
110 static int radeonfb_match(device_t, cfdata_t, void *);
111 static void radeonfb_attach(device_t, device_t, void *);
112 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int,
113 struct lwp *);
114 static paddr_t radeonfb_mmap(void *, void *, off_t, int);
115 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t);
116 static void radeonfb_loadbios(struct radeonfb_softc *,
117 const struct pci_attach_args *);
118
119 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *,
120 uintmax_t);
121 static int radeonfb_getclocks(struct radeonfb_softc *);
122 static int radeonfb_gettmds(struct radeonfb_softc *);
123 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t,
124 uint32_t *, uint32_t *, int);
125 /* flags for radeonfb_calc_dividers */
126 #define NO_ODD_FBDIV 1
127
128 static int radeonfb_getconnectors(struct radeonfb_softc *);
129 static const struct videomode *radeonfb_modelookup(const char *);
130 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *);
131 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int);
132 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int);
133 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int, int);
134 static void radeonfb_modeswitch(struct radeonfb_display *);
135 static void radeonfb_setcrtc(struct radeonfb_display *, int);
136 static void radeonfb_init_misc(struct radeonfb_softc *);
137 static void radeonfb_set_fbloc(struct radeonfb_softc *);
138 static void radeonfb_init_palette(struct radeonfb_display *);
139 static void radeonfb_r300cg_workaround(struct radeonfb_softc *);
140
141 static int radeonfb_isblank(struct radeonfb_display *);
142 static void radeonfb_blank(struct radeonfb_display *, int);
143 static int radeonfb_set_cursor(struct radeonfb_display *,
144 struct wsdisplay_cursor *);
145 static int radeonfb_set_curpos(struct radeonfb_display *,
146 struct wsdisplay_curpos *);
147 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int);
148 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *);
149 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *);
150
151 /* acceleration support */
152 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty,
153 int width, int height, uint32_t color);
154 static void radeonfb_rectfill_a(void *, int, int, int, int, long);
155 static void radeonfb_bitblt(void *, int srcx, int srcy,
156 int dstx, int dsty, int width, int height, int rop);
157
158 /* hw cursor support */
159 static void radeonfb_cursor_cmap(struct radeonfb_display *);
160 static void radeonfb_cursor_shape(struct radeonfb_display *);
161 static void radeonfb_cursor_position(struct radeonfb_display *);
162 static void radeonfb_cursor_visible(struct radeonfb_display *);
163 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned);
164
165 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int);
166 static void radeonfb_engine_idle(struct radeonfb_softc *);
167 static void radeonfb_engine_flush(struct radeonfb_softc *);
168 static void radeonfb_engine_reset(struct radeonfb_softc *);
169 static void radeonfb_engine_init(struct radeonfb_display *);
170 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused;
171
172 static void radeonfb_eraserows(void *, int, int, long);
173 static void radeonfb_erasecols(void *, int, int, int, long);
174 static void radeonfb_copyrows(void *, int, int, int);
175 static void radeonfb_copycols(void *, int, int, int, int);
176 static void radeonfb_cursor(void *, int, int, int);
177 static void radeonfb_putchar(void *, int, int, unsigned, long);
178 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long);
179 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long);
180 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR
181 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long);
182 #endif
183
184 static int radeonfb_set_backlight(struct radeonfb_display *, int);
185 static int radeonfb_get_backlight(struct radeonfb_display *);
186 static void radeonfb_switch_backlight(struct radeonfb_display *, int);
187 static void radeonfb_lvds_callout(void *);
188
189 static void radeonfb_brightness_up(device_t);
190 static void radeonfb_brightness_down(device_t);
191
192 static struct videomode *radeonfb_best_refresh(struct videomode *,
193 struct videomode *);
194 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *,
195 uint16_t *, int);
196 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *,
197 struct radeonfb_port *, int, int);
198
199 static int radeonfb_drm_print(void *, const char *);
200
201 #ifdef RADEONFB_DEBUG
202 int radeon_debug = 1;
203 #define DPRINTF(x) \
204 if (radeon_debug) printf x
205 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r)))
206 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r)))
207 #else
208 #define DPRINTF(x)
209 #define PRINTREG(r)
210 #define PRINTPLL(r)
211 #endif
212
213 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1))
214
215 #ifndef RADEON_DEFAULT_MODE
216 /* any reasonably modern display should handle this */
217 #define RADEON_DEFAULT_MODE "1024x768x60"
218 #endif
219
220 extern const u_char rasops_cmap[768];
221
222 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE;
223
224 static struct {
225 int size; /* minimum memory size (MB) */
226 int maxx; /* maximum x dimension */
227 int maxy; /* maximum y dimension */
228 int maxbpp; /* maximum bpp */
229 int maxdisp; /* maximum logical display count */
230 } radeonfb_limits[] = {
231 { 32, 2048, 1536, 32, 2 },
232 { 16, 1600, 1200, 32, 2 },
233 { 8, 1600, 1200, 32, 1 },
234 { 0, 0, 0, 0, 0 },
235 };
236
237 static struct wsscreen_descr radeonfb_stdscreen = {
238 "fb", /* name */
239 0, 0, /* ncols, nrows */
240 NULL, /* textops */
241 8, 16, /* fontwidth, fontheight */
242 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */
243 0, /* modecookie */
244 };
245
246 struct wsdisplay_accessops radeonfb_accessops = {
247 radeonfb_ioctl,
248 radeonfb_mmap,
249 NULL, /* vcons_alloc_screen */
250 NULL, /* vcons_free_screen */
251 NULL, /* vcons_show_screen */
252 NULL, /* load_font */
253 NULL, /* pollc */
254 NULL, /* scroll */
255 };
256
257 static struct {
258 uint16_t devid;
259 uint16_t family;
260 uint16_t flags;
261 } radeonfb_devices[] =
262 {
263 /* R100 family */
264 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 },
265 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 },
266 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 },
267 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 },
268
269 /* RV100 family */
270 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB },
271 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB },
272 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 },
273 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 },
274
275 /* RS100 family */
276 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 },
277 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB },
278
279 /* RS200/RS250 family */
280 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB },
281 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 },
282 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB },
283 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 },
284
285 /* R200 family */
286 /* add more R200 products? , 5148 */
287 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 },
288 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 },
289 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 },
290 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 },
291 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 },
292
293 /* RV200 family */
294 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB },
295 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB },
296 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 },
297 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 },
298
299 /* RV250 family */
300 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 },
301 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 },
302 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB },
303 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB },
304 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB },
305
306 /* RS300 family */
307 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 },
308 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 },
309 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 },
310 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB },
311
312 /* RV280 family */
313 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 },
314 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 },
315 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 },
316 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 },
317 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 },
318 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB },
319 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB },
320
321 /* R300 family */
322 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 },
323 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 },
324 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 },
325 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 },
326 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 },
327 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 },
328 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 },
329 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 },
330
331 /* RV350/RV360 family */
332 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 },
333 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 },
334 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 },
335 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 },
336 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 },
337 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 },
338 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB },
339 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB },
340 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB },
341 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB },
342 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB },
343 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB },
344
345 /* R350/R360 family */
346 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 },
347 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 },
348 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 },
349 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 },
350 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 },
351 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 },
352 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 },
353 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 },
354
355 /* RV380/RV370 family */
356 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB },
357 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB },
358 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 },
359 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 },
360 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB },
361 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB },
362 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 },
363 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 },
364 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 },
365 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 },
366
367 #if notyet
368 /* R420/R423 family */
369 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 },
370 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 },
371 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 },
372 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 },
373 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 },
374 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 },
375 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB },
376 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 },
377 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 },
378 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 },
379 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 },
380 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 },
381 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 },
382 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 },
383 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 },
384 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 },
385 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 },
386 #endif
387
388 /* R5xx family */
389 { 0x7240, RADEON_R580, RFB_IS_AVIVO },
390 { 0, 0, 0 }
391 };
392
393 static struct {
394 int divider;
395 int mask;
396 } radeonfb_dividers[] = {
397 { 16, 5 },
398 { 12, 7 },
399 { 8, 3 },
400 { 6, 6 },
401 { 4, 2 },
402 { 3, 4 },
403 { 2, 1 },
404 { 1, 0 },
405 { 0, 0 }
406 };
407
408 /*
409 * This table taken from X11.
410 */
411 static const struct {
412 int family;
413 struct radeon_tmds_pll plls[4];
414 } radeonfb_tmds_pll[] = {
415 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}},
416 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}},
417 { RADEON_RS100, {{0, 0}}},
418 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}},
419 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}},
420 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}},
421 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}},
422 { RADEON_RS300, {{0, 0}}},
423 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}, {-1, 0x40111}}},
424 { RADEON_R300, {{-1, 0xb01cb}}},
425 { RADEON_R350, {{-1, 0xb01cb}}},
426 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}},
427 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}},
428 { RADEON_R420, {{-1, 0xb01cb}}},
429 { RADEON_R580, {{-1, 0xb01cb}}}, /* XXX likely bogus */
430 };
431
432 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */
433
434
435 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc),
436 radeonfb_match, radeonfb_attach, NULL, NULL);
437
438 static int
radeonfb_match(device_t parent,cfdata_t match,void * aux)439 radeonfb_match(device_t parent, cfdata_t match, void *aux)
440 {
441 const struct pci_attach_args *pa = aux;
442 int i;
443
444 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI)
445 return 0;
446
447 for (i = 0; radeonfb_devices[i].devid; i++) {
448 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid)
449 return 100; /* high to defeat VGA/VESA */
450 }
451
452 return 0;
453 }
454
455 static void
radeonfb_attach(device_t parent,device_t dev,void * aux)456 radeonfb_attach(device_t parent, device_t dev, void *aux)
457 {
458 struct radeonfb_softc *sc = device_private(dev);
459 const struct pci_attach_args *pa = aux;
460 const char *mptr;
461 bus_size_t bsz;
462 pcireg_t screg;
463 int i, j, fg, bg, ul, flags;
464 uint32_t v;
465
466 sc->sc_dev = dev;
467 sc->sc_id = pa->pa_id;
468 for (i = 0; radeonfb_devices[i].devid; i++) {
469 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid)
470 break;
471 }
472
473 pci_aprint_devinfo(pa, NULL);
474
475 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev))));
476
477 KASSERT(radeonfb_devices[i].devid != 0);
478 sc->sc_pt = pa->pa_tag;
479 sc->sc_iot = pa->pa_iot;
480 sc->sc_pc = pa->pa_pc;
481 sc->sc_family = radeonfb_devices[i].family;
482 sc->sc_flags = radeonfb_devices[i].flags;
483 sc->sc_bios = NULL;
484 sc->sc_biossz = 0;
485
486 /* enable memory and IO access */
487 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG);
488 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
489 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg);
490
491 /*
492 * Some flags are general to entire chip families, and rather
493 * than clutter up the table with them, we go ahead and set
494 * them here.
495 */
496 switch (sc->sc_family) {
497 case RADEON_RS100:
498 case RADEON_RS200:
499 sc->sc_flags |= RFB_IGP | RFB_RV100;
500 break;
501
502 case RADEON_RV100:
503 case RADEON_RV200:
504 case RADEON_RV250:
505 case RADEON_RV280:
506 sc->sc_flags |= RFB_RV100;
507 break;
508
509 case RADEON_RS300:
510 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100;
511 break;
512
513 case RADEON_R300:
514 case RADEON_RV350:
515 case RADEON_R350:
516 case RADEON_RV380:
517 case RADEON_R420:
518 case RADEON_R580:
519 /* newer chips */
520 sc->sc_flags |= RFB_R300;
521 break;
522
523 case RADEON_R100:
524 sc->sc_flags |= RFB_NCRTC2;
525 break;
526 }
527
528 if ((sc->sc_family == RADEON_RV200) ||
529 (sc->sc_family == RADEON_RV250) ||
530 (sc->sc_family == RADEON_RV280) ||
531 (sc->sc_family == RADEON_RV350)) {
532 bool inverted = 0;
533 /* backlight level is linear */
534 DPRINTF(("found RV* chip, backlight is supposedly linear\n"));
535 prop_dictionary_get_bool(device_properties(sc->sc_dev),
536 "backlight_level_reverted", &inverted);
537 if (inverted) {
538 DPRINTF(("nope, it's inverted\n"));
539 sc->sc_flags |= RFB_INV_BLIGHT;
540 }
541 } else
542 sc->sc_flags |= RFB_INV_BLIGHT;
543
544 /*
545 * XXX: to support true multihead, this must change.
546 */
547 sc->sc_ndisplays = 1;
548
549 /* XXX: */
550 if (!HAS_CRTC2(sc)) {
551 sc->sc_ndisplays = 1;
552 }
553
554 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0,
555 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr,
556 &sc->sc_regsz) != 0) {
557 aprint_error("%s: unable to map registers!\n", XNAME(sc));
558 goto error;
559 }
560
561 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM,
562 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0)
563 {
564 aprint_error("%s: unable to find ROM!\n", XNAME(sc));
565 goto error;
566 }
567 sc->sc_romt = sc->sc_memt;
568
569 sc->sc_mapped = TRUE;
570
571 /* scratch register test... */
572 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) ||
573 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) {
574 aprint_error("%s: scratch register test failed!\n", XNAME(sc));
575 goto error;
576 }
577
578 PRINTREG(RADEON_CRTC_EXT_CNTL);
579 PRINTREG(RADEON_CRTC_GEN_CNTL);
580 PRINTREG(RADEON_CRTC2_GEN_CNTL);
581 PRINTREG(RADEON_DISP_OUTPUT_CNTL);
582 PRINTREG(RADEON_DAC_CNTL2);
583 PRINTREG(RADEON_BIOS_4_SCRATCH);
584 PRINTREG(RADEON_FP_GEN_CNTL);
585 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL);
586 PRINTREG(RADEON_FP2_GEN_CNTL);
587 PRINTREG(RADEON_TMDS_CNTL);
588 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL);
589 PRINTREG(RADEON_TMDS_PLL_CNTL);
590 PRINTREG(RADEON_LVDS_GEN_CNTL);
591 PRINTREG(RADEON_DISP_HW_DEBUG);
592 if (!IS_AVIVO(sc)) {
593 /*
594 XXX: We can't print this, as it's not correctly aligned
595 PRINTREG(RADEON_PIXCLKS_CNTL);
596 */
597 PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID);
598 PRINTREG(RADEON_FP_H_SYNC_STRT_WID);
599 PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID);
600 PRINTREG(RADEON_FP_H2_SYNC_STRT_WID);
601 }
602 /*
603 * XXX
604 * This was if (IS_RV100()), which is set for all pre-R3xx chips.
605 * I suspect this only makes sense on Sun XVR-100 with firmware that doesn't
606 * support DVI, so for now let's restrict it to only actual RV100
607 */
608 if (sc->sc_family == RADEON_RV100)
609 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27);
610
611 /* XXX
612 * according to xf86-video-radeon R3xx has this bit backwards
613 */
614 if (IS_R300(sc)) {
615 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL,
616 0,
617 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST));
618 } else {
619 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL,
620 RADEON_TMDS_TRANSMITTER_PLLEN,
621 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST));
622 }
623
624 radeonfb_i2c_init(sc);
625
626 radeonfb_loadbios(sc, pa);
627
628 #ifdef RADEONFB_BIOS_INIT
629 if (radeonfb_bios_init(sc)) {
630 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc));
631 }
632 #endif
633
634 if (radeonfb_getclocks(sc)) {
635 aprint_error("%s: Unable to get reference clocks from BIOS\n",
636 XNAME(sc));
637 goto error;
638 }
639
640 if (radeonfb_gettmds(sc)) {
641 aprint_error("%s: Unable to identify TMDS PLL settings\n",
642 XNAME(sc));
643 goto error;
644 }
645
646 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d "
647 "minpll = %d, maxpll = %d\n", XNAME(sc),
648 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000,
649 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll);
650
651 radeonfb_getconnectors(sc);
652
653 radeonfb_set_fbloc(sc);
654
655 /* 64 MB should be enough -- more just wastes map entries */
656 if (sc->sc_memsz > (64 << 20))
657 sc->sc_memsz = (64 << 20);
658
659 for (i = 0; radeonfb_limits[i].size; i++) {
660 if (sc->sc_memsz >= radeonfb_limits[i].size) {
661 sc->sc_maxx = radeonfb_limits[i].maxx;
662 sc->sc_maxy = radeonfb_limits[i].maxy;
663 sc->sc_maxbpp = radeonfb_limits[i].maxbpp;
664 /* framebuffer offset, start at a 4K page */
665 sc->sc_fboffset = sc->sc_memsz /
666 radeonfb_limits[i].maxdisp;
667 /*
668 * we use the fbsize to figure out where we can store
669 * things like cursor data.
670 */
671 sc->sc_fbsize =
672 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 ,
673 RADEON_STRIDEALIGN) * sc->sc_maxy,
674 4096);
675 break;
676 }
677 }
678
679
680 radeonfb_init_misc(sc);
681
682 /* program the DAC wirings */
683 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) {
684 switch (sc->sc_ports[i].rp_dac_type) {
685 case RADEON_DAC_PRIMARY:
686 PATCH32(sc, RADEON_DAC_CNTL2,
687 i ? RADEON_DAC2_DAC_CLK_SEL : 0,
688 ~RADEON_DAC2_DAC_CLK_SEL);
689 break;
690 case RADEON_DAC_TVDAC:
691 /* we always use the TVDAC to drive a secondary analog
692 * CRT for now. if we ever support TV-out this will
693 * have to change.
694 */
695 SET32(sc, RADEON_DAC_CNTL2,
696 RADEON_DAC2_DAC2_CLK_SEL);
697 PATCH32(sc, RADEON_DISP_HW_DEBUG,
698 i ? 0 : RADEON_CRT2_DISP1_SEL,
699 ~RADEON_CRT2_DISP1_SEL);
700 /* we're using CRTC2 for the 2nd port */
701 if (sc->sc_ports[i].rp_number == 1) {
702 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL,
703 RADEON_DISP_DAC2_SOURCE_CRTC2,
704 ~RADEON_DISP_DAC2_SOURCE_MASK);
705 }
706
707 break;
708 }
709 DPRINTF(("%s: port %d tmds type %d\n", __func__, i,
710 sc->sc_ports[i].rp_tmds_type));
711 switch (sc->sc_ports[i].rp_tmds_type) {
712 case RADEON_TMDS_INT:
713 /* point FP0 at the CRTC this port uses */
714 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n",
715 __func__, sc->sc_ports[i].rp_number));
716 if (IS_R300(sc)) {
717 PATCH32(sc, RADEON_FP_GEN_CNTL,
718 sc->sc_ports[i].rp_number ?
719 R200_FP_SOURCE_SEL_CRTC2 :
720 R200_FP_SOURCE_SEL_CRTC1,
721 ~R200_FP_SOURCE_SEL_MASK);
722 } else {
723 PATCH32(sc, RADEON_FP_GEN_CNTL,
724 sc->sc_ports[i].rp_number ?
725 RADEON_FP_SEL_CRTC2 :
726 RADEON_FP_SEL_CRTC1,
727 ~RADEON_FP_SEL_MASK);
728 }
729 break;
730 case RADEON_TMDS_EXT:
731 /* point FP2 at the CRTC this port uses */
732 DPRINTF(("%s: plugging external TMDS into CRTC %d\n",
733 __func__, sc->sc_ports[i].rp_number));
734 if (IS_R300(sc)) {
735 PATCH32(sc, RADEON_FP2_GEN_CNTL,
736 sc->sc_ports[i].rp_number ?
737 R200_FP2_SOURCE_SEL_CRTC2 :
738 R200_FP2_SOURCE_SEL_CRTC1,
739 ~R200_FP2_SOURCE_SEL_CRTC2);
740 } else {
741 PATCH32(sc, RADEON_FP2_GEN_CNTL,
742 sc->sc_ports[i].rp_number ?
743 RADEON_FP2_SRC_SEL_CRTC2 :
744 RADEON_FP2_SRC_SEL_CRTC1,
745 ~RADEON_FP2_SRC_SEL_CRTC2);
746 }
747 break;
748 }
749 }
750 PRINTREG(RADEON_DAC_CNTL2);
751 PRINTREG(RADEON_DISP_HW_DEBUG);
752
753 PRINTREG(RADEON_DAC_CNTL);
754 /* other DAC programming */
755 v = GET32(sc, RADEON_DAC_CNTL);
756 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING);
757 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN;
758 PUT32(sc, RADEON_DAC_CNTL, v);
759 PRINTREG(RADEON_DAC_CNTL);
760
761 /* XXX: this may need more investigation */
762 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203);
763 PRINTREG(RADEON_TV_DAC_CNTL);
764
765 /* enable TMDS */
766 SET32(sc, RADEON_FP_GEN_CNTL,
767 RADEON_FP_TMDS_EN |
768 RADEON_FP_CRTC_DONT_SHADOW_VPAR |
769 RADEON_FP_CRTC_DONT_SHADOW_HEND);
770 /*
771 * XXX
772 * no idea why this is necessary - if I do not clear this bit on my
773 * iBook G4 the screen remains black, even though it's already clear.
774 * It needs to be set on my Sun XVR-100 for the DVI port to work
775 * TODO:
776 * see if this is still necessary now that CRTCs, DACs and outputs are
777 * getting wired up in a halfway sane way
778 */
779 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) {
780 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2);
781 } else {
782 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2);
783 }
784
785 /*
786 * we use bus_space_map instead of pci_mapreg, because we don't
787 * need the full aperature space. no point in wasting virtual
788 * address space we don't intend to use, right?
789 */
790 if ((sc->sc_memsz < (4096 * 1024)) ||
791 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM,
792 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) ||
793 (bsz < sc->sc_memsz)) {
794 sc->sc_memsz = 0;
795 aprint_error("%s: Bad frame buffer configuration\n",
796 XNAME(sc));
797 goto error;
798 }
799
800 sc->sc_memt = pa->pa_memt;
801 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz,
802 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE,
803 &sc->sc_memh) != 0) {
804 sc->sc_memsz = 0;
805 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc));
806 goto error;
807 }
808
809 aprint_normal("%s: %d MB aperture at 0x%08x, "
810 "%d KB registers at 0x%08x\n", XNAME(sc),
811 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr,
812 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr);
813
814 /* setup default video mode from devprop (allows PROM override) */
815 sc->sc_defaultmode = radeonfb_default_mode;
816 if (prop_dictionary_get_string(device_properties(sc->sc_dev),
817 "videomode", &mptr)) {
818
819 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf));
820 sc->sc_defaultmode = sc->sc_modebuf;
821 }
822
823 /* initialize some basic display parameters */
824 for (i = 0; i < sc->sc_ndisplays; i++) {
825 struct radeonfb_display *dp = &sc->sc_displays[i];
826 struct rasops_info *ri;
827 long defattr;
828 struct wsemuldisplaydev_attach_args aa;
829
830 /*
831 * Figure out how many "displays" (desktops) we are going to
832 * support. If more than one, then each CRTC gets its own
833 * programming.
834 *
835 * XXX: this code needs to change to support mergedfb.
836 * XXX: would be nice to allow this to be overridden
837 */
838 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) {
839 DPRINTF(("dual crtcs!\n"));
840 dp->rd_ncrtcs = 2;
841 dp->rd_crtcs[0].rc_port =
842 &sc->sc_ports[0];
843 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number;
844 dp->rd_crtcs[1].rc_port =
845 &sc->sc_ports[1];
846 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number;
847 } else {
848 dp->rd_ncrtcs = 1;
849 dp->rd_crtcs[0].rc_port =
850 &sc->sc_ports[i];
851 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number;
852 }
853
854 dp->rd_softc = sc;
855 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL;
856 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */
857
858 /* for text mode, we pick a resolution that won't
859 * require panning */
860 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0);
861
862 aprint_normal("%s: display %d: "
863 "initial virtual resolution %dx%d at %d bpp\n",
864 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp);
865 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n",
866 sc->sc_fboffset >> 20);
867 /* now select the *video mode* that we will use */
868 for (j = 0; j < dp->rd_ncrtcs; j++) {
869 const struct videomode *vmp;
870 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port,
871 dp->rd_virtx, dp->rd_virty);
872
873 /*
874 * virtual resolution should be at least as high as
875 * physical
876 */
877 if (dp->rd_virtx < vmp->hdisplay ||
878 dp->rd_virty < vmp->vdisplay) {
879 dp->rd_virtx = vmp->hdisplay;
880 dp->rd_virty = vmp->vdisplay;
881 }
882
883 dp->rd_crtcs[j].rc_videomode = *vmp;
884 printf("%s: port %d: physical %dx%d %dHz\n",
885 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay,
886 DIVIDE(DIVIDE(vmp->dot_clock * 1000,
887 vmp->htotal), vmp->vtotal));
888 }
889
890 /* N.B.: radeon wants 64-byte aligned stride */
891 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8;
892 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN);
893
894 dp->rd_offset = sc->sc_fboffset * i;
895 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt,
896 sc->sc_memh) + dp->rd_offset;
897 dp->rd_curoff = sc->sc_fboffset - 16384; /* 16KB cursor space */
898 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff;
899
900 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr));
901
902 switch (dp->rd_bpp) {
903 case 8:
904 dp->rd_format = 2;
905 break;
906 case 32:
907 dp->rd_format = 6;
908 break;
909 default:
910 aprint_error("%s: bad depth %d\n", XNAME(sc),
911 dp->rd_bpp);
912 goto error;
913 }
914 DPRINTF(("init engine\n"));
915 /* XXX: this seems suspicious - per display engine
916 initialization? */
917
918 radeonfb_modeswitch(dp);
919 radeonfb_engine_init(dp);
920
921 /* copy the template into place */
922 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen;
923 dp->rd_wsscreens = dp->rd_wsscreens_storage;
924
925 /* and make up the list */
926 dp->rd_wsscreenlist.nscreens = 1;
927 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens;
928
929 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens,
930 &radeonfb_accessops);
931
932 dp->rd_vd.init_screen = radeonfb_init_screen;
933
934 dp->rd_console = 0;
935 prop_dictionary_get_bool(device_properties(sc->sc_dev),
936 "is_console", &dp->rd_console);
937
938 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC;
939
940
941 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen,
942 dp->rd_console, &defattr);
943
944 ri = &dp->rd_vscreen.scr_ri;
945
946 /* clear the screen */
947 rasops_unpack_attr(defattr, &fg, &bg, &ul);
948 dp->rd_bg = ri->ri_devcmap[bg & 0xf];
949 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height,
950 dp->rd_bg);
951
952 dp->rd_wsscreens->textops = &ri->ri_ops;
953 dp->rd_wsscreens->capabilities = ri->ri_caps;
954 dp->rd_wsscreens->nrows = ri->ri_rows;
955 dp->rd_wsscreens->ncols = ri->ri_cols;
956
957 #ifdef SPLASHSCREEN
958 dp->rd_splash.si_depth = ri->ri_depth;
959 dp->rd_splash.si_bits = ri->ri_bits;
960 dp->rd_splash.si_hwbits = ri->ri_hwbits;
961 dp->rd_splash.si_width = ri->ri_width;
962 dp->rd_splash.si_height = ri->ri_height;
963 dp->rd_splash.si_stride = ri->ri_stride;
964 dp->rd_splash.si_fillrect = NULL;
965 #endif
966 dp->rd_gc.gc_bitblt = radeonfb_bitblt;
967 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a;
968 dp->rd_gc.gc_rop = RADEON_ROP3_S;
969 dp->rd_gc.gc_blitcookie = dp;
970 /*
971 * use memory between framebuffer and cursor area as glyph
972 * cache, cap at 4096 lines
973 */
974 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4,
975 uimin(4096,
976 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)),
977 dp->rd_virtx,
978 ri->ri_font->fontwidth,
979 ri->ri_font->fontheight,
980 defattr);
981 dp->rd_vd.show_screen_cookie = &dp->rd_gc;
982 dp->rd_vd.show_screen_cb = glyphcache_adapt;
983
984 if (dp->rd_console) {
985
986 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0,
987 defattr);
988 #ifdef SPLASHSCREEN
989 if (splash_render(&dp->rd_splash,
990 SPLASH_F_CENTER|SPLASH_F_FILL) == 0)
991 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen);
992 else
993 #endif
994 vcons_replay_msgbuf(&dp->rd_vscreen);
995 } else {
996
997 /*
998 * since we're not the console we can postpone
999 * the rest until someone actually allocates a
1000 * screen for us. but we do clear the screen
1001 * at least.
1002 */
1003 memset(ri->ri_bits, 0, 1024);
1004
1005 #ifdef SPLASHSCREEN
1006 if (splash_render(&dp->rd_splash,
1007 SPLASH_F_CENTER|SPLASH_F_FILL) == 0)
1008 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen);
1009 #endif
1010 }
1011
1012 aa.console = dp->rd_console;
1013 aa.scrdata = &dp->rd_wsscreenlist;
1014 aa.accessops = &radeonfb_accessops;
1015 aa.accesscookie = &dp->rd_vd;
1016
1017 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint,
1018 CFARGS(.iattr = "wsemuldisplaydev"));
1019
1020 radeonfb_blank(dp, 0);
1021
1022 /* Initialise delayed lvds operations for backlight. */
1023 callout_init(&dp->rd_bl_lvds_co, 0);
1024 callout_setfunc(&dp->rd_bl_lvds_co,
1025 radeonfb_lvds_callout, dp);
1026
1027 dp->rd_bl_on = 1;
1028 if (sc->sc_flags & RFB_MOB) {
1029 dp->rd_bl_level = radeonfb_get_backlight(dp);
1030 } else
1031 dp->rd_bl_level = 128;
1032
1033 radeonfb_set_backlight(dp, dp->rd_bl_level);
1034 }
1035 for (i = 0; i < RADEON_NDISPLAYS; i++)
1036 radeonfb_init_palette(&sc->sc_displays[i]);
1037
1038 if (HAS_CRTC2(sc) && !IS_AVIVO(sc)) {
1039 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS);
1040 }
1041
1042 if (!IS_AVIVO(sc)) {
1043 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS);
1044 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON);
1045 }
1046
1047 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP,
1048 radeonfb_brightness_up, TRUE);
1049 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN,
1050 radeonfb_brightness_down, TRUE);
1051
1052 /*
1053 * if we attach a DRM we need to unmap registers in
1054 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like
1055 * screen blanking we only do it if needed
1056 */
1057 sc->sc_needs_unmap =
1058 (config_found(dev, aux, radeonfb_drm_print,
1059 CFARGS(.iattr = "drm")) != NULL);
1060 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap));
1061
1062 if (!IS_AVIVO(sc)) {
1063 PRINTREG(RADEON_CRTC_EXT_CNTL);
1064 PRINTREG(RADEON_CRTC_GEN_CNTL);
1065 PRINTREG(RADEON_CRTC2_GEN_CNTL);
1066 PRINTREG(RADEON_DISP_OUTPUT_CNTL);
1067 PRINTREG(RADEON_DAC_CNTL2);
1068 PRINTREG(RADEON_FP_GEN_CNTL);
1069 PRINTREG(RADEON_FP2_GEN_CNTL);
1070 PRINTREG(RADEON_TMDS_CNTL);
1071 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL);
1072 PRINTREG(RADEON_TMDS_PLL_CNTL);
1073 /*
1074 XXX: We can't print this, as it's not correctly aligned
1075 PRINTREG(RADEON_PIXCLKS_CNTL);
1076 */
1077 }
1078 return;
1079
1080 error:
1081 if (sc->sc_biossz)
1082 free(sc->sc_bios, M_DEVBUF);
1083
1084 if (sc->sc_regsz)
1085 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz);
1086
1087 if (sc->sc_memsz)
1088 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz);
1089 }
1090
1091 static void
radeonfb_map(struct radeonfb_softc * sc)1092 radeonfb_map(struct radeonfb_softc *sc)
1093 {
1094 if (!sc->sc_mapped) {
1095 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0,
1096 &sc->sc_regh) != 0) {
1097 aprint_error_dev(sc->sc_dev,
1098 "unable to map registers!\n");
1099 return;
1100 }
1101 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz,
1102 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE,
1103 &sc->sc_memh) != 0) {
1104 sc->sc_memsz = 0;
1105 aprint_error_dev(sc->sc_dev,
1106 "Unable to map frame buffer\n");
1107 return;
1108 }
1109 sc->sc_mapped = TRUE;
1110 }
1111 }
1112
1113 static void
radeonfb_unmap(struct radeonfb_softc * sc)1114 radeonfb_unmap(struct radeonfb_softc *sc)
1115 {
1116 if (!sc->sc_needs_unmap)
1117 return;
1118
1119 if (sc->sc_mapped) {
1120 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz);
1121 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz);
1122 sc->sc_mapped = FALSE;
1123 }
1124 }
1125
1126 static int
radeonfb_drm_print(void * aux,const char * pnp)1127 radeonfb_drm_print(void *aux, const char *pnp)
1128 {
1129 if (pnp)
1130 aprint_normal("drm at %s", pnp);
1131 return (UNCONF);
1132 }
1133
1134 int
radeonfb_ioctl(void * v,void * vs,unsigned long cmd,void * d,int flag,struct lwp * l)1135 radeonfb_ioctl(void *v, void *vs,
1136 unsigned long cmd, void *d, int flag, struct lwp *l)
1137 {
1138 struct vcons_data *vd;
1139 struct radeonfb_display *dp;
1140 struct radeonfb_softc *sc;
1141 struct wsdisplay_param *param;
1142 struct vcons_screen *ms;
1143
1144 vd = (struct vcons_data *)v;
1145 ms = vd->active;
1146 dp = (struct radeonfb_display *)vd->cookie;
1147 sc = dp->rd_softc;
1148
1149 /* can't do these without registers being mapped */
1150 if (!sc->sc_mapped) {
1151 switch (cmd) {
1152 case WSDISPLAYIO_GVIDEO:
1153 case WSDISPLAYIO_SVIDEO:
1154 case WSDISPLAYIO_GETCMAP:
1155 case WSDISPLAYIO_PUTCMAP:
1156 case WSDISPLAYIO_SCURSOR:
1157 case WSDISPLAYIO_GCURPOS:
1158 case WSDISPLAYIO_SCURPOS:
1159 case WSDISPLAYIO_SETPARAM:
1160 return EINVAL;
1161 }
1162 }
1163
1164 switch (cmd) {
1165 case WSDISPLAYIO_GTYPE:
1166 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC;
1167 return 0;
1168
1169 case WSDISPLAYIO_GINFO:
1170 if (vd->active != NULL) {
1171 struct wsdisplay_fbinfo *fb;
1172 fb = (struct wsdisplay_fbinfo *)d;
1173 fb->width = dp->rd_virtx;
1174 fb->height = dp->rd_virty;
1175 fb->depth = dp->rd_bpp;
1176 fb->cmsize = 256;
1177 return 0;
1178 } else
1179 return ENODEV;
1180 case WSDISPLAYIO_GVIDEO:
1181 if (radeonfb_isblank(dp))
1182 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF;
1183 else
1184 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON;
1185 return 0;
1186
1187 case WSDISPLAYIO_SVIDEO:
1188 if (dp->rd_wsmode != WSDISPLAYIO_MODE_MAPPED) {
1189 radeonfb_blank(dp,
1190 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF));
1191 radeonfb_switch_backlight(dp,
1192 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON));
1193 }
1194 pmf_event_inject(NULL,
1195 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON) ?
1196 PMFE_DISPLAY_ON : PMFE_DISPLAY_OFF);
1197 return 0;
1198
1199 case WSDISPLAYIO_GETCMAP:
1200 if (dp->rd_bpp == 8)
1201 return radeonfb_getcmap(dp,
1202 (struct wsdisplay_cmap *)d);
1203 return EINVAL;
1204
1205 case WSDISPLAYIO_PUTCMAP:
1206 if (dp->rd_bpp == 8)
1207 return radeonfb_putcmap(dp,
1208 (struct wsdisplay_cmap *)d);
1209 return EINVAL;
1210
1211 case WSDISPLAYIO_LINEBYTES:
1212 *(unsigned *)d = dp->rd_stride;
1213 return 0;
1214
1215 case WSDISPLAYIO_SMODE:
1216 if (*(int *)d != dp->rd_wsmode) {
1217 dp->rd_wsmode = *(int *)d;
1218 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) ||
1219 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB))
1220 radeonfb_map(sc);
1221
1222 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) &&
1223 (dp->rd_vd.active)) {
1224 radeonfb_engine_init(dp);
1225 glyphcache_wipe(&dp->rd_gc);
1226 radeonfb_init_palette(dp);
1227 radeonfb_modeswitch(dp);
1228 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx,
1229 dp->rd_virty, dp->rd_bg);
1230 vcons_redraw_screen(dp->rd_vd.active);
1231 }
1232 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED)
1233 radeonfb_unmap(sc);
1234 }
1235 return 0;
1236
1237 case WSDISPLAYIO_GCURMAX:
1238 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX;
1239 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY;
1240 return 0;
1241
1242 case WSDISPLAYIO_SCURSOR:
1243 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d);
1244
1245 case WSDISPLAYIO_GCURSOR:
1246 return EPASSTHROUGH;
1247
1248 case WSDISPLAYIO_GCURPOS:
1249 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x;
1250 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y;
1251 return 0;
1252
1253 case WSDISPLAYIO_SCURPOS:
1254 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d);
1255
1256 case WSDISPLAYIO_SSPLASH:
1257 #if defined(SPLASHSCREEN)
1258 if (*(int *)d == 1) {
1259 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen);
1260 splash_render(&dp->rd_splash,
1261 SPLASH_F_CENTER|SPLASH_F_FILL);
1262 } else
1263 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen);
1264 return 0;
1265 #else
1266 return ENODEV;
1267 #endif
1268 case WSDISPLAYIO_GETPARAM:
1269 param = (struct wsdisplay_param *)d;
1270 switch (param->param) {
1271 case WSDISPLAYIO_PARAM_BRIGHTNESS:
1272 param->min = 0;
1273 param->max = 255;
1274 param->curval = dp->rd_bl_level;
1275 return 0;
1276 case WSDISPLAYIO_PARAM_BACKLIGHT:
1277 param->min = 0;
1278 param->max = RADEONFB_BACKLIGHT_MAX;
1279 param->curval = dp->rd_bl_on;
1280 return 0;
1281 }
1282 return EPASSTHROUGH;
1283
1284 case WSDISPLAYIO_SETPARAM:
1285 param = (struct wsdisplay_param *)d;
1286 switch (param->param) {
1287 case WSDISPLAYIO_PARAM_BRIGHTNESS:
1288 radeonfb_set_backlight(dp, param->curval);
1289 return 0;
1290 case WSDISPLAYIO_PARAM_BACKLIGHT:
1291 radeonfb_switch_backlight(dp, param->curval);
1292 return 0;
1293 }
1294 return EPASSTHROUGH;
1295
1296 /* PCI config read/write passthrough. */
1297 case PCI_IOC_CFGREAD:
1298 case PCI_IOC_CFGWRITE:
1299 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l);
1300
1301 case WSDISPLAYIO_GET_BUSID:
1302 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc,
1303 sc->sc_pt, d);
1304
1305 case WSDISPLAYIO_GET_EDID: {
1306 struct wsdisplayio_edid_info *ei = d;
1307 return wsdisplayio_get_edid(sc->sc_dev, ei);
1308 }
1309
1310 case WSDISPLAYIO_GET_FBINFO: {
1311 struct wsdisplayio_fbinfo *fbi = d;
1312 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi);
1313 }
1314
1315 default:
1316 return EPASSTHROUGH;
1317 }
1318 }
1319
1320 paddr_t
radeonfb_mmap(void * v,void * vs,off_t offset,int prot)1321 radeonfb_mmap(void *v, void *vs, off_t offset, int prot)
1322 {
1323 struct vcons_data *vd;
1324 struct radeonfb_display *dp;
1325 struct radeonfb_softc *sc;
1326 paddr_t pa;
1327
1328 vd = (struct vcons_data *)v;
1329 dp = (struct radeonfb_display *)vd->cookie;
1330 sc = dp->rd_softc;
1331
1332 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) {
1333 pa = bus_space_mmap(sc->sc_memt,
1334 sc->sc_memaddr + dp->rd_offset + offset, 0,
1335 prot, BUS_SPACE_MAP_LINEAR);
1336 return pa;
1337 }
1338
1339 /*
1340 * restrict all other mappings to processes with superuser privileges
1341 * or the kernel itself
1342 */
1343 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM,
1344 NULL, NULL, NULL, NULL) != 0) {
1345 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n");
1346 return -1;
1347 }
1348
1349 if ((offset >= sc->sc_regaddr) &&
1350 (offset < sc->sc_regaddr + sc->sc_regsz)) {
1351 return bus_space_mmap(sc->sc_regt, offset, 0, prot,
1352 BUS_SPACE_MAP_LINEAR);
1353 }
1354
1355 if ((offset >= sc->sc_memaddr) &&
1356 (offset < sc->sc_memaddr + sc->sc_memsz)) {
1357 return bus_space_mmap(sc->sc_memt, offset, 0, prot,
1358 BUS_SPACE_MAP_LINEAR);
1359 }
1360
1361 if ((offset >= sc->sc_romaddr) &&
1362 (offset < sc->sc_romaddr + sc->sc_romsz)) {
1363 return bus_space_mmap(sc->sc_memt, offset, 0, prot,
1364 BUS_SPACE_MAP_LINEAR);
1365 }
1366
1367 #ifdef PCI_MAGIC_IO_RANGE
1368 /* allow mapping of IO space */
1369 if ((offset >= PCI_MAGIC_IO_RANGE) &&
1370 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) {
1371 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE,
1372 0, prot, 0);
1373 return pa;
1374 }
1375 #endif /* PCI_MAGIC_IO_RANGE */
1376
1377 return -1;
1378 }
1379
1380 static void
radeonfb_loadbios(struct radeonfb_softc * sc,const struct pci_attach_args * pa)1381 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa)
1382 {
1383 bus_space_tag_t romt;
1384 bus_space_handle_t romh, biosh;
1385 bus_size_t romsz;
1386 bus_addr_t ptr;
1387 uint32_t busctl, crtcg, crtc2g = 0, viphctl, seprom, extc;
1388 int bios_voodoo = 0;
1389
1390 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM,
1391 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) {
1392 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc));
1393 return;
1394 }
1395
1396 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh,
1397 &sc->sc_biossz);
1398 if (sc->sc_biossz != 0) goto foundit;
1399
1400 aprint_verbose("trying to read disabled BIOS...\n");
1401
1402 bios_voodoo = 1;
1403 seprom = radeonfb_get32(sc, RADEON_SEPROM_CNTL1);
1404 radeonfb_put32(sc, RADEON_SEPROM_CNTL1,
1405 (seprom & ~RADEON_SCK_PRESCALE_MASK) |
1406 (0xc << RADEON_SCK_PRESCALE_SHIFT));
1407 viphctl = radeonfb_get32(sc, RADEON_VIPH_CONTROL);
1408 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl & ~RADEON_VIPH_EN);
1409 busctl = radeonfb_get32(sc, RADEON_BUS_CNTL);
1410 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl & ~RADEON_BUS_BIOS_DIS_ROM);
1411 crtcg = radeonfb_get32(sc, RADEON_CRTC_GEN_CNTL);
1412 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, ((crtcg & ~RADEON_CRTC_EN) |
1413 (RADEON_CRTC_DISP_REQ_EN_B |
1414 RADEON_CRTC_EXT_DISP_EN)));
1415 if (HAS_CRTC2(sc)) {
1416 crtc2g = radeonfb_get32(sc, RADEON_CRTC2_GEN_CNTL);
1417 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL,
1418 (crtc2g & ~RADEON_CRTC2_EN) |
1419 RADEON_CRTC2_DISP_REQ_EN_B);
1420 }
1421 extc = radeonfb_get32(sc, RADEON_CRTC_EXT_CNTL);
1422 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, (extc & ~RADEON_CRTC_CRT_ON) |
1423 (RADEON_CRTC_SYNC_TRISTAT |
1424 RADEON_CRTC_DISPLAY_DIS));
1425 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh,
1426 &sc->sc_biossz);
1427
1428 foundit:
1429 if (sc->sc_biossz > 0) {
1430 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK);
1431 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios,
1432 sc->sc_biossz);
1433 }
1434
1435 if (bios_voodoo != 0) {
1436 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, extc);
1437 if (HAS_CRTC2(sc)) {
1438 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, crtc2g);
1439 }
1440 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, crtcg);
1441 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl);
1442 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl);
1443 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, seprom);
1444 }
1445
1446 /* unmap the PCI expansion rom */
1447 bus_space_unmap(romt, romh, romsz);
1448
1449 /* turn off rom decoder now */
1450 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM,
1451 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) &
1452 ~PCI_MAPREG_ROM_ENABLE);
1453
1454 if (sc->sc_biossz > 0) {
1455 ptr = GETBIOS16(sc, 0x48);
1456 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) ||
1457 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) {
1458 sc->sc_flags |= RFB_ATOM;
1459 }
1460
1461 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc),
1462 (unsigned)sc->sc_biossz >> 10,
1463 IS_ATOM(sc) ? "ATOM" : "Legacy");
1464 }
1465 }
1466
1467
1468 uint32_t
radeonfb_get32(struct radeonfb_softc * sc,uint32_t reg)1469 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg)
1470 {
1471
1472 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg);
1473 }
1474
1475 void
radeonfb_put32(struct radeonfb_softc * sc,uint32_t reg,uint32_t val)1476 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val)
1477 {
1478
1479 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val);
1480 }
1481
1482 void
radeonfb_put32s(struct radeonfb_softc * sc,uint32_t reg,uint32_t val)1483 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val)
1484 {
1485
1486 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val);
1487 }
1488
1489 void
radeonfb_mask32(struct radeonfb_softc * sc,uint32_t reg,uint32_t andmask,uint32_t ormask)1490 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg,
1491 uint32_t andmask, uint32_t ormask)
1492 {
1493 int s;
1494 uint32_t val;
1495
1496 s = splhigh();
1497 val = radeonfb_get32(sc, reg);
1498 val = (val & andmask) | ormask;
1499 radeonfb_put32(sc, reg, val);
1500 splx(s);
1501 }
1502
1503 uint32_t
radeonfb_getindex(struct radeonfb_softc * sc,uint32_t idx)1504 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx)
1505 {
1506 int s;
1507 uint32_t val;
1508
1509 s = splhigh();
1510 radeonfb_put32(sc, RADEON_MM_INDEX, idx);
1511 val = radeonfb_get32(sc, RADEON_MM_DATA);
1512 splx(s);
1513
1514 return (val);
1515 }
1516
1517 void
radeonfb_putindex(struct radeonfb_softc * sc,uint32_t idx,uint32_t val)1518 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val)
1519 {
1520 int s;
1521
1522 s = splhigh();
1523 radeonfb_put32(sc, RADEON_MM_INDEX, idx);
1524 radeonfb_put32(sc, RADEON_MM_DATA, val);
1525 splx(s);
1526 }
1527
1528 void
radeonfb_maskindex(struct radeonfb_softc * sc,uint32_t idx,uint32_t andmask,uint32_t ormask)1529 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx,
1530 uint32_t andmask, uint32_t ormask)
1531 {
1532 int s;
1533 uint32_t val;
1534
1535 s = splhigh();
1536 radeonfb_put32(sc, RADEON_MM_INDEX, idx);
1537 val = radeonfb_get32(sc, RADEON_MM_DATA);
1538 val = (val & andmask) | ormask;
1539 radeonfb_put32(sc, RADEON_MM_DATA, val);
1540 splx(s);
1541 }
1542
1543 uint32_t
radeonfb_getpll(struct radeonfb_softc * sc,uint32_t idx)1544 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx)
1545 {
1546 int s;
1547 uint32_t val;
1548
1549 s = splhigh();
1550 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f));
1551 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA);
1552 if (HAS_R300CG(sc))
1553 radeonfb_r300cg_workaround(sc);
1554 splx(s);
1555
1556 return (val);
1557 }
1558
1559 void
radeonfb_putpll(struct radeonfb_softc * sc,uint32_t idx,uint32_t val)1560 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val)
1561 {
1562 int s;
1563
1564 s = splhigh();
1565 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) |
1566 RADEON_PLL_WR_EN);
1567 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val);
1568 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0);
1569 splx(s);
1570 }
1571
1572 void
radeonfb_maskpll(struct radeonfb_softc * sc,uint32_t idx,uint32_t andmask,uint32_t ormask)1573 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx,
1574 uint32_t andmask, uint32_t ormask)
1575 {
1576 int s;
1577 uint32_t val;
1578
1579 s = splhigh();
1580 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) |
1581 RADEON_PLL_WR_EN);
1582 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA);
1583 val = (val & andmask) | ormask;
1584 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val);
1585 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0);
1586 splx(s);
1587 }
1588
1589 int
radeonfb_scratch_test(struct radeonfb_softc * sc,int reg,uint32_t v)1590 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v)
1591 {
1592 uint32_t saved;
1593
1594 saved = GET32(sc, reg);
1595 PUT32(sc, reg, v);
1596 if (GET32(sc, reg) != v) {
1597 return -1;
1598 }
1599 PUT32(sc, reg, saved);
1600 return 0;
1601 }
1602
1603 uintmax_t
radeonfb_getprop_num(struct radeonfb_softc * sc,const char * name,uintmax_t defval)1604 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name,
1605 uintmax_t defval)
1606 {
1607 prop_number_t pn;
1608 pn = prop_dictionary_get(device_properties(sc->sc_dev), name);
1609 if (pn == NULL) {
1610 return defval;
1611 }
1612 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
1613 return prop_number_unsigned_value(pn);
1614 }
1615
1616 int
radeonfb_getclocks(struct radeonfb_softc * sc)1617 radeonfb_getclocks(struct radeonfb_softc *sc)
1618 {
1619 bus_addr_t ptr;
1620 int refclk = 0;
1621 int refdiv = 0;
1622 int minpll = 0;
1623 int maxpll = 0;
1624
1625 /* load initial property values if port/board provides them */
1626 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff;
1627 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff;
1628 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU;
1629 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU;
1630
1631 PRINTPLL(RADEON_PPLL_REF_DIV);
1632 PRINTPLL(RADEON_PPLL_DIV_0);
1633 PRINTPLL(RADEON_PPLL_DIV_1);
1634 PRINTPLL(RADEON_PPLL_DIV_2);
1635 PRINTPLL(RADEON_PPLL_DIV_3);
1636 PRINTREG(RADEON_CLOCK_CNTL_INDEX);
1637 PRINTPLL(RADEON_P2PLL_REF_DIV);
1638 PRINTPLL(RADEON_P2PLL_DIV_0);
1639
1640 if (refclk && refdiv && minpll && maxpll)
1641 goto dontprobe;
1642
1643 if (!sc->sc_biossz) {
1644 /* no BIOS */
1645 aprint_verbose("%s: No video BIOS, using default clocks\n",
1646 XNAME(sc));
1647 if (IS_IGP(sc))
1648 refclk = refclk ? refclk : 1432;
1649 else
1650 refclk = refclk ? refclk : 2700;
1651 refdiv = refdiv ? refdiv : 12;
1652 minpll = minpll ? minpll : 12500;
1653 /* XXX
1654 * Need to check if the firmware or something programmed a
1655 * higher value than this, and if so, bump it.
1656 * The RV280 in my iBook is unhappy if the PLL input is less
1657 * than 360MHz
1658 */
1659 maxpll = maxpll ? maxpll : 40000/*35000*/;
1660 } else if (IS_ATOM(sc)) {
1661 /* ATOM BIOS */
1662 ptr = GETBIOS16(sc, 0x48);
1663 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */
1664 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */
1665 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82);
1666 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78);
1667 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32);
1668 /*
1669 * ATOM BIOS doesn't supply a reference divider, so we
1670 * have to probe for it.
1671 */
1672 if (refdiv < 2)
1673 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) &
1674 RADEON_PPLL_REF_DIV_MASK;
1675 /*
1676 * if probe is zero, just assume one that should work
1677 * for most parts
1678 */
1679 if (refdiv < 2)
1680 refdiv = 12;
1681
1682 } else {
1683 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV);
1684 /* Legacy BIOS */
1685 ptr = GETBIOS16(sc, 0x48);
1686 ptr = GETBIOS16(sc, ptr + 0x30);
1687 if (IS_R300(sc)) {
1688 refdiv = refdiv ? refdiv :
1689 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >>
1690 R300_PPLL_REF_DIV_ACC_SHIFT;
1691 } else {
1692 refdiv = refdiv ? refdiv :
1693 tmp & RADEON_PPLL_REF_DIV_MASK;
1694 }
1695 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E);
1696 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10);
1697 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12);
1698 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16);
1699 }
1700
1701
1702 dontprobe:
1703 sc->sc_refclk = refclk * 10;
1704 sc->sc_refdiv = refdiv;
1705 sc->sc_minpll = minpll * 10;
1706 sc->sc_maxpll = maxpll * 10;
1707 return 0;
1708 }
1709
1710 int
radeonfb_calc_dividers(struct radeonfb_softc * sc,uint32_t dotclock,uint32_t * postdivbit,uint32_t * feedbackdiv,int flags)1711 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock,
1712 uint32_t *postdivbit, uint32_t *feedbackdiv, int flags)
1713 {
1714 int i;
1715 uint32_t outfreq;
1716 int div;
1717
1718 DPRINTF(("dot clock: %u\n", dotclock));
1719 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) {
1720
1721 if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0))
1722 continue;
1723
1724 /*
1725 * XXX
1726 * the rv350 in my last generation 14" iBook G4 produces
1727 * garbage with dividers > 4. No idea if this is a hardware
1728 * limitation or an error in the divider table.
1729 */
1730 if ((sc->sc_family == RADEON_RV350) && (div > 4))
1731 continue;
1732
1733 outfreq = div * dotclock;
1734 if ((outfreq >= sc->sc_minpll) &&
1735 (outfreq <= sc->sc_maxpll)) {
1736 DPRINTF(("outfreq: %u\n", outfreq));
1737 *postdivbit =
1738 ((uint32_t)radeonfb_dividers[i].mask << 16);
1739 DPRINTF(("post divider: %d (mask %x)\n", div,
1740 *postdivbit));
1741 break;
1742 }
1743 }
1744
1745 if (div == 0)
1746 return 1;
1747
1748 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk);
1749 DPRINTF(("feedback divider: %d\n", *feedbackdiv));
1750 return 0;
1751 }
1752
1753 #if 0
1754 #ifdef RADEONFB_DEBUG
1755 static void
1756 dump_buffer(const char *pfx, void *buffer, unsigned int size)
1757 {
1758 char asc[17];
1759 unsigned ptr = (unsigned)buffer;
1760 char *start = (char *)(ptr & ~0xf);
1761 char *end = (char *)(ptr + size);
1762
1763 end = (char *)(((unsigned)end + 0xf) & ~0xf);
1764
1765 if (pfx == NULL) {
1766 pfx = "";
1767 }
1768
1769 while (start < end) {
1770 unsigned offset = (unsigned)start & 0xf;
1771 if (offset == 0) {
1772 printf("%s%x: ", pfx, (unsigned)start);
1773 }
1774 if (((unsigned)start < ptr) ||
1775 ((unsigned)start >= (ptr + size))) {
1776 printf(" ");
1777 asc[offset] = ' ';
1778 } else {
1779 printf("%02x", *(unsigned char *)start);
1780 if ((*start >= ' ') && (*start <= '~')) {
1781 asc[offset] = *start;
1782 } else {
1783 asc[offset] = '.';
1784 }
1785 }
1786 asc[offset + 1] = 0;
1787 if (offset % 2) {
1788 printf(" ");
1789 }
1790 if (offset == 15) {
1791 printf(" %s\n", asc);
1792 }
1793 start++;
1794 }
1795 }
1796 #endif
1797 #endif
1798
1799 int
radeonfb_getconnectors(struct radeonfb_softc * sc)1800 radeonfb_getconnectors(struct radeonfb_softc *sc)
1801 {
1802 int i;
1803 int found = 0;
1804
1805 for (i = 0; i < 2; i++) {
1806 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN;
1807 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE;
1808 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN;
1809 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE;
1810 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN;
1811 }
1812
1813 /*
1814 * This logic is borrowed from Xorg's radeon driver.
1815 */
1816 if (!sc->sc_biossz)
1817 goto nobios;
1818
1819 if (IS_ATOM(sc)) {
1820 /* not done yet */
1821 } else {
1822 uint16_t ptr;
1823 int port = 0;
1824
1825 ptr = GETBIOS16(sc, 0x48);
1826 ptr = GETBIOS16(sc, ptr + 0x50);
1827 for (i = 1; i < 4; i++) {
1828 uint16_t entry;
1829 uint8_t conn, ddc, dac, tmds;
1830
1831 /*
1832 * Parse the connector table. From reading the code,
1833 * it appears to made up of 16-bit entries for each
1834 * connector. The 16-bits are defined as:
1835 *
1836 * bits 12-15 - connector type (0 == end of table)
1837 * bits 8-11 - DDC type
1838 * bits 5-7 - ???
1839 * bit 4 - TMDS type (1 = EXT, 0 = INT)
1840 * bits 1-3 - ???
1841 * bit 0 - DAC, 1 = TVDAC, 0 = primary
1842 */
1843 if (!GETBIOS8(sc, ptr + i * 2) && i > 1)
1844 break;
1845 entry = GETBIOS16(sc, ptr + i * 2);
1846
1847 conn = (entry >> 12) & 0xf;
1848 ddc = (entry >> 8) & 0xf;
1849 dac = (entry & 0x1) ? RADEON_DAC_TVDAC :
1850 RADEON_DAC_PRIMARY;
1851 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT :
1852 RADEON_TMDS_INT;
1853
1854 if (conn == RADEON_CONN_NONE)
1855 continue; /* no connector */
1856
1857 /*
1858 * XXX
1859 * both Mac Mini variants have both outputs wired to
1860 * the same connector and share the DDC lines
1861 */
1862 if ((found > 0) &&
1863 (sc->sc_ports[port].rp_ddc_type == ddc)) {
1864 /* duplicate entry for same connector */
1865 continue;
1866 }
1867
1868 /* internal DDC_DVI port gets priority */
1869 if ((ddc == RADEON_DDC_DVI) || (port == 1))
1870 port = 0;
1871 else
1872 port = 1;
1873
1874 sc->sc_ports[port].rp_ddc_type =
1875 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc;
1876 sc->sc_ports[port].rp_dac_type = dac;
1877 sc->sc_ports[port].rp_conn_type =
1878 uimin(conn, RADEON_CONN_UNSUPPORTED) ;
1879
1880 sc->sc_ports[port].rp_tmds_type = tmds;
1881
1882 if ((conn != RADEON_CONN_DVI_I) &&
1883 (conn != RADEON_CONN_DVI_D) &&
1884 (tmds == RADEON_TMDS_INT))
1885 sc->sc_ports[port].rp_tmds_type =
1886 RADEON_TMDS_UNKNOWN;
1887 sc->sc_ports[port].rp_number = i - 1;
1888
1889 found += (port + 1);
1890 }
1891 }
1892
1893 nobios:
1894 if (!found) {
1895 bool dvi_ext = FALSE, dvi_int = FALSE;
1896 DPRINTF(("No connector info in BIOS!\n"));
1897 prop_dictionary_get_bool(device_properties(sc->sc_dev),
1898 "dvi-internal", &dvi_int);
1899 prop_dictionary_get_bool(device_properties(sc->sc_dev),
1900 "dvi-external", &dvi_ext);
1901 if (dvi_ext) {
1902 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN;
1903 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2;
1904 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY;
1905 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I;
1906 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; /* output to fp2 */
1907 sc->sc_ports[0].rp_number = 0;
1908 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN;
1909 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE;
1910 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN;
1911 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE;
1912 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN;
1913 sc->sc_ports[1].rp_number = 1;
1914 } else if (dvi_int) {
1915 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN;
1916 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2;
1917 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY;
1918 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I;
1919 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT;
1920 sc->sc_ports[0].rp_number = 0;
1921 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN;
1922 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE;
1923 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN;
1924 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE;
1925 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN;
1926 sc->sc_ports[1].rp_number = 1;
1927 } else if IS_MOBILITY(sc) {
1928 /* default, port 0 = internal TMDS, port 1 = CRT */
1929 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN;
1930 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI;
1931 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC;
1932 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D;
1933 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT;
1934 sc->sc_ports[0].rp_number = 0;
1935
1936 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN;
1937 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA;
1938 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY;
1939 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT;
1940 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT;
1941 sc->sc_ports[1].rp_number = 1;
1942 } else {
1943 /* default, port 0 = DVI, port 1 = CRT */
1944 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN;
1945 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI;
1946 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC;
1947 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D;
1948 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT;
1949 sc->sc_ports[0].rp_number = 0;
1950
1951 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN;
1952 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA;
1953 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY;
1954 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT;
1955 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN;
1956 sc->sc_ports[1].rp_number = 1;
1957 }
1958 }
1959
1960 /*
1961 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC.
1962 * these chips should use TVDAC for the VGA port.
1963 */
1964 if (HAS_SDAC(sc)) {
1965 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) {
1966 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC;
1967 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY;
1968 } else {
1969 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC;
1970 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY;
1971 }
1972 } else if (!HAS_CRTC2(sc)) {
1973 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY;
1974 }
1975
1976 for (i = 0; i < 2; i++) {
1977 char edid[128], edid_port_str[7] = "EDID:";
1978 uint8_t ddc;
1979 struct edid_info *eip = &sc->sc_ports[i].rp_edid;
1980 prop_data_t edid_data;
1981
1982 DPRINTF(("Port #%d:\n", i));
1983 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type));
1984 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type));
1985 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type));
1986 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type));
1987 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number));
1988
1989 sc->sc_ports[i].rp_edid_valid = 0;
1990 /*
1991 * First look for static EDID data
1992 * Try "EDID:port" then "EDID"
1993 */
1994 snprintf(&edid_port_str[5], 2, "%d", i);
1995 edid_data = prop_dictionary_get(device_properties(
1996 sc->sc_dev), edid_port_str);
1997 if (edid_data == NULL)
1998 edid_data = prop_dictionary_get(device_properties(
1999 sc->sc_dev), "EDID");
2000 if (edid_data != NULL) {
2001 aprint_debug_dev(sc->sc_dev, "using static EDID\n");
2002 memcpy(edid, prop_data_value(edid_data), 128);
2003 if (edid_parse(edid, eip) == 0) {
2004
2005 sc->sc_ports[i].rp_edid_valid = 1;
2006 #ifdef RADEONFB_DEBUG
2007 edid_print(eip);
2008 #endif
2009 }
2010 }
2011 /* if we didn't find any we'll try to talk to the monitor */
2012 if (sc->sc_ports[i].rp_edid_valid != 1) {
2013
2014 ddc = sc->sc_ports[i].rp_ddc_type;
2015 if (ddc != RADEON_DDC_NONE) {
2016 if ((radeonfb_i2c_read_edid(sc, ddc, edid)
2017 == 0) && (edid_parse(edid, eip) == 0)) {
2018
2019 sc->sc_ports[i].rp_edid_valid = 1;
2020 #ifdef RADEONFB_DEBUG
2021 edid_print(eip);
2022 #endif
2023 }
2024 }
2025 }
2026 }
2027
2028 return found;
2029 }
2030
2031 int
radeonfb_gettmds(struct radeonfb_softc * sc)2032 radeonfb_gettmds(struct radeonfb_softc *sc)
2033 {
2034 int i;
2035
2036 if (!sc->sc_biossz) {
2037 goto nobios;
2038 }
2039
2040 if (IS_ATOM(sc)) {
2041 /* XXX: not done yet */
2042 } else {
2043 uint16_t ptr;
2044 int n;
2045
2046 ptr = GETBIOS16(sc, 0x48);
2047 ptr = GETBIOS16(sc, ptr + 0x34);
2048 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr)));
2049 if (GETBIOS8(sc, ptr) == 3) {
2050 /* revision three table */
2051 n = GETBIOS8(sc, ptr + 5) + 1;
2052 n = uimin(n, 4);
2053
2054 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll));
2055 for (i = 0; i < n; i++) {
2056 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc,
2057 ptr + i * 10 + 8);
2058 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc,
2059 ptr + i * 10 + 0x10);
2060 DPRINTF(("TMDS_PLL dot clock %d pll %x\n",
2061 sc->sc_tmds_pll[i].rtp_freq,
2062 sc->sc_tmds_pll[i].rtp_pll));
2063 }
2064 return 0;
2065 }
2066 }
2067
2068 nobios:
2069 DPRINTF(("no suitable DFP table present\n"));
2070 for (i = 0;
2071 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]);
2072 i++) {
2073 int j;
2074
2075 if (radeonfb_tmds_pll[i].family != sc->sc_family)
2076 continue;
2077
2078 for (j = 0; j < 4; j++) {
2079 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j];
2080 DPRINTF(("TMDS_PLL dot clock %d pll %x\n",
2081 sc->sc_tmds_pll[j].rtp_freq,
2082 sc->sc_tmds_pll[j].rtp_pll));
2083 }
2084 return 0;
2085 }
2086
2087 return -1;
2088 }
2089
2090 const struct videomode *
radeonfb_modelookup(const char * name)2091 radeonfb_modelookup(const char *name)
2092 {
2093 int i;
2094 /* Use a default mode in case we don't find a matching mode */
2095 const char *vm = "1024x768x60";
2096 const struct videomode *vmp = NULL;
2097
2098 for (i = 0; i < videomode_count; i++) {
2099 if (!strcmp(name, videomode_list[i].name))
2100 return &videomode_list[i];
2101 if (!strcmp(vm, videomode_list[i].name))
2102 vmp = &videomode_list[i];
2103 }
2104 return vmp;
2105 }
2106
2107 void
radeonfb_pllwriteupdate(struct radeonfb_softc * sc,int crtc)2108 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc)
2109 {
2110 if (crtc) {
2111 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) &
2112 RADEON_P2PLL_ATOMIC_UPDATE_R);
2113 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W);
2114 } else {
2115 while (GETPLL(sc, RADEON_PPLL_REF_DIV) &
2116 RADEON_PPLL_ATOMIC_UPDATE_R);
2117 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W);
2118 }
2119 }
2120
2121 void
radeonfb_pllwaitatomicread(struct radeonfb_softc * sc,int crtc)2122 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc)
2123 {
2124 int i;
2125
2126 for (i = 10000; i; i--) {
2127 if (crtc) {
2128 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) &
2129 RADEON_P2PLL_ATOMIC_UPDATE_R)
2130 break;
2131 } else {
2132 if (GETPLL(sc, RADEON_PPLL_REF_DIV) &
2133 RADEON_PPLL_ATOMIC_UPDATE_R)
2134 break;
2135 }
2136 }
2137 }
2138
2139 void
radeonfb_program_vclk(struct radeonfb_softc * sc,int dotclock,int crtc,int flags)2140 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags)
2141 {
2142 uint32_t pbit = 0;
2143 uint32_t feed = 0;
2144 uint32_t data, refdiv, div0, r2xxref;
2145
2146 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags);
2147
2148 if (crtc == 0) {
2149
2150 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV);
2151
2152 /*
2153 * XXX
2154 * the RV350 in my last generation iBook G4 behaves like an
2155 * r2xx here - try to detect that and not screw up the reference
2156 * divider.
2157 * xf86-video-radeon just skips PLL programming altogether
2158 * on iBooks, probably for this reason.
2159 */
2160 r2xxref = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | sc->sc_refdiv;
2161 if (IS_R300(sc) && (r2xxref != refdiv)) {
2162 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) |
2163 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT);
2164 } else {
2165 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) |
2166 sc->sc_refdiv;
2167 }
2168 DPRINTF(("refdiv %08x\n", refdiv));
2169 div0 = GETPLL(sc, RADEON_PPLL_DIV_0);
2170 DPRINTF(("div0 %08x\n", div0));
2171 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK |
2172 RADEON_PPLL_POST3_DIV_MASK);
2173 div0 |= pbit;
2174 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK);
2175 DPRINTF(("div0 %08x\n", div0));
2176
2177 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) &&
2178 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) {
2179 /*
2180 * nothing to do here, the PLL is already where we
2181 * want it
2182 */
2183 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0,
2184 ~RADEON_PLL_DIV_SEL);
2185 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n");
2186 return;
2187 }
2188
2189 /* alright, we do need to reprogram stuff */
2190 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL,
2191 RADEON_VCLK_SRC_SEL_CPUCLK,
2192 ~RADEON_VCLK_SRC_SEL_MASK);
2193
2194 /* put vclk into reset, use atomic updates */
2195 SETPLL(sc, RADEON_PPLL_CNTL,
2196 RADEON_PPLL_REFCLK_SEL |
2197 RADEON_PPLL_FBCLK_SEL |
2198 RADEON_PPLL_RESET |
2199 RADEON_PPLL_ATOMIC_UPDATE_EN |
2200 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN);
2201
2202 /* select clock 0 */
2203 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0,
2204 ~RADEON_PLL_DIV_SEL);
2205
2206 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv);
2207
2208 /* xf86-video-radeon does this, not sure why */
2209 PUTPLL(sc, RADEON_PPLL_DIV_0, div0);
2210 PUTPLL(sc, RADEON_PPLL_DIV_0, div0);
2211
2212 /* use the atomic update */
2213 radeonfb_pllwriteupdate(sc, crtc);
2214
2215 /* and wait for it to complete */
2216 radeonfb_pllwaitatomicread(sc, crtc);
2217
2218 /* program HTOTAL (why?) */
2219 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0);
2220
2221 /* drop reset */
2222 CLRPLL(sc, RADEON_PPLL_CNTL,
2223 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP |
2224 RADEON_PPLL_ATOMIC_UPDATE_EN |
2225 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN);
2226
2227 PRINTPLL(RADEON_PPLL_CNTL);
2228 PRINTPLL(RADEON_PPLL_REF_DIV);
2229 PRINTPLL(RADEON_PPLL_DIV_3);
2230
2231 /* give clock time to lock */
2232 delay(50000);
2233
2234 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL,
2235 RADEON_VCLK_SRC_SEL_PPLLCLK,
2236 ~RADEON_VCLK_SRC_SEL_MASK);
2237
2238 } else {
2239
2240 PATCHPLL(sc, RADEON_PIXCLKS_CNTL,
2241 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
2242 ~RADEON_PIX2CLK_SRC_SEL_MASK);
2243
2244 /* put vclk into reset, use atomic updates */
2245 SETPLL(sc, RADEON_P2PLL_CNTL,
2246 RADEON_P2PLL_RESET |
2247 RADEON_P2PLL_ATOMIC_UPDATE_EN |
2248 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN);
2249
2250 /* program reference divider */
2251 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv,
2252 ~RADEON_P2PLL_REF_DIV_MASK);
2253
2254 /* program feedback and post dividers */
2255 data = GETPLL(sc, RADEON_P2PLL_DIV_0);
2256 data &= ~(RADEON_P2PLL_FB0_DIV_MASK |
2257 RADEON_P2PLL_POST0_DIV_MASK);
2258 data |= pbit;
2259 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK);
2260 PUTPLL(sc, RADEON_P2PLL_DIV_0, data);
2261 PUTPLL(sc, RADEON_P2PLL_DIV_0, data);
2262
2263 PRINTPLL(RADEON_P2PLL_REF_DIV);
2264 PRINTPLL(RADEON_P2PLL_DIV_0);
2265
2266 /* use the atomic update */
2267 radeonfb_pllwriteupdate(sc, crtc);
2268
2269 /* and wait for it to complete */
2270 radeonfb_pllwaitatomicread(sc, crtc);
2271
2272 /* program HTOTAL (why?) */
2273 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0);
2274
2275 /* drop reset */
2276 CLRPLL(sc, RADEON_P2PLL_CNTL,
2277 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP |
2278 RADEON_P2PLL_ATOMIC_UPDATE_EN |
2279 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN);
2280
2281 /* allow time for clock to lock */
2282 delay(50000);
2283
2284 PATCHPLL(sc, RADEON_PIXCLKS_CNTL,
2285 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
2286 ~RADEON_PIX2CLK_SRC_SEL_MASK);
2287 }
2288 PRINTREG(RADEON_CRTC_MORE_CNTL);
2289 }
2290
2291 void
radeonfb_modeswitch(struct radeonfb_display * dp)2292 radeonfb_modeswitch(struct radeonfb_display *dp)
2293 {
2294 struct radeonfb_softc *sc = dp->rd_softc;
2295 int i;
2296
2297 if (IS_AVIVO(sc)) {
2298 /*
2299 * no actual mode setting yet, we just make sure the CRTCs
2300 * point at the right memory ranges and use the same pitch
2301 * for the drawing engine
2302 */
2303 if (GET32(sc, AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) {
2304 CLR32(sc, AVIVO_D1GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE);
2305 dp->rd_stride = GET32(sc, AVIVO_D1GRPH_PITCH);
2306 PUT32(sc, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, 0);
2307 }
2308 if (GET32(sc, AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) {
2309 CLR32(sc, AVIVO_D2GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE);
2310 dp->rd_stride = GET32(sc, AVIVO_D2GRPH_PITCH);
2311 PUT32(sc, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, 0);
2312 }
2313 return;
2314 }
2315
2316 /* blank the display while we switch modes */
2317 //radeonfb_blank(dp, 1);
2318
2319 #if 0
2320 SET32(sc, RADEON_CRTC_EXT_CNTL,
2321 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS |
2322 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */);
2323 #endif
2324
2325 /* these registers might get in the way... */
2326 PUT32(sc, RADEON_OVR_CLR, 0);
2327 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0);
2328 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0);
2329 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0);
2330 PUT32(sc, RADEON_SUBPIC_CNTL, 0);
2331 PUT32(sc, RADEON_VIPH_CONTROL, 0);
2332 PUT32(sc, RADEON_I2C_CNTL_1, 0);
2333 PUT32(sc, RADEON_GEN_INT_CNTL, 0);
2334 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0);
2335 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0);
2336
2337 for (i = 0; i < dp->rd_ncrtcs; i++)
2338 radeonfb_setcrtc(dp, i);
2339
2340 #if 0
2341 /*
2342 * DVO chip voodoo from xf86-video-radeon
2343 * apparently this is needed for some powerbooks with DVI outputs
2344 */
2345
2346 uint8_t data[5][2] = {{0x8, 0x030}, {0x9, 0}, {0xa, 0x90}, {0xc, 0x89}, {0x8, 0x3b}};
2347 int n = 0;
2348 iic_acquire_bus(&sc->sc_i2c[0].ric_controller, 0);
2349 for (i = 0; i < 5; i++)
2350 n += iic_exec(&sc->sc_i2c[0].ric_controller, I2C_OP_WRITE, 0x38, data[i], 2, NULL, 0, 0);
2351 iic_release_bus(&sc->sc_i2c[0].ric_controller, 0);
2352 printf("n = %d\n", n);
2353 #endif
2354
2355 /* activate the display */
2356 radeonfb_blank(dp, 0);
2357 }
2358
2359 void
radeonfb_setcrtc(struct radeonfb_display * dp,int index)2360 radeonfb_setcrtc(struct radeonfb_display *dp, int index)
2361 {
2362 int crtc, flags = 0;
2363 struct videomode *mode;
2364 struct radeonfb_softc *sc;
2365 struct radeonfb_crtc *cp;
2366 uint32_t v, hd, vd;
2367 uint32_t gencntl;
2368 uint32_t htotaldisp;
2369 uint32_t hsyncstrt;
2370 uint32_t vtotaldisp;
2371 uint32_t vsyncstrt;
2372 uint32_t fphsyncstrt;
2373 uint32_t fpvsyncstrt;
2374 uint32_t fphtotaldisp;
2375 uint32_t fpvtotaldisp;
2376 uint32_t pitch;
2377
2378 sc = dp->rd_softc;
2379
2380 if ((sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) ||
2381 (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_EXT)) {
2382 flags |= NO_ODD_FBDIV;
2383 }
2384
2385 cp = &dp->rd_crtcs[index];
2386 crtc = cp->rc_number;
2387 mode = &cp->rc_videomode;
2388
2389 #if 1
2390 pitch = dp->rd_stride / dp->rd_bpp;
2391 #else
2392 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) /
2393 (sc->sc_maxbpp * 8));
2394 #endif
2395 switch (crtc) {
2396 case 0:
2397 gencntl = RADEON_CRTC_GEN_CNTL;
2398 htotaldisp = RADEON_CRTC_H_TOTAL_DISP;
2399 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID;
2400 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP;
2401 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID;
2402 /* should probably leave those alone on non-LVDS */
2403 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID;
2404 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID;
2405 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP;
2406 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP;
2407 break;
2408 case 1:
2409 gencntl = RADEON_CRTC2_GEN_CNTL;
2410 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP;
2411 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID;
2412 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP;
2413 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID;
2414 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID;
2415 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID;
2416 /* XXX these registers don't seem to exist */
2417 fpvtotaldisp = 0;//RADEON_FP_CRTC2_V_TOTAL_DISP;
2418 fphtotaldisp = 0;//RADEON_FP_CRTC2_H_TOTAL_DISP;
2419 break;
2420 default:
2421 panic("Bad CRTC!");
2422 break;
2423 }
2424
2425 /*
2426 * CRTC_GEN_CNTL - depth, accelerator mode, etc.
2427 */
2428 /* only bother with 32bpp and 8bpp */
2429 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT;
2430
2431 if (crtc == 1) {
2432 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN;
2433 } else {
2434 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN;
2435 }
2436
2437 if (mode->flags & VID_DBLSCAN)
2438 v |= RADEON_CRTC2_DBL_SCAN_EN;
2439
2440 if (mode->flags & VID_INTERLACE)
2441 v |= RADEON_CRTC2_INTERLACE_EN;
2442
2443 if (mode->flags & VID_CSYNC) {
2444 v |= RADEON_CRTC2_CSYNC_EN;
2445 if (crtc == 1)
2446 v |= RADEON_CRTC2_VSYNC_TRISTAT;
2447 }
2448
2449 PUT32(sc, gencntl, v);
2450 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v));
2451
2452 /*
2453 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT
2454 */
2455 v = GET32(sc, RADEON_CRTC_EXT_CNTL);
2456 if (crtc == 0) {
2457 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS |
2458 RADEON_CRTC_DISPLAY_DIS);
2459 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR;
2460 if (mode->flags & VID_CSYNC)
2461 v |= RADEON_CRTC_VSYNC_TRISTAT;
2462 }
2463 /* unconditional turn on CRT, in case first CRTC is DFP */
2464 v |= RADEON_CRTC_CRT_ON;
2465 PUT32(sc, RADEON_CRTC_EXT_CNTL, v);
2466 PRINTREG(RADEON_CRTC_EXT_CNTL);
2467
2468 hd = ((GET32(sc, htotaldisp) >> 16) + 1) * 8;
2469 vd = (GET32(sc, vtotaldisp) >> 16) + 1;
2470 DPRINTF(("res %d x %d\n", hd, vd));
2471
2472 if ((hd != mode->hdisplay) || (vd != mode->vdisplay)) {
2473
2474 /*
2475 * H_TOTAL_DISP
2476 */
2477 v = ((mode->hdisplay / 8) - 1) << 16;
2478 v |= (mode->htotal / 8) - 1;
2479 PRINTREG(RADEON_CRTC_H_TOTAL_DISP);
2480 PUT32(sc, htotaldisp, v);
2481 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
2482 if (fphtotaldisp) {
2483 PRINTREG(RADEON_FP_CRTC_H_TOTAL_DISP);
2484 PUT32(sc, fphtotaldisp, v);
2485 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
2486 }
2487 /*
2488 * H_SYNC_STRT_WID
2489 */
2490 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16);
2491 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */
2492 if (mode->flags & VID_NHSYNC)
2493 v |= RADEON_CRTC_H_SYNC_POL;
2494 PUT32(sc, hsyncstrt, v);
2495 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
2496 if (fphsyncstrt) {
2497 PUT32(sc, fphsyncstrt, v);
2498 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
2499 }
2500
2501 /*
2502 * V_TOTAL_DISP
2503 */
2504 v = ((mode->vdisplay - 1) << 16);
2505 v |= (mode->vtotal - 1);
2506 PUT32(sc, vtotaldisp, v);
2507 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
2508 if (fpvtotaldisp) {
2509 PUT32(sc, fpvtotaldisp, v);
2510 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
2511 }
2512
2513 /*
2514 * V_SYNC_STRT_WID
2515 */
2516 v = ((mode->vsync_end - mode->vsync_start) << 16);
2517 v |= (mode->vsync_start - 1);
2518 if (mode->flags & VID_NVSYNC)
2519 v |= RADEON_CRTC_V_SYNC_POL;
2520 PUT32(sc, vsyncstrt, v);
2521 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
2522 if (fpvsyncstrt) {
2523 PUT32(sc, fpvsyncstrt, v);
2524 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
2525 }
2526 }
2527 radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags);
2528
2529 switch (crtc) {
2530 case 0:
2531 PUT32(sc, RADEON_CRTC_OFFSET, 0);
2532 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0);
2533 PUT32(sc, RADEON_CRTC_PITCH, pitch);
2534 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN);
2535
2536 CLR32(sc, RADEON_CRTC_EXT_CNTL,
2537 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS |
2538 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */);
2539 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B);
2540 PRINTREG(RADEON_CRTC_EXT_CNTL);
2541 PRINTREG(RADEON_CRTC_GEN_CNTL);
2542 PRINTREG(RADEON_CLOCK_CNTL_INDEX);
2543 break;
2544
2545 case 1:
2546 PUT32(sc, RADEON_CRTC2_OFFSET, 0);
2547 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0);
2548 PUT32(sc, RADEON_CRTC2_PITCH, pitch);
2549 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN);
2550 CLR32(sc, RADEON_CRTC2_GEN_CNTL,
2551 RADEON_CRTC2_VSYNC_DIS |
2552 RADEON_CRTC2_HSYNC_DIS |
2553 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B);
2554 PRINTREG(RADEON_CRTC2_GEN_CNTL);
2555 break;
2556 }
2557 }
2558
2559 int
radeonfb_isblank(struct radeonfb_display * dp)2560 radeonfb_isblank(struct radeonfb_display *dp)
2561 {
2562 struct radeonfb_softc *sc = dp->rd_softc;
2563 uint32_t reg, mask;
2564
2565 if(!dp->rd_softc->sc_mapped)
2566 return 1;
2567
2568 if (IS_AVIVO(sc)) {
2569 reg = GET32(sc, AVIVO_D1CRTC_CONTROL);
2570 return ((reg & AVIVO_CRTC_EN) == 0);
2571 }
2572
2573 if (dp->rd_crtcs[0].rc_number) {
2574 reg = RADEON_CRTC2_GEN_CNTL;
2575 mask = RADEON_CRTC2_DISP_DIS;
2576 } else {
2577 reg = RADEON_CRTC_EXT_CNTL;
2578 mask = RADEON_CRTC_DISPLAY_DIS;
2579 }
2580 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0);
2581 }
2582
2583 void
radeonfb_blank(struct radeonfb_display * dp,int blank)2584 radeonfb_blank(struct radeonfb_display *dp, int blank)
2585 {
2586 struct radeonfb_softc *sc = dp->rd_softc;
2587 uint32_t reg, mask;
2588 uint32_t fpreg, fpval;
2589 int i;
2590
2591
2592 if (!sc->sc_mapped)
2593 return;
2594
2595 if(IS_AVIVO(sc)) {
2596
2597 /*
2598 * XXX
2599 * I don't know how to turn the sunc outputs off for DPMS
2600 * power control, so for now just turn the entire CRTC off
2601 */
2602 if (blank) {
2603 CLR32(sc, AVIVO_D1CRTC_CONTROL, AVIVO_CRTC_EN);
2604 CLR32(sc, AVIVO_D2CRTC_CONTROL, AVIVO_CRTC_EN);
2605 } else {
2606 SET32(sc, AVIVO_D1CRTC_CONTROL, AVIVO_CRTC_EN);
2607 SET32(sc, AVIVO_D2CRTC_CONTROL, AVIVO_CRTC_EN);
2608 }
2609 return;
2610 }
2611 /* non-AVIVO case */
2612 for (i = 0; i < dp->rd_ncrtcs; i++) {
2613
2614 if (dp->rd_crtcs[i].rc_number) {
2615 reg = RADEON_CRTC2_GEN_CNTL;
2616 mask = RADEON_CRTC2_DISP_DIS;
2617 fpreg = RADEON_FP2_GEN_CNTL;
2618 fpval = RADEON_FP2_ON;
2619 } else {
2620 reg = RADEON_CRTC_EXT_CNTL;
2621 mask = RADEON_CRTC_DISPLAY_DIS;
2622 fpreg = RADEON_FP_GEN_CNTL;
2623 fpval = RADEON_FP_FPON;
2624 }
2625
2626 if (blank) {
2627 SET32(sc, reg, mask);
2628 CLR32(sc, fpreg, fpval);
2629 } else {
2630 CLR32(sc, reg, mask);
2631 SET32(sc, fpreg, fpval);
2632 }
2633 }
2634 PRINTREG(RADEON_FP_GEN_CNTL);
2635 PRINTREG(RADEON_FP2_GEN_CNTL);
2636 }
2637
2638 void
radeonfb_init_screen(void * cookie,struct vcons_screen * scr,int existing,long * defattr)2639 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing,
2640 long *defattr)
2641 {
2642 struct radeonfb_display *dp = cookie;
2643 struct rasops_info *ri = &scr->scr_ri;
2644
2645 /* initialize font subsystem */
2646 wsfont_init();
2647
2648 scr->scr_flags |= VCONS_LOADFONT;
2649
2650 DPRINTF(("init screen called, existing %d\n", existing));
2651
2652 ri->ri_depth = dp->rd_bpp;
2653 ri->ri_width = dp->rd_virtx;
2654 ri->ri_height = dp->rd_virty;
2655 ri->ri_stride = dp->rd_stride;
2656 ri->ri_flg = RI_CENTER;
2657 switch (ri->ri_depth) {
2658 case 8:
2659 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA;
2660 break;
2661 case 32:
2662 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA;
2663 /* we run radeons in RGB even on SPARC hardware */
2664 ri->ri_rnum = 8;
2665 ri->ri_gnum = 8;
2666 ri->ri_bnum = 8;
2667 ri->ri_rpos = 16;
2668 ri->ri_gpos = 8;
2669 ri->ri_bpos = 0;
2670 break;
2671 }
2672
2673 ri->ri_bits = (void *)dp->rd_fbptr;
2674
2675 #ifdef VCONS_DRAW_INTR
2676 scr->scr_flags |= VCONS_DONT_READ;
2677 #endif
2678
2679 if (existing) {
2680 ri->ri_flg |= RI_CLEAR;
2681
2682 /* start a modeswitch now */
2683 //radeonfb_modeswitch(dp);
2684 }
2685
2686 /*
2687 * XXX: font selection should be based on properties, with some
2688 * normal/reasonable default.
2689 */
2690
2691 /* initialize and look for an initial font */
2692 rasops_init(ri, 0, 0);
2693 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT |
2694 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE;
2695
2696 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight,
2697 dp->rd_virtx / ri->ri_font->fontwidth);
2698
2699 /* enable acceleration */
2700 dp->rd_putchar = ri->ri_ops.putchar;
2701 ri->ri_ops.copyrows = radeonfb_copyrows;
2702 ri->ri_ops.copycols = radeonfb_copycols;
2703 ri->ri_ops.eraserows = radeonfb_eraserows;
2704 ri->ri_ops.erasecols = radeonfb_erasecols;
2705 /* pick a putchar method based on font and Radeon model */
2706 if (ri->ri_font->stride < ri->ri_font->fontwidth) {
2707 /* got a bitmap font */
2708 #if !defined(RADEONFB_ALWAYS_ACCEL_PUTCHAR)
2709 if (IS_R300(dp->rd_softc) && 0) {
2710 /*
2711 * radeonfb_putchar() doesn't work right on some R3xx
2712 * so we use software drawing here, the wrapper just
2713 * makes sure the engine is idle before scribbling
2714 * into vram
2715 */
2716 ri->ri_ops.putchar = radeonfb_putchar_wrapper;
2717 } else
2718 #endif
2719 ri->ri_ops.putchar = radeonfb_putchar;
2720 } else {
2721 /* got an alpha font */
2722 switch(ri->ri_depth) {
2723 case 32:
2724 ri->ri_ops.putchar = radeonfb_putchar_aa32;
2725 break;
2726 case 8:
2727 ri->ri_ops.putchar = radeonfb_putchar_aa8;
2728 break;
2729 default:
2730 /* XXX this should never happen */
2731 panic("%s: depth is not 8 or 32 but we got an" \
2732 " alpha font?!", __func__);
2733 }
2734 }
2735 ri->ri_ops.cursor = radeonfb_cursor;
2736 }
2737
2738 static uint32_t
radeonfb_avivo_INMC(struct radeonfb_softc * sc,uint32_t addr)2739 radeonfb_avivo_INMC(struct radeonfb_softc *sc, uint32_t addr)
2740 {
2741 uint32_t data;
2742
2743 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
2744 (void)GET32(sc, AVIVO_MC_INDEX);
2745 data = GET32(sc, AVIVO_MC_DATA);
2746 PUT32(sc, AVIVO_MC_INDEX, 0);
2747 (void)GET32(sc, AVIVO_MC_INDEX);
2748 return data;
2749 }
2750
2751 static void
radeonfb_avivo_OUTMC(struct radeonfb_softc * sc,uint32_t addr,uint32_t data)2752 radeonfb_avivo_OUTMC(struct radeonfb_softc *sc, uint32_t addr, uint32_t data)
2753 {
2754
2755 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
2756 (void)GET32(sc, AVIVO_MC_INDEX);
2757 PUT32(sc, AVIVO_MC_DATA, data);
2758 PUT32(sc, AVIVO_MC_INDEX, 0);
2759 (void)GET32(sc, AVIVO_MC_INDEX);
2760 }
2761
2762 void
radeonfb_set_fbloc(struct radeonfb_softc * sc)2763 radeonfb_set_fbloc(struct radeonfb_softc *sc)
2764 {
2765 uint32_t gen = 0, ext = 0, gen2 = 0;
2766 uint32_t agploc, aperbase, apersize, mcfbloc;
2767
2768
2769 if (IS_AVIVO(sc)) {
2770 agploc = radeonfb_avivo_INMC(sc, R520_MC_AGP_LOCATION);
2771 } else {
2772 gen = GET32(sc, RADEON_CRTC_GEN_CNTL);
2773 /* XXX */
2774 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS;
2775 agploc = GET32(sc, RADEON_MC_AGP_LOCATION);
2776 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B);
2777 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS);
2778 #if 0
2779 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS);
2780 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B);
2781 #endif
2782
2783 if (HAS_CRTC2(sc)) {
2784 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL);
2785 PUT32(sc, RADEON_CRTC2_GEN_CNTL,
2786 gen2 | RADEON_CRTC2_DISP_REQ_EN_B);
2787 }
2788
2789 delay(100000);
2790 }
2791
2792 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE);
2793 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE);
2794
2795
2796 mcfbloc = (aperbase >> 16) |
2797 ((aperbase + (apersize - 1)) & 0xffff0000);
2798
2799 sc->sc_aperbase = (mcfbloc & 0xffff) << 16;
2800 sc->sc_memsz = apersize;
2801 DPRINTF(("aperbase = %08x\n", aperbase));
2802
2803 if (((agploc & 0xffff) << 16) !=
2804 ((mcfbloc & 0xffff0000U) + 0x10000)) {
2805 agploc = mcfbloc & 0xffff0000U;
2806 agploc |= ((agploc + 0x10000) >> 16);
2807 }
2808
2809 PUT32(sc, RADEON_HOST_PATH_CNTL, 0);
2810
2811 if (IS_AVIVO(sc)) {
2812 radeonfb_avivo_OUTMC(sc, R520_MC_FB_LOCATION, mcfbloc);
2813 radeonfb_avivo_OUTMC(sc, R520_MC_AGP_LOCATION, agploc);
2814 PRINTREG(AVIVO_HDP_FB_LOCATION);
2815 DPRINTF((" FB loc %08x\n", radeonfb_avivo_INMC(sc, R520_MC_FB_LOCATION)));
2816 DPRINTF(("AGP loc %08x\n", radeonfb_avivo_INMC(sc, R520_MC_AGP_LOCATION)));
2817 } else {
2818 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc);
2819 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc);
2820 PRINTREG(RADEON_MC_FB_LOCATION);
2821 PRINTREG(RADEON_MC_AGP_LOCATION);
2822
2823 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase);
2824
2825 if (HAS_CRTC2(sc))
2826 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase);
2827
2828 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase);
2829 delay(100000);
2830
2831 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen);
2832 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext);
2833
2834 if (HAS_CRTC2(sc))
2835 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2);
2836 }
2837 #if 0
2838 /* XXX: what is this AGP garbage? :-) */
2839 PUT32(sc, RADEON_AGP_CNTL, 0x00100000);
2840 #endif
2841 }
2842
2843 void
radeonfb_init_misc(struct radeonfb_softc * sc)2844 radeonfb_init_misc(struct radeonfb_softc *sc)
2845 {
2846 PUT32(sc, RADEON_BUS_CNTL,
2847 RADEON_BUS_MASTER_DIS |
2848 RADEON_BUS_PREFETCH_MODE_ACT |
2849 RADEON_BUS_PCI_READ_RETRY_EN |
2850 RADEON_BUS_PCI_WRT_RETRY_EN |
2851 (3 << RADEON_BUS_RETRY_WS_SHIFT) |
2852 RADEON_BUS_MSTR_RD_MULT |
2853 RADEON_BUS_MSTR_RD_LINE |
2854 RADEON_BUS_RD_DISCARD_EN |
2855 RADEON_BUS_MSTR_DISCONNECT_EN |
2856 RADEON_BUS_READ_BURST);
2857
2858 PUT32(sc, RADEON_BUS_CNTL1, 0xf0);
2859 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */
2860 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND);
2861 PUT32(sc, RADEON_RBBM_CNTL,
2862 (3 << RADEON_RB_SETTLE_SHIFT) |
2863 (4 << RADEON_ABORTCLKS_HI_SHIFT) |
2864 (4 << RADEON_ABORTCLKS_CP_SHIFT) |
2865 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT));
2866
2867 /* XXX: figure out what these mean! */
2868 PUT32(sc, RADEON_AGP_CNTL, 0x00100000);
2869 PUT32(sc, RADEON_HOST_PATH_CNTL, 0);
2870 #if 0
2871 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400);
2872 #endif
2873
2874 PUT32(sc, RADEON_GEN_INT_CNTL, 0);
2875 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS));
2876 }
2877
2878 static void
radeonfb_putpal(struct radeonfb_display * dp,int idx,int r,int g,int b)2879 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b)
2880 {
2881 struct radeonfb_softc *sc = dp->rd_softc;
2882 int crtc, cc;
2883 uint32_t vclk;
2884
2885 if (IS_AVIVO(sc)) {
2886 for (cc = 0; cc < dp->rd_ncrtcs; cc++) {
2887 crtc = dp->rd_crtcs[cc].rc_number;
2888
2889 if (crtc)
2890 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 1);
2891 else
2892 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 0);
2893
2894 PUT32(sc, AVIVO_DC_LUT_RW_INDEX, idx);
2895 PUT32(sc, AVIVO_DC_LUT_30_COLOR,
2896 (r << 22) | (g << 12) | (b << 2));
2897 }
2898
2899 } else {
2900 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL);
2901 PUTPLL(sc, RADEON_VCLK_ECP_CNTL,
2902 vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb);
2903
2904 /* init the palette for every CRTC used by this display */
2905 for (cc = 0; cc < dp->rd_ncrtcs; cc++) {
2906 crtc = dp->rd_crtcs[cc].rc_number;
2907
2908 if (crtc)
2909 SET32(sc, RADEON_DAC_CNTL2,
2910 RADEON_DAC2_PALETTE_ACC_CTL);
2911 else
2912 CLR32(sc, RADEON_DAC_CNTL2,
2913 RADEON_DAC2_PALETTE_ACC_CTL);
2914
2915 PUT32(sc, RADEON_PALETTE_INDEX, idx);
2916 PUT32(sc, RADEON_PALETTE_30_DATA,
2917 (r << 22) | (g << 12) | (b << 2));
2918 }
2919
2920 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk);
2921 }
2922 }
2923
2924 /*
2925 * This loads a linear color map for true color.
2926 */
2927 void
radeonfb_init_palette(struct radeonfb_display * dp)2928 radeonfb_init_palette(struct radeonfb_display *dp)
2929 {
2930 int i;
2931
2932 #define DAC_WIDTH ((1 << 10) - 1)
2933 #define CLUT_WIDTH ((1 << 8) - 1)
2934 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2)
2935
2936 if (dp->rd_bpp == 8) {
2937
2938 /* R3G3B2 palette */
2939 uint32_t tmp, r, g, b;
2940
2941 for (i = 0; i <= CLUT_WIDTH; ++i) {
2942 tmp = i & 0xe0;
2943
2944 /*
2945 * replicate bits so 0xe0 maps to a red value of 0xff
2946 * in order to make white look actually white
2947 */
2948 tmp |= (tmp >> 3) | (tmp >> 6);
2949 r = tmp;
2950
2951 tmp = (i & 0x1c) << 3;
2952 tmp |= (tmp >> 3) | (tmp >> 6);
2953 g = tmp;
2954
2955 tmp = (i & 0x03) << 6;
2956 tmp |= tmp >> 2;
2957 tmp |= tmp >> 4;
2958 b = tmp;
2959
2960 dp->rd_cmap_red[i] = r;
2961 dp->rd_cmap_green[i] = g;
2962 dp->rd_cmap_blue[i] = b;
2963 radeonfb_putpal(dp, i, r, g, b);
2964 }
2965 } else {
2966 /* linear ramp */
2967 for (i = 0; i <= CLUT_WIDTH; ++i) {
2968 radeonfb_putpal(dp, i, i, i, i);
2969 }
2970 }
2971 }
2972
2973 static int
radeonfb_putcmap(struct radeonfb_display * dp,struct wsdisplay_cmap * cm)2974 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm)
2975 {
2976 u_char *r, *g, *b;
2977 u_int index = cm->index;
2978 u_int count = cm->count;
2979 int i, error;
2980 u_char rbuf[256], gbuf[256], bbuf[256];
2981
2982 #ifdef GENFB_DEBUG
2983 aprint_debug("putcmap: %d %d\n",index, count);
2984 #endif
2985 if (index >= 256 || count > 256 - index)
2986 return EINVAL;
2987 error = copyin(cm->red, &rbuf[index], count);
2988 if (error)
2989 return error;
2990 error = copyin(cm->green, &gbuf[index], count);
2991 if (error)
2992 return error;
2993 error = copyin(cm->blue, &bbuf[index], count);
2994 if (error)
2995 return error;
2996
2997 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count);
2998 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count);
2999 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count);
3000
3001 r = &dp->rd_cmap_red[index];
3002 g = &dp->rd_cmap_green[index];
3003 b = &dp->rd_cmap_blue[index];
3004
3005 for (i = 0; i < count; i++) {
3006 radeonfb_putpal(dp, index, *r, *g, *b);
3007 index++;
3008 r++, g++, b++;
3009 }
3010 return 0;
3011 }
3012
3013 static int
radeonfb_getcmap(struct radeonfb_display * dp,struct wsdisplay_cmap * cm)3014 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm)
3015 {
3016 u_int index = cm->index;
3017 u_int count = cm->count;
3018 int error;
3019
3020 if (index >= 256 || count > 256 - index)
3021 return EINVAL;
3022
3023 error = copyout(&dp->rd_cmap_red[index], cm->red, count);
3024 if (error)
3025 return error;
3026 error = copyout(&dp->rd_cmap_green[index], cm->green, count);
3027 if (error)
3028 return error;
3029 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count);
3030 if (error)
3031 return error;
3032
3033 return 0;
3034 }
3035
3036 /*
3037 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX.
3038 */
3039 void
radeonfb_r300cg_workaround(struct radeonfb_softc * sc)3040 radeonfb_r300cg_workaround(struct radeonfb_softc *sc)
3041 {
3042 uint32_t tmp, save;
3043
3044 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX);
3045 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
3046 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp);
3047 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA);
3048 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save);
3049 }
3050
3051 /*
3052 * Acceleration entry points.
3053 */
3054
3055 /* this one draws characters using bitmap fonts */
3056 static void
radeonfb_putchar(void * cookie,int row,int col,u_int c,long attr)3057 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr)
3058 {
3059 struct rasops_info *ri = cookie;
3060 struct vcons_screen *scr = ri->ri_hw;
3061 struct radeonfb_display *dp = scr->scr_cookie;
3062 struct radeonfb_softc *sc = dp->rd_softc;
3063 struct wsdisplay_font *font = PICK_FONT(ri, c);
3064 uint32_t w, h;
3065 int xd, yd, offset, i;
3066 uint32_t bg, fg, gmc;
3067 uint32_t reg;
3068 uint8_t *data8;
3069 uint16_t *data16;
3070 uint32_t *data32;
3071 void *data;
3072
3073 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL)
3074 return;
3075
3076 if (!CHAR_IN_FONT(c, font))
3077 return;
3078
3079 w = font->fontwidth;
3080 h = font->fontheight;
3081
3082 bg = ri->ri_devcmap[(attr >> 16) & 0xf];
3083 fg = ri->ri_devcmap[(attr >> 24) & 0xf];
3084
3085 xd = ri->ri_xorigin + col * w;
3086 yd = ri->ri_yorigin + row * h;
3087
3088 if (c == 0x20) {
3089 radeonfb_rectfill(dp, xd, yd, w, h, bg);
3090 return;
3091 }
3092 data = WSFONT_GLYPH(c, font);
3093
3094 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
3095
3096 radeonfb_wait_fifo(sc, 9);
3097
3098 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3099 RADEON_GMC_BRUSH_NONE |
3100 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG |
3101 RADEON_GMC_DST_CLIPPING |
3102 RADEON_ROP3_S |
3103 RADEON_DP_SRC_SOURCE_HOST_DATA |
3104 RADEON_GMC_CLR_CMP_CNTL_DIS |
3105 RADEON_GMC_WR_MSK_DIS |
3106 gmc);
3107
3108 PUT32(sc, RADEON_SC_LEFT, xd);
3109 PUT32(sc, RADEON_SC_RIGHT, xd + w);
3110 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg);
3111 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg);
3112 PUT32(sc, RADEON_DP_CNTL,
3113 RADEON_DST_X_LEFT_TO_RIGHT |
3114 RADEON_DST_Y_TOP_TO_BOTTOM);
3115
3116 PUT32(sc, RADEON_SRC_X_Y, 0);
3117 offset = 32 - (font->stride << 3);
3118 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd);
3119 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h);
3120
3121 radeonfb_wait_fifo(sc, h);
3122 switch (font->stride) {
3123 case 1: {
3124 data8 = data;
3125 for (i = 0; i < h; i++) {
3126 reg = *data8;
3127 #if BYTE_ORDER == LITTLE_ENDIAN
3128 reg = reg << 24;
3129 #endif
3130 bus_space_write_stream_4(sc->sc_regt,
3131 sc->sc_regh, RADEON_HOST_DATA0, reg);
3132 data8++;
3133 }
3134 break;
3135 }
3136 case 2: {
3137 data16 = data;
3138 for (i = 0; i < h; i++) {
3139 reg = *data16;
3140 #if BYTE_ORDER == LITTLE_ENDIAN
3141 reg = reg << 16;
3142 #endif
3143 bus_space_write_stream_4(sc->sc_regt,
3144 sc->sc_regh, RADEON_HOST_DATA0, reg);
3145 data16++;
3146 }
3147 break;
3148 }
3149 case 4: {
3150 data32 = data;
3151 for (i = 0; i < h; i++) {
3152 reg = *data32;
3153 bus_space_write_stream_4(sc->sc_regt,
3154 sc->sc_regh, RADEON_HOST_DATA0, reg);
3155 data32++;
3156 }
3157 break;
3158 }
3159 }
3160 if (attr & 1)
3161 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg);
3162 }
3163
3164 /* ... while this one is for anti-aliased ones */
3165 static void
radeonfb_putchar_aa32(void * cookie,int row,int col,u_int c,long attr)3166 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr)
3167 {
3168 struct rasops_info *ri = cookie;
3169 struct vcons_screen *scr = ri->ri_hw;
3170 struct radeonfb_display *dp = scr->scr_cookie;
3171 struct radeonfb_softc *sc = dp->rd_softc;
3172 struct wsdisplay_font *font = PICK_FONT(ri, c);
3173 uint32_t bg, fg, gmc;
3174 uint8_t *data;
3175 int w, h, xd, yd;
3176 int i, r, g, b, aval;
3177 int rf, gf, bf, rb, gb, bb;
3178 uint32_t pixel;
3179 int rv;
3180
3181 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL)
3182 return;
3183
3184 if (!CHAR_IN_FONT(c, font))
3185 return;
3186
3187 w = font->fontwidth;
3188 h = font->fontheight;
3189
3190 bg = ri->ri_devcmap[(attr >> 16) & 0xf];
3191 fg = ri->ri_devcmap[(attr >> 24) & 0xf];
3192
3193 xd = ri->ri_xorigin + col * w;
3194 yd = ri->ri_yorigin + row * h;
3195
3196 if (c == 0x20) {
3197 radeonfb_rectfill(dp, xd, yd, w, h, bg);
3198 if (attr & 1)
3199 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg);
3200 return;
3201 }
3202 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr);
3203 if (rv == GC_OK)
3204 return;
3205
3206 data = WSFONT_GLYPH(c, font);
3207
3208 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
3209
3210 radeonfb_wait_fifo(sc, 5);
3211
3212 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3213 RADEON_GMC_BRUSH_NONE |
3214 RADEON_GMC_SRC_DATATYPE_COLOR |
3215 RADEON_ROP3_S |
3216 RADEON_DP_SRC_SOURCE_HOST_DATA |
3217 RADEON_GMC_CLR_CMP_CNTL_DIS |
3218 RADEON_GMC_WR_MSK_DIS |
3219 gmc);
3220
3221 PUT32(sc, RADEON_DP_CNTL,
3222 RADEON_DST_X_LEFT_TO_RIGHT |
3223 RADEON_DST_Y_TOP_TO_BOTTOM);
3224
3225 PUT32(sc, RADEON_SRC_X_Y, 0);
3226 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd);
3227 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h);
3228
3229 rf = (fg >> 16) & 0xff;
3230 rb = (bg >> 16) & 0xff;
3231 gf = (fg >> 8) & 0xff;
3232 gb = (bg >> 8) & 0xff;
3233 bf = fg & 0xff;
3234 bb = bg & 0xff;
3235
3236 /*
3237 * I doubt we can upload data faster than even the slowest Radeon
3238 * could process them, especially when doing the alpha blending stuff
3239 * along the way, so just make sure there's some room in the FIFO and
3240 * then hammer away
3241 * As it turns out we can, so make periodic stops to let the FIFO
3242 * drain.
3243 */
3244 radeonfb_wait_fifo(sc, 20);
3245 for (i = 0; i < ri->ri_fontscale; i++) {
3246 aval = *data;
3247 data++;
3248 if (aval == 0) {
3249 pixel = bg;
3250 } else if (aval == 255) {
3251 pixel = fg;
3252 } else {
3253 r = aval * rf + (255 - aval) * rb;
3254 g = aval * gf + (255 - aval) * gb;
3255 b = aval * bf + (255 - aval) * bb;
3256 pixel = (r & 0xff00) << 8 |
3257 (g & 0xff00) |
3258 (b & 0xff00) >> 8;
3259 }
3260 if (i & 16)
3261 radeonfb_wait_fifo(sc, 20);
3262 PUT32(sc, RADEON_HOST_DATA0, pixel);
3263 }
3264 if (rv == GC_ADD) {
3265 glyphcache_add(&dp->rd_gc, c, xd, yd);
3266 } else if (attr & 1)
3267 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg);
3268 }
3269
3270 static void
radeonfb_putchar_aa8(void * cookie,int row,int col,u_int c,long attr)3271 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr)
3272 {
3273 struct rasops_info *ri = cookie;
3274 struct vcons_screen *scr = ri->ri_hw;
3275 struct radeonfb_display *dp = scr->scr_cookie;
3276 struct radeonfb_softc *sc = dp->rd_softc;
3277 struct wsdisplay_font *font = PICK_FONT(ri, c);
3278 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc;
3279 int i, x, y, wi, he, r, g, b, aval;
3280 int r1, g1, b1, r0, g0, b0, fgo, bgo;
3281 uint8_t *data8;
3282 int rv, cnt;
3283
3284 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL)
3285 return;
3286
3287 if (!CHAR_IN_FONT(c, font))
3288 return;
3289
3290 wi = font->fontwidth;
3291 he = font->fontheight;
3292
3293 bg = ri->ri_devcmap[(attr >> 16) & 0xf];
3294 fg = ri->ri_devcmap[(attr >> 24) & 0xf];
3295
3296 x = ri->ri_xorigin + col * wi;
3297 y = ri->ri_yorigin + row * he;
3298
3299 if (c == 0x20) {
3300 radeonfb_rectfill(dp, x, y, wi, he, bg);
3301 if (attr & 1)
3302 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg);
3303 return;
3304 }
3305 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr);
3306 if (rv == GC_OK)
3307 return;
3308
3309 data8 = WSFONT_GLYPH(c, font);
3310
3311 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
3312
3313 radeonfb_wait_fifo(sc, 5);
3314
3315 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3316 RADEON_GMC_BRUSH_NONE |
3317 RADEON_GMC_SRC_DATATYPE_COLOR |
3318 RADEON_ROP3_S |
3319 RADEON_DP_SRC_SOURCE_HOST_DATA |
3320 RADEON_GMC_CLR_CMP_CNTL_DIS |
3321 RADEON_GMC_WR_MSK_DIS |
3322 gmc);
3323
3324 PUT32(sc, RADEON_DP_CNTL,
3325 RADEON_DST_X_LEFT_TO_RIGHT |
3326 RADEON_DST_Y_TOP_TO_BOTTOM);
3327
3328 PUT32(sc, RADEON_SRC_X_Y, 0);
3329 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y);
3330 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he);
3331
3332 /*
3333 * we need the RGB colours here, so get offsets into rasops_cmap
3334 */
3335 fgo = ((attr >> 24) & 0xf) * 3;
3336 bgo = ((attr >> 16) & 0xf) * 3;
3337
3338 r0 = rasops_cmap[bgo];
3339 r1 = rasops_cmap[fgo];
3340 g0 = rasops_cmap[bgo + 1];
3341 g1 = rasops_cmap[fgo + 1];
3342 b0 = rasops_cmap[bgo + 2];
3343 b1 = rasops_cmap[fgo + 2];
3344 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6))
3345 bg8 = R3G3B2(r0, g0, b0);
3346 fg8 = R3G3B2(r1, g1, b1);
3347
3348 radeonfb_wait_fifo(sc, 20);
3349 cnt = 0;
3350 for (i = 0; i < ri->ri_fontscale; i++) {
3351 aval = *data8;
3352 if (aval == 0) {
3353 pixel = bg8;
3354 } else if (aval == 255) {
3355 pixel = fg8;
3356 } else {
3357 r = aval * r1 + (255 - aval) * r0;
3358 g = aval * g1 + (255 - aval) * g0;
3359 b = aval * b1 + (255 - aval) * b0;
3360 pixel = ((r & 0xe000) >> 8) |
3361 ((g & 0xe000) >> 11) |
3362 ((b & 0xc000) >> 14);
3363 }
3364 latch |= pixel << (8 * (i & 3));
3365 /* write in 32bit chunks */
3366 if ((i & 3) == 3) {
3367 PUT32(sc, RADEON_HOST_DATA0, latch);
3368 /*
3369 * not strictly necessary, old data should be shifted
3370 * out
3371 */
3372 latch = 0;
3373 cnt++;
3374 if (cnt > 16) {
3375 cnt = 0;
3376 radeonfb_wait_fifo(sc, 20);
3377 }
3378 }
3379 data8++;
3380 }
3381 /* if we have pixels left in latch write them out */
3382 if ((i & 3) != 0) {
3383 /*
3384 * radeon is weird - apparently leftover pixels are written
3385 * from the middle, not from the left as everything else
3386 */
3387 PUT32(sc, RADEON_HOST_DATA0, latch);
3388 }
3389
3390 if (rv == GC_ADD) {
3391 glyphcache_add(&dp->rd_gc, c, x, y);
3392 } else
3393 if (attr & 1)
3394 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg);
3395 }
3396
3397 /*
3398 * wrapper for software character drawing
3399 * just sync the engine and call rasops*_putchar()
3400 */
3401
3402 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR
3403 static void
radeonfb_putchar_wrapper(void * cookie,int row,int col,u_int c,long attr)3404 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr)
3405 {
3406 struct rasops_info *ri = cookie;
3407 struct vcons_screen *scr = ri->ri_hw;
3408 struct radeonfb_display *dp = scr->scr_cookie;
3409
3410 radeonfb_engine_idle(dp->rd_softc);
3411 dp->rd_putchar(ri, row, col, c, attr);
3412 }
3413 #endif
3414
3415 static void
radeonfb_eraserows(void * cookie,int row,int nrows,long fillattr)3416 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr)
3417 {
3418 struct rasops_info *ri = cookie;
3419 struct vcons_screen *scr = ri->ri_hw;
3420 struct radeonfb_display *dp = scr->scr_cookie;
3421 uint32_t x, y, w, h, fg, bg, ul;
3422
3423 /* XXX: check for full emulation mode? */
3424 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
3425 x = ri->ri_xorigin;
3426 y = ri->ri_yorigin + ri->ri_font->fontheight * row;
3427 w = ri->ri_emuwidth;
3428 h = ri->ri_font->fontheight * nrows;
3429
3430 rasops_unpack_attr(fillattr, &fg, &bg, &ul);
3431 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]);
3432 }
3433 }
3434
3435 static void
radeonfb_copyrows(void * cookie,int srcrow,int dstrow,int nrows)3436 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows)
3437 {
3438 struct rasops_info *ri = cookie;
3439 struct vcons_screen *scr = ri->ri_hw;
3440 struct radeonfb_display *dp = scr->scr_cookie;
3441 uint32_t x, ys, yd, w, h;
3442
3443 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
3444 x = ri->ri_xorigin;
3445 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow;
3446 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow;
3447 w = ri->ri_emuwidth;
3448 h = ri->ri_font->fontheight * nrows;
3449 radeonfb_bitblt(dp, x, ys, x, yd, w, h,
3450 RADEON_ROP3_S);
3451 }
3452 }
3453
3454 static void
radeonfb_copycols(void * cookie,int row,int srccol,int dstcol,int ncols)3455 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols)
3456 {
3457 struct rasops_info *ri = cookie;
3458 struct vcons_screen *scr = ri->ri_hw;
3459 struct radeonfb_display *dp = scr->scr_cookie;
3460 uint32_t xs, xd, y, w, h;
3461
3462 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
3463 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol;
3464 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol;
3465 y = ri->ri_yorigin + ri->ri_font->fontheight * row;
3466 w = ri->ri_font->fontwidth * ncols;
3467 h = ri->ri_font->fontheight;
3468 radeonfb_bitblt(dp, xs, y, xd, y, w, h,
3469 RADEON_ROP3_S);
3470 }
3471 }
3472
3473 static void
radeonfb_erasecols(void * cookie,int row,int startcol,int ncols,long fillattr)3474 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols,
3475 long fillattr)
3476 {
3477 struct rasops_info *ri = cookie;
3478 struct vcons_screen *scr = ri->ri_hw;
3479 struct radeonfb_display *dp = scr->scr_cookie;
3480 uint32_t x, y, w, h, fg, bg, ul;
3481
3482 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
3483 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol;
3484 y = ri->ri_yorigin + ri->ri_font->fontheight * row;
3485 w = ri->ri_font->fontwidth * ncols;
3486 h = ri->ri_font->fontheight;
3487
3488 rasops_unpack_attr(fillattr, &fg, &bg, &ul);
3489 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]);
3490 }
3491 }
3492
3493 static void
radeonfb_cursor(void * cookie,int on,int row,int col)3494 radeonfb_cursor(void *cookie, int on, int row, int col)
3495 {
3496 struct rasops_info *ri = cookie;
3497 struct vcons_screen *scr = ri->ri_hw;
3498 struct radeonfb_display *dp = scr->scr_cookie;
3499 int x, y, wi, he;
3500
3501 wi = ri->ri_font->fontwidth;
3502 he = ri->ri_font->fontheight;
3503
3504 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
3505 x = ri->ri_ccol * wi + ri->ri_xorigin;
3506 y = ri->ri_crow * he + ri->ri_yorigin;
3507 /* first turn off the old cursor */
3508 if (ri->ri_flg & RI_CURSOR) {
3509 radeonfb_bitblt(dp, x, y, x, y, wi, he,
3510 RADEON_ROP3_Dn);
3511 ri->ri_flg &= ~RI_CURSOR;
3512 }
3513 ri->ri_crow = row;
3514 ri->ri_ccol = col;
3515 /* then (possibly) turn on the new one */
3516 if (on) {
3517 x = ri->ri_ccol * wi + ri->ri_xorigin;
3518 y = ri->ri_crow * he + ri->ri_yorigin;
3519 radeonfb_bitblt(dp, x, y, x, y, wi, he,
3520 RADEON_ROP3_Dn);
3521 ri->ri_flg |= RI_CURSOR;
3522 }
3523 } else {
3524 scr->scr_ri.ri_crow = row;
3525 scr->scr_ri.ri_ccol = col;
3526 scr->scr_ri.ri_flg &= ~RI_CURSOR;
3527 }
3528 }
3529
3530 /*
3531 * Underlying acceleration support.
3532 */
3533
3534 static void
radeonfb_rectfill(struct radeonfb_display * dp,int dstx,int dsty,int width,int height,uint32_t color)3535 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty,
3536 int width, int height, uint32_t color)
3537 {
3538 struct radeonfb_softc *sc = dp->rd_softc;
3539 uint32_t gmc;
3540
3541 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
3542
3543 radeonfb_wait_fifo(sc, 6);
3544
3545 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3546 RADEON_GMC_BRUSH_SOLID_COLOR |
3547 RADEON_GMC_SRC_DATATYPE_COLOR |
3548 RADEON_GMC_CLR_CMP_CNTL_DIS |
3549 RADEON_ROP3_P | gmc);
3550
3551 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color);
3552 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
3553 PUT32(sc, RADEON_DP_CNTL,
3554 RADEON_DST_X_LEFT_TO_RIGHT |
3555 RADEON_DST_Y_TOP_TO_BOTTOM);
3556 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx);
3557 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height));
3558 }
3559
3560 static void
radeonfb_rectfill_a(void * cookie,int dstx,int dsty,int width,int height,long attr)3561 radeonfb_rectfill_a(void *cookie, int dstx, int dsty,
3562 int width, int height, long attr)
3563 {
3564 struct radeonfb_display *dp = cookie;
3565
3566 radeonfb_rectfill(dp, dstx, dsty, width, height,
3567 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]);
3568 }
3569
3570 static void
radeonfb_bitblt(void * cookie,int srcx,int srcy,int dstx,int dsty,int width,int height,int rop)3571 radeonfb_bitblt(void *cookie, int srcx, int srcy,
3572 int dstx, int dsty, int width, int height, int rop)
3573 {
3574 struct radeonfb_display *dp = cookie;
3575 struct radeonfb_softc *sc = dp->rd_softc;
3576 uint32_t gmc;
3577 uint32_t dir;
3578
3579 if (dsty < srcy) {
3580 dir = RADEON_DST_Y_TOP_TO_BOTTOM;
3581 } else {
3582 srcy += height - 1;
3583 dsty += height - 1;
3584 dir = 0;
3585 }
3586 if (dstx < srcx) {
3587 dir |= RADEON_DST_X_LEFT_TO_RIGHT;
3588 } else {
3589 srcx += width - 1;
3590 dstx += width - 1;
3591 }
3592
3593 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
3594
3595 radeonfb_wait_fifo(sc, 6);
3596
3597 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3598 RADEON_GMC_BRUSH_NONE |
3599 RADEON_GMC_SRC_DATATYPE_COLOR |
3600 RADEON_GMC_CLR_CMP_CNTL_DIS |
3601 RADEON_DP_SRC_SOURCE_MEMORY |
3602 rop | gmc);
3603
3604 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
3605 PUT32(sc, RADEON_DP_CNTL, dir);
3606 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx);
3607 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx);
3608 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height));
3609 }
3610
3611 static void
radeonfb_engine_idle(struct radeonfb_softc * sc)3612 radeonfb_engine_idle(struct radeonfb_softc *sc)
3613 {
3614
3615 radeonfb_wait_fifo(sc, 64);
3616 while ((GET32(sc, RADEON_RBBM_STATUS) &
3617 RADEON_RBBM_ACTIVE) != 0);
3618 radeonfb_engine_flush(sc);
3619 }
3620
3621 static inline void
radeonfb_wait_fifo(struct radeonfb_softc * sc,int n)3622 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n)
3623 {
3624 int i;
3625
3626 for (i = RADEON_TIMEOUT; i; i--) {
3627 if ((GET32(sc, RADEON_RBBM_STATUS) &
3628 RADEON_RBBM_FIFOCNT_MASK) >= n)
3629 return;
3630 }
3631 #ifdef RADEONFB_DEBUG
3632 if (!i)
3633 printf("%s: timed out waiting for fifo (%x)\n",
3634 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS));
3635 #endif
3636 }
3637
3638 static void
radeonfb_engine_flush(struct radeonfb_softc * sc)3639 radeonfb_engine_flush(struct radeonfb_softc *sc)
3640 {
3641 int i = 0;
3642
3643 if (IS_R300(sc) || IS_AVIVO(sc)) {
3644 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL);
3645 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) {
3646 i++;
3647 }
3648 } else {
3649 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT,
3650 RADEON_RB2D_DC_FLUSH_ALL);
3651 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) &
3652 RADEON_RB2D_DC_BUSY) {
3653 i++;
3654 }
3655 }
3656 #ifdef DIAGNOSTIC
3657 if (i > RADEON_TIMEOUT)
3658 printf("%s: engine flush timed out!\n", XNAME(sc));
3659 #endif
3660 }
3661
3662 static inline void
radeonfb_unclip(struct radeonfb_softc * sc)3663 radeonfb_unclip(struct radeonfb_softc *sc)
3664 {
3665
3666 radeonfb_wait_fifo(sc, 2);
3667 PUT32(sc, RADEON_SC_TOP_LEFT, 0);
3668 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff);
3669 }
3670
3671 static void
radeonfb_engine_init(struct radeonfb_display * dp)3672 radeonfb_engine_init(struct radeonfb_display *dp)
3673 {
3674 struct radeonfb_softc *sc = dp->rd_softc;
3675 uint32_t pitch;
3676
3677 /* no 3D */
3678 PUT32(sc, RADEON_RB3D_CNTL, 0);
3679
3680 if (IS_AVIVO(sc)) {
3681
3682 #if 0
3683 /* XXX the xf86-video-radeon does this, causes lockups here */
3684 psel = GET32(sc, R400_GB_PIPE_SELECT);
3685 PRINTREG(R400_GB_PIPE_SELECT);
3686 DPRINTF(("PLL %08x %08x\n", GETPLL(sc, R500_DYN_SCLK_PWMEM_PIPE),
3687 (1 | ((psel >> 8) & 0xf) << 4)));
3688 PUTPLL(sc, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((psel >> 8) & 0xf) << 4));
3689 #endif
3690 SET32(sc, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
3691 SET32(sc, R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
3692 SET32(sc, R300_RB2D_DSTCACHE_MODE, R300_DC_AUTOFLUSH_ENABLE |
3693 R300_DC_DC_DISABLE_IGNORE_PE);
3694 }
3695
3696 PRINTREG(RADEON_RB3D_CNTL);
3697 PRINTREG(RADEON_DP_GUI_MASTER_CNTL);
3698 PRINTREG(RADEON_RBBM_STATUS);
3699
3700 radeonfb_engine_reset(sc);
3701 PRINTREG(RADEON_RBBM_STATUS);
3702
3703 /*
3704 * Apple OF hands us some radeons with tiling enabled - explicitly
3705 * disable it here
3706 */
3707 PUT32(sc, RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS);
3708
3709 radeonfb_wait_fifo(sc, 1);
3710 if (!IS_R300(sc) && !IS_AVIVO(sc))
3711 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0);
3712
3713 radeonfb_wait_fifo(sc, 3);
3714
3715 /*
3716 * XXX
3717 * I strongly suspect this works mostly by accident on !AVIVO
3718 * AVIVO uses all 22 bits for the framebuffer offset, so it can
3719 * address up to 4GB. Older chips probably use bits 20-22 for other
3720 * things and we just so happen to set the right ones by having our
3721 * PCI/AGP space above 0x80000000.
3722 * Either way, r5xx does not work if we set these bits, while older
3723 * chips don't work without.
3724 */
3725 pitch = (dp->rd_stride + 0x3f) >> 6;
3726 if (IS_AVIVO(sc)) {
3727 pitch = pitch << 22;
3728 } else
3729 pitch = (pitch << 22) | (sc->sc_aperbase >> 10);
3730
3731 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, pitch);
3732 PUT32(sc, RADEON_DST_PITCH_OFFSET, pitch);
3733 PUT32(sc, RADEON_SRC_PITCH_OFFSET, pitch);
3734
3735 (void)GET32(sc, RADEON_DP_DATATYPE);
3736
3737 /* default scissors -- no clipping */
3738 radeonfb_wait_fifo(sc, 1);
3739 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT,
3740 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
3741
3742 radeonfb_wait_fifo(sc, 1);
3743 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
3744 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) |
3745 RADEON_GMC_CLR_CMP_CNTL_DIS |
3746 RADEON_GMC_BRUSH_SOLID_COLOR |
3747 RADEON_GMC_SRC_DATATYPE_COLOR);
3748
3749 radeonfb_wait_fifo(sc, 10);
3750 PUT32(sc, RADEON_DST_LINE_START, 0);
3751 PUT32(sc, RADEON_DST_LINE_END, 0);
3752 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
3753 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0);
3754 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff);
3755 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0);
3756 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
3757 PUT32(sc, RADEON_SC_TOP_LEFT, 0);
3758 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff);
3759 PUT32(sc, RADEON_AUX_SC_CNTL, 0);
3760 radeonfb_engine_idle(sc);
3761 }
3762
3763 static void
radeonfb_engine_reset(struct radeonfb_softc * sc)3764 radeonfb_engine_reset(struct radeonfb_softc *sc)
3765 {
3766 uint32_t hpc, rbbm, mclkcntl, clkindex;
3767
3768 radeonfb_engine_flush(sc);
3769
3770 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX);
3771 if (HAS_R300CG(sc))
3772 radeonfb_r300cg_workaround(sc);
3773 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL);
3774
3775 /*
3776 * According to comments in XFree code, resetting the HDP via
3777 * the RBBM_SOFT_RESET can cause bad behavior on some systems.
3778 * So we use HOST_PATH_CNTL instead.
3779 */
3780
3781 hpc = GET32(sc, RADEON_HOST_PATH_CNTL);
3782 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET);
3783 if (IS_R300(sc) || IS_AVIVO(sc)) {
3784 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm |
3785 RADEON_SOFT_RESET_CP |
3786 RADEON_SOFT_RESET_HI |
3787 RADEON_SOFT_RESET_E2);
3788 GET32(sc, RADEON_RBBM_SOFT_RESET);
3789 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0);
3790 /*
3791 * XXX: this bit is not defined in any ATI docs I have,
3792 * nor in the XFree code, but XFree does it. Why?
3793 */
3794 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, R300_DC_DC_DISABLE_IGNORE_PE);
3795 } else {
3796 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm |
3797 RADEON_SOFT_RESET_CP |
3798 RADEON_SOFT_RESET_SE |
3799 RADEON_SOFT_RESET_RE |
3800 RADEON_SOFT_RESET_PP |
3801 RADEON_SOFT_RESET_E2 |
3802 RADEON_SOFT_RESET_RB);
3803 GET32(sc, RADEON_RBBM_SOFT_RESET);
3804 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm &
3805 ~(RADEON_SOFT_RESET_CP |
3806 RADEON_SOFT_RESET_SE |
3807 RADEON_SOFT_RESET_RE |
3808 RADEON_SOFT_RESET_PP |
3809 RADEON_SOFT_RESET_E2 |
3810 RADEON_SOFT_RESET_RB));
3811 GET32(sc, RADEON_RBBM_SOFT_RESET);
3812 }
3813
3814 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET);
3815 GET32(sc, RADEON_HOST_PATH_CNTL);
3816 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc);
3817
3818 if (!IS_R300(sc) && !IS_AVIVO(sc))
3819 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm);
3820
3821 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex);
3822 PRINTREG(RADEON_CLOCK_CNTL_INDEX);
3823 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl);
3824
3825 if (HAS_R300CG(sc))
3826 radeonfb_r300cg_workaround(sc);
3827 }
3828
3829 static int
radeonfb_set_curpos(struct radeonfb_display * dp,struct wsdisplay_curpos * pos)3830 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos)
3831 {
3832 int x, y;
3833
3834 x = pos->x;
3835 y = pos->y;
3836
3837 /*
3838 * This doesn't let a cursor move off the screen. I'm not
3839 * sure if this will have negative effects for e.g. Xinerama.
3840 * I'd guess Xinerama handles it by changing the cursor shape,
3841 * but that needs verification.
3842 */
3843 if (x >= dp->rd_virtx)
3844 x = dp->rd_virtx - 1;
3845 if (x < 0)
3846 x = 0;
3847 if (y >= dp->rd_virty)
3848 y = dp->rd_virty - 1;
3849 if (y < 0)
3850 y = 0;
3851
3852 dp->rd_cursor.rc_pos.x = x;
3853 dp->rd_cursor.rc_pos.y = y;
3854
3855 radeonfb_cursor_position(dp);
3856 return 0;
3857 }
3858
3859 static int
radeonfb_set_cursor(struct radeonfb_display * dp,struct wsdisplay_cursor * wc)3860 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc)
3861 {
3862 unsigned flags;
3863
3864 uint8_t r[2], g[2], b[2];
3865 unsigned index, count;
3866 int i, err;
3867 int pitch, size;
3868 struct radeonfb_cursor *nc = &dp->rd_tempcursor;
3869
3870 flags = wc->which;
3871
3872 /* copy old values */
3873 memcpy(nc, &dp->rd_cursor, sizeof(struct radeonfb_cursor));
3874
3875 if (flags & WSDISPLAY_CURSOR_DOCMAP) {
3876 index = wc->cmap.index;
3877 count = wc->cmap.count;
3878
3879 if (index >= 2 || count > 2 - index)
3880 return EINVAL;
3881
3882 err = copyin(wc->cmap.red, &r[index], count);
3883 if (err)
3884 return err;
3885 err = copyin(wc->cmap.green, &g[index], count);
3886 if (err)
3887 return err;
3888 err = copyin(wc->cmap.blue, &b[index], count);
3889 if (err)
3890 return err;
3891
3892 for (i = index; i < index + count; i++) {
3893 nc->rc_cmap[i] =
3894 (r[i] << 16) + (g[i] << 8) + (b[i] << 0);
3895 }
3896 }
3897
3898 if (flags & WSDISPLAY_CURSOR_DOSHAPE) {
3899 if ((wc->size.x > RADEON_CURSORMAXX) ||
3900 (wc->size.y > RADEON_CURSORMAXY))
3901 return EINVAL;
3902
3903 /* figure bytes per line */
3904 pitch = (wc->size.x + 7) / 8;
3905 size = pitch * wc->size.y;
3906
3907 /* clear the old cursor and mask */
3908 memset(nc->rc_image, 0, 512);
3909 memset(nc->rc_mask, 0, 512);
3910
3911 nc->rc_size = wc->size;
3912
3913 if ((err = copyin(wc->image, nc->rc_image, size)) != 0)
3914 return err;
3915
3916 if ((err = copyin(wc->mask, nc->rc_mask, size)) != 0)
3917 return err;
3918 }
3919
3920 if (flags & WSDISPLAY_CURSOR_DOHOT) {
3921 nc->rc_hot = wc->hot;
3922 if (nc->rc_hot.x >= nc->rc_size.x)
3923 nc->rc_hot.x = nc->rc_size.x - 1;
3924 if (nc->rc_hot.y >= nc->rc_size.y)
3925 nc->rc_hot.y = nc->rc_size.y - 1;
3926 }
3927
3928 if (flags & WSDISPLAY_CURSOR_DOPOS) {
3929 nc->rc_pos = wc->pos;
3930 if (nc->rc_pos.x >= dp->rd_virtx)
3931 nc->rc_pos.x = dp->rd_virtx - 1;
3932 #if 0
3933 if (nc->rc_pos.x < 0)
3934 nc->rc_pos.x = 0;
3935 #endif
3936 if (nc->rc_pos.y >= dp->rd_virty)
3937 nc->rc_pos.y = dp->rd_virty - 1;
3938 #if 0
3939 if (nc->rc_pos.y < 0)
3940 nc->rc_pos.y = 0;
3941 #endif
3942 }
3943 if (flags & WSDISPLAY_CURSOR_DOCUR) {
3944 nc->rc_visible = wc->enable;
3945 }
3946
3947 memcpy(&dp->rd_cursor, nc, sizeof(struct radeonfb_cursor));
3948 radeonfb_cursor_update(dp, wc->which);
3949
3950 return 0;
3951 }
3952
3953 static uint8_t
radeonfb_backwards(uint8_t d)3954 radeonfb_backwards(uint8_t d)
3955 {
3956 uint8_t l;
3957
3958 l = d << 7;
3959 l |= ((d & 0x02) << 5);
3960 l |= ((d & 0x04) << 3);
3961 l |= ((d & 0x08) << 1);
3962 l |= ((d & 0x10) >> 1);
3963 l |= ((d & 0x20) >> 3);
3964 l |= ((d & 0x40) >> 5);
3965 l |= ((d & 0x80) >> 7);
3966 return l;
3967 }
3968
3969 /*
3970 * Change the cursor shape. Call this with the cursor locked to avoid
3971 * flickering/tearing.
3972 */
3973 static void
radeonfb_cursor_shape(struct radeonfb_display * dp)3974 radeonfb_cursor_shape(struct radeonfb_display *dp)
3975 {
3976 uint8_t and[512], xor[512];
3977 int i, j, src, dst /* , pitch */;
3978 const uint8_t *msk = dp->rd_cursor.rc_mask;
3979 const uint8_t *img = dp->rd_cursor.rc_image;
3980
3981 /*
3982 * Radeon cursor data interleaves one line of AND data followed
3983 * by a line of XOR data. (Each line corresponds to a whole hardware
3984 * pitch - i.e. 64 pixels or 8 bytes.)
3985 *
3986 * The cursor is displayed using the following table:
3987 *
3988 * AND XOR Result
3989 * ----------------------
3990 * 0 0 Cursor color 0
3991 * 0 1 Cursor color 1
3992 * 1 0 Transparent
3993 * 1 1 Complement of background
3994 *
3995 * Our masks are therefore different from what we were passed.
3996 * Passed in, I'm assuming the data represents either color 0 or 1,
3997 * and a mask, so the passed in table looks like:
3998 *
3999 * IMG Mask Result
4000 * -----------------------
4001 * 0 0 Transparent
4002 * 0 1 Cursor color 0
4003 * 1 0 Transparent
4004 * 1 1 Cursor color 1
4005 *
4006 * IF mask bit == 1, AND = 0, XOR = color.
4007 * IF mask bit == 0, AND = 1, XOR = 0.
4008 *
4009 * hence: AND = ~(mask); XOR = color & ~(mask);
4010 */
4011
4012 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */
4013
4014 /* start by assuming all bits are transparent */
4015 memset(and, 0xff, 512);
4016 memset(xor, 0x00, 512);
4017
4018 src = 0;
4019 dst = 0;
4020 for (i = 0; i < 64; i++) {
4021 for (j = 0; j < 64; j += 8) {
4022 if ((i < dp->rd_cursor.rc_size.y) &&
4023 (j < dp->rd_cursor.rc_size.x)) {
4024
4025 /* take care to leave odd bits alone */
4026 and[dst] &= ~(msk[src]);
4027 xor[dst] = img[src] & msk[src];
4028 src++;
4029 }
4030 dst++;
4031 }
4032 }
4033
4034 for (i = 0; i < 512; i++) {
4035 and[i] = radeonfb_backwards(and[i]);
4036 xor[i] = radeonfb_backwards(xor[i]);
4037 }
4038
4039 /* copy the image into place */
4040 for (i = 0; i < 64; i++) {
4041 memcpy((uint8_t *)dp->rd_curptr + (i * 16),
4042 &and[i * 8], 8);
4043 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8,
4044 &xor[i * 8], 8);
4045 }
4046 }
4047
4048 /*
4049 * We use the cursor in 24bit mode on avivo, much simpler than the above.
4050 * Should probably do the same on older radeons
4051 */
4052 static void
radeonfb_avivo_cursor_shape(struct radeonfb_display * dp)4053 radeonfb_avivo_cursor_shape(struct radeonfb_display *dp)
4054 {
4055 const uint8_t *msk = dp->rd_cursor.rc_mask;
4056 const uint8_t *img = dp->rd_cursor.rc_image;
4057 uint32_t *out = (uint32_t *)dp->rd_curptr;
4058 uint8_t bit;
4059 int i, j, px;
4060
4061 for (i = 0; i < 64 * 8; i++) {
4062 bit = 0x01;
4063 for (j = 0; j < 8; j++) {
4064 px = ((*msk & bit) ? 2 : 0) | ((*img & bit) ? 1 : 0);
4065 switch (px) {
4066 case 0:
4067 case 1:
4068 *out = htole32(0x00000000);
4069 break;
4070 case 2:
4071 *out = htole32(0xff000000 |
4072 dp->rd_cursor.rc_cmap[0]);
4073 break;
4074 case 3:
4075 *out = htole32(0xff000000 |
4076 dp->rd_cursor.rc_cmap[1]);
4077 break;
4078 }
4079 out++;
4080 bit = bit << 1;
4081 }
4082 msk++;
4083 img++;
4084 }
4085 }
4086
4087 static void
radeonfb_cursor_position(struct radeonfb_display * dp)4088 radeonfb_cursor_position(struct radeonfb_display *dp)
4089 {
4090 struct radeonfb_softc *sc = dp->rd_softc;
4091 uint32_t offset, hvoff, hvpos; /* registers */
4092 uint32_t coff; /* cursor offset */
4093 int i, x, y, xoff, yoff, crtcoff, lock;
4094
4095 /*
4096 * XXX: this also needs to handle pan/scan
4097 */
4098 for (i = 0; i < dp->rd_ncrtcs; i++) {
4099
4100 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i];
4101
4102 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
4103 PUT32(sc, AVIVO_D1CUR_SIZE, 0x003f003f);
4104 if (IS_AVIVO(sc)) {
4105 if (rcp->rc_number) {
4106 offset = AVIVO_D2CUR_SURFACE_ADDRESS;
4107 hvoff = AVIVO_D2CUR_HOT_SPOT;
4108 hvpos = AVIVO_D2CUR_POSITION;
4109 crtcoff = 0/*RADEON_CRTC_OFFSET*/;
4110 } else {
4111 offset = AVIVO_D1CUR_SURFACE_ADDRESS;
4112 hvoff = AVIVO_D1CUR_HOT_SPOT;
4113 hvpos = AVIVO_D1CUR_POSITION;
4114 crtcoff = 0/*RADEON_CRTC_OFFSET*/;
4115 }
4116 lock = 0;
4117 } else {
4118 if (rcp->rc_number) {
4119 offset = RADEON_CUR2_OFFSET;
4120 hvoff = RADEON_CUR2_HORZ_VERT_OFF;
4121 hvpos = RADEON_CUR2_HORZ_VERT_POSN;
4122 crtcoff = RADEON_CRTC2_OFFSET;
4123 } else {
4124 offset = RADEON_CUR_OFFSET;
4125 hvoff = RADEON_CUR_HORZ_VERT_OFF;
4126 hvpos = RADEON_CUR_HORZ_VERT_POSN;
4127 crtcoff = RADEON_CRTC_OFFSET;
4128 }
4129 lock = RADEON_CUR_LOCK;
4130 }
4131
4132 x = dp->rd_cursor.rc_pos.x;
4133 y = dp->rd_cursor.rc_pos.y;
4134
4135 while (y < rcp->rc_yoffset) {
4136 rcp->rc_yoffset -= RADEON_PANINCREMENT;
4137 }
4138 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) {
4139 rcp->rc_yoffset += RADEON_PANINCREMENT;
4140 }
4141 while (x < rcp->rc_xoffset) {
4142 rcp->rc_xoffset -= RADEON_PANINCREMENT;
4143 }
4144 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) {
4145 rcp->rc_xoffset += RADEON_PANINCREMENT;
4146 }
4147
4148 /* adjust for the cursor's hotspot */
4149 x -= dp->rd_cursor.rc_hot.x;
4150 y -= dp->rd_cursor.rc_hot.y;
4151 xoff = yoff = 0;
4152
4153 if (x >= dp->rd_virtx)
4154 x = dp->rd_virtx - 1;
4155 if (y >= dp->rd_virty)
4156 y = dp->rd_virty - 1;
4157
4158 /* now adjust cursor so it is relative to viewport */
4159 x -= rcp->rc_xoffset;
4160 y -= rcp->rc_yoffset;
4161
4162 /*
4163 * no need to check for fall off, because we should
4164 * never move off the screen entirely!
4165 */
4166 coff = 0;
4167 if (x < 0) {
4168 xoff = -x;
4169 x = 0;
4170 }
4171 if (y < 0) {
4172 yoff = -y;
4173 y = 0;
4174 coff = (yoff * 2) * 8;
4175 }
4176
4177 /* pan the display */
4178 if (crtcoff != 0)
4179 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) +
4180 rcp->rc_xoffset);
4181
4182 PUT32(sc, offset, (dp->rd_curoff + coff) | lock);
4183 PUT32(sc, hvoff, (xoff << 16) | (yoff) | lock);
4184 /* NB: this unlocks the cursor */
4185 PUT32(sc, hvpos, (x << 16) | y);
4186 if (IS_AVIVO(sc))
4187 CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
4188 }
4189 }
4190
4191 static void
radeonfb_cursor_visible(struct radeonfb_display * dp)4192 radeonfb_cursor_visible(struct radeonfb_display *dp)
4193 {
4194 struct radeonfb_softc *sc = dp->rd_softc;
4195 int i;
4196 uint32_t gencntl, bit;
4197
4198 for (i = 0; i < dp->rd_ncrtcs; i++) {
4199 if (IS_AVIVO(sc)) {
4200 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
4201 if (dp->rd_crtcs[i].rc_number) {
4202 gencntl = AVIVO_D2CUR_CONTROL;
4203 bit = AVIVO_D1CURSOR_EN | (2 << 8);
4204 } else {
4205 gencntl = AVIVO_D1CUR_CONTROL;
4206 bit = AVIVO_D1CURSOR_EN | (2 << 8);
4207 }
4208 } else {
4209 if (dp->rd_crtcs[i].rc_number) {
4210 gencntl = RADEON_CRTC2_GEN_CNTL;
4211 bit = RADEON_CRTC2_CUR_EN;
4212 } else {
4213 gencntl = RADEON_CRTC_GEN_CNTL;
4214 bit = RADEON_CRTC_CUR_EN;
4215 }
4216 }
4217 if (dp->rd_cursor.rc_visible)
4218 SET32(dp->rd_softc, gencntl, bit);
4219 else
4220 CLR32(dp->rd_softc, gencntl, bit);
4221 if (IS_AVIVO(sc))
4222 CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
4223
4224 }
4225 }
4226
4227 static void
radeonfb_cursor_cmap(struct radeonfb_display * dp)4228 radeonfb_cursor_cmap(struct radeonfb_display *dp)
4229 {
4230 int i;
4231 uint32_t c0reg, c1reg;
4232 struct radeonfb_softc *sc = dp->rd_softc;
4233
4234 for (i = 0; i < dp->rd_ncrtcs; i++) {
4235 if (dp->rd_crtcs[i].rc_number) {
4236 c0reg = RADEON_CUR2_CLR0;
4237 c1reg = RADEON_CUR2_CLR1;
4238 } else {
4239 c0reg = RADEON_CUR_CLR0;
4240 c1reg = RADEON_CUR_CLR1;
4241 }
4242
4243 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]);
4244 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]);
4245 }
4246 }
4247
4248 static void
radeonfb_cursor_update(struct radeonfb_display * dp,unsigned which)4249 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which)
4250 {
4251 struct radeonfb_softc *sc;
4252 int i;
4253
4254 sc = dp->rd_softc;
4255
4256 for (i = 0; i < dp->rd_ncrtcs; i++) {
4257 if (dp->rd_crtcs[i].rc_number) {
4258 if (IS_AVIVO(sc)) {
4259 SET32(sc, AVIVO_D2CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
4260 } else
4261 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK);
4262 } else {
4263 if (IS_AVIVO(sc)) {
4264 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
4265 } else
4266 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK);
4267 }
4268 }
4269
4270 if (which & WSDISPLAY_CURSOR_DOCMAP) {
4271 if (IS_AVIVO(sc)) {
4272 /*
4273 * we use an ARGB cursor here, so we need to rebuild
4274 * the cursor image every time the palette changes
4275 */
4276 radeonfb_avivo_cursor_shape(dp);
4277 } else
4278 radeonfb_cursor_cmap(dp);
4279 }
4280
4281 if (which & WSDISPLAY_CURSOR_DOSHAPE) {
4282 if (IS_AVIVO(sc)) {
4283 radeonfb_avivo_cursor_shape(dp);
4284 } else
4285 radeonfb_cursor_shape(dp);
4286 }
4287
4288 if (which & WSDISPLAY_CURSOR_DOCUR)
4289 radeonfb_cursor_visible(dp);
4290
4291 /* this one is unconditional, because it updates other stuff */
4292 radeonfb_cursor_position(dp);
4293 }
4294
4295 static struct videomode *
radeonfb_best_refresh(struct videomode * m1,struct videomode * m2)4296 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2)
4297 {
4298 int r1, r2;
4299
4300 /* otherwise pick the higher refresh rate */
4301 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal);
4302 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal);
4303
4304 return (r1 < r2 ? m2 : m1);
4305 }
4306
4307 static const struct videomode *
radeonfb_port_mode(struct radeonfb_softc * sc,struct radeonfb_port * rp,int x,int y)4308 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp,
4309 int x, int y)
4310 {
4311 struct edid_info *ep = &rp->rp_edid;
4312 struct videomode *vmp = NULL;
4313 int i;
4314
4315 if (!rp->rp_edid_valid) {
4316 /* fallback to safe mode */
4317 return radeonfb_modelookup(sc->sc_defaultmode);
4318 }
4319
4320 /* always choose the preferred mode first! */
4321 if (ep->edid_preferred_mode) {
4322
4323 /* XXX: add auto-stretching support for native mode */
4324
4325 /* this may want panning to occur, btw */
4326 if ((ep->edid_preferred_mode->hdisplay <= x) &&
4327 (ep->edid_preferred_mode->vdisplay <= y))
4328 return ep->edid_preferred_mode;
4329 }
4330
4331 for (i = 0; i < ep->edid_nmodes; i++) {
4332 /*
4333 * We elect to pick a resolution that is too large for
4334 * the monitor than one that is too small. This means
4335 * that we will prefer to pan rather than to try to
4336 * center a smaller display on a larger screen. In
4337 * practice, this shouldn't matter because if a
4338 * monitor can support a larger resolution, it can
4339 * probably also support the smaller. A specific
4340 * exception is fixed format panels, but hopefully
4341 * they are properly dealt with by the "autostretch"
4342 * logic above.
4343 */
4344 if ((ep->edid_modes[i].hdisplay > x) ||
4345 (ep->edid_modes[i].vdisplay > y)) {
4346 continue;
4347 }
4348
4349 /*
4350 * at this point, the display mode is no larger than
4351 * what we've requested.
4352 */
4353 if (vmp == NULL)
4354 vmp = &ep->edid_modes[i];
4355
4356 /* eliminate smaller modes */
4357 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) ||
4358 (vmp->vdisplay >= ep->edid_modes[i].vdisplay))
4359 continue;
4360
4361 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) ||
4362 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) {
4363 vmp = &ep->edid_modes[i];
4364 continue;
4365 }
4366
4367 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay);
4368 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay);
4369
4370 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]);
4371 }
4372
4373 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode));
4374 }
4375
4376 static int
radeonfb_hasres(struct videomode * list,int nlist,int x,int y)4377 radeonfb_hasres(struct videomode *list, int nlist, int x, int y)
4378 {
4379 int i;
4380
4381 for (i = 0; i < nlist; i++) {
4382 if ((x == list[i].hdisplay) &&
4383 (y == list[i].vdisplay)) {
4384 return 1;
4385 }
4386 }
4387 return 0;
4388 }
4389
4390 static void
radeonfb_pickres(struct radeonfb_display * dp,uint16_t * x,uint16_t * y,int pan)4391 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y,
4392 int pan)
4393 {
4394 struct radeonfb_port *rp;
4395 struct edid_info *ep;
4396 int i, j;
4397
4398 *x = 0;
4399 *y = 0;
4400
4401 if (pan) {
4402 for (i = 0; i < dp->rd_ncrtcs; i++) {
4403 rp = dp->rd_crtcs[i].rc_port;
4404 ep = &rp->rp_edid;
4405 if (!rp->rp_edid_valid) {
4406 /* monitor not present */
4407 continue;
4408 }
4409
4410 /*
4411 * For now we are ignoring "conflict" that
4412 * could occur when mixing some modes like
4413 * 1280x1024 and 1400x800. It isn't clear
4414 * which is better, so the first one wins.
4415 */
4416 for (j = 0; j < ep->edid_nmodes; j++) {
4417 /*
4418 * ignore resolutions that are too big for
4419 * the radeon
4420 */
4421 if (ep->edid_modes[j].hdisplay >
4422 dp->rd_softc->sc_maxx)
4423 continue;
4424 if (ep->edid_modes[j].vdisplay >
4425 dp->rd_softc->sc_maxy)
4426 continue;
4427
4428 /*
4429 * pick largest resolution, the
4430 * smaller monitor will pan
4431 */
4432 if ((ep->edid_modes[j].hdisplay >= *x) &&
4433 (ep->edid_modes[j].vdisplay >= *y)) {
4434 *x = ep->edid_modes[j].hdisplay;
4435 *y = ep->edid_modes[j].vdisplay;
4436 }
4437 }
4438 }
4439
4440 } else {
4441 struct videomode *modes;
4442 size_t smodes;
4443 int nmodes = 0;
4444 int valid = 0;
4445
4446 smodes = sizeof(struct videomode) * 64;
4447 modes = kmem_alloc(smodes, KM_SLEEP);
4448
4449 for (i = 0; i < dp->rd_ncrtcs; i++) {
4450 /*
4451 * pick the largest resolution in common.
4452 */
4453 rp = dp->rd_crtcs[i].rc_port;
4454 ep = &rp->rp_edid;
4455
4456 if (!rp->rp_edid_valid)
4457 continue;
4458
4459 if (!valid) {
4460 /*
4461 * Pick the preferred mode for this port
4462 * if available.
4463 */
4464 if (ep->edid_preferred_mode) {
4465 struct videomode *vmp =
4466 ep->edid_preferred_mode;
4467
4468 if ((vmp->hdisplay <=
4469 dp->rd_softc->sc_maxx) &&
4470 (vmp->vdisplay <=
4471 dp->rd_softc->sc_maxy))
4472 modes[nmodes++] = *vmp;
4473 } else {
4474
4475 /* initialize starting list */
4476 for (j = 0; j < ep->edid_nmodes; j++) {
4477 /*
4478 * ignore resolutions that are
4479 * too big for the radeon
4480 */
4481 if (ep->edid_modes[j].hdisplay >
4482 dp->rd_softc->sc_maxx)
4483 continue;
4484 if (ep->edid_modes[j].vdisplay >
4485 dp->rd_softc->sc_maxy)
4486 continue;
4487
4488 modes[nmodes] =
4489 ep->edid_modes[j];
4490 nmodes++;
4491 }
4492 }
4493 valid = 1;
4494 } else {
4495 /* merge into preexisting list */
4496 for (j = 0; j < nmodes; j++) {
4497 if (!radeonfb_hasres(ep->edid_modes,
4498 ep->edid_nmodes,
4499 modes[j].hdisplay,
4500 modes[j].vdisplay)) {
4501 modes[j] = modes[nmodes];
4502 j--;
4503 nmodes--;
4504 }
4505 }
4506 }
4507 }
4508
4509 /* now we have to pick from the merged list */
4510 for (i = 0; i < nmodes; i++) {
4511 if ((modes[i].hdisplay >= *x) &&
4512 (modes[i].vdisplay >= *y)) {
4513 *x = modes[i].hdisplay;
4514 *y = modes[i].vdisplay;
4515 }
4516 }
4517 kmem_free(modes, smodes);
4518
4519 }
4520
4521 if ((*x == 0) || (*y == 0)) {
4522 /* fallback to safe mode */
4523 *x = 640;
4524 *y = 480;
4525 }
4526 }
4527
4528 /*
4529 * backlight levels are linear on:
4530 * - RV200, RV250, RV280, RV350
4531 * - but NOT on PowerBook4,3 6,3 6,5
4532 * according to Linux' radeonfb
4533 */
4534
4535 /* Get the current backlight level for the display. */
4536
4537 static int
radeonfb_get_backlight(struct radeonfb_display * dp)4538 radeonfb_get_backlight(struct radeonfb_display *dp)
4539 {
4540 int s;
4541 uint32_t level;
4542
4543 s = spltty();
4544
4545 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL);
4546 level &= RADEON_LVDS_BL_MOD_LEV_MASK;
4547 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT;
4548
4549 /*
4550 * On some chips, we should negate the backlight level.
4551 * XXX Find out on which chips.
4552 */
4553 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT)
4554 level = RADEONFB_BACKLIGHT_MAX - level;
4555
4556 splx(s);
4557
4558 return level;
4559 }
4560
4561 /* Set the backlight to the given level for the display. */
4562 static void
radeonfb_switch_backlight(struct radeonfb_display * dp,int on)4563 radeonfb_switch_backlight(struct radeonfb_display *dp, int on)
4564 {
4565 if (dp->rd_bl_on == on)
4566 return;
4567 dp->rd_bl_on = on;
4568 radeonfb_set_backlight(dp, dp->rd_bl_level);
4569 }
4570
4571 static int
radeonfb_set_backlight(struct radeonfb_display * dp,int level)4572 radeonfb_set_backlight(struct radeonfb_display *dp, int level)
4573 {
4574 struct radeonfb_softc *sc = dp->rd_softc;
4575 int rlevel, s;
4576 uint32_t lvds;
4577
4578 if(!sc->sc_mapped)
4579 return 0;
4580
4581 s = spltty();
4582
4583 dp->rd_bl_level = level;
4584 if (dp->rd_bl_on == 0)
4585 level = 0;
4586
4587 if (level < 0)
4588 level = 0;
4589 else if (level >= RADEONFB_BACKLIGHT_MAX)
4590 level = RADEONFB_BACKLIGHT_MAX;
4591
4592 /* On some chips, we should negate the backlight level. */
4593 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) {
4594 rlevel = RADEONFB_BACKLIGHT_MAX - level;
4595 } else
4596 rlevel = level;
4597
4598 callout_stop(&dp->rd_bl_lvds_co);
4599 //radeonfb_engine_idle(sc);
4600
4601 /*
4602 * Turn off the display if the backlight is set to 0, since the
4603 * display is useless without backlight anyway.
4604 */
4605 if (level == 0)
4606 radeonfb_blank(dp, 1);
4607 else if (radeonfb_get_backlight(dp) == 0)
4608 radeonfb_blank(dp, 0);
4609
4610 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL);
4611 lvds &= ~RADEON_LVDS_DISPLAY_DIS;
4612 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) {
4613 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON;
4614 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN;
4615 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds);
4616 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK;
4617 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT;
4618 lvds |= RADEON_LVDS_ON;
4619 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN;
4620 } else {
4621 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK;
4622 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT;
4623 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds);
4624 }
4625
4626 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK;
4627 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK;
4628 /* XXX What is the correct delay? */
4629 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz);
4630
4631 splx(s);
4632
4633 return 0;
4634 }
4635
4636 /*
4637 * Callout function for delayed operations on the LVDS_GEN_CNTL register.
4638 * Set the delayed bits in the register, and clear the stored delayed
4639 * value.
4640 */
4641
radeonfb_lvds_callout(void * arg)4642 static void radeonfb_lvds_callout(void *arg)
4643 {
4644 struct radeonfb_display *dp = arg;
4645 int s;
4646
4647 s = splhigh();
4648
4649 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0,
4650 dp->rd_bl_lvds_val);
4651 dp->rd_bl_lvds_val = 0;
4652
4653 splx(s);
4654 }
4655
4656 static void
radeonfb_brightness_up(device_t dev)4657 radeonfb_brightness_up(device_t dev)
4658 {
4659 struct radeonfb_softc *sc = device_private(dev);
4660 struct radeonfb_display *dp = &sc->sc_displays[0];
4661 int level;
4662
4663 /* we assume the main display is the first one - need a better way */
4664 if (sc->sc_ndisplays < 1) return;
4665 /* make sure pushing the hotkeys always has an effect */
4666 dp->rd_bl_on = 1;
4667 level = dp->rd_bl_level;
4668 level = uimin(RADEONFB_BACKLIGHT_MAX, level + 5);
4669 radeonfb_set_backlight(dp, level);
4670 }
4671
4672 static void
radeonfb_brightness_down(device_t dev)4673 radeonfb_brightness_down(device_t dev)
4674 {
4675 struct radeonfb_softc *sc = device_private(dev);
4676 struct radeonfb_display *dp = &sc->sc_displays[0];
4677 int level;
4678
4679 /* we assume the main display is the first one - need a better way */
4680 if (sc->sc_ndisplays < 1) return;
4681 /* make sure pushing the hotkeys always has an effect */
4682 dp->rd_bl_on = 1;
4683 level = dp->rd_bl_level;
4684 level = uimax(0, level - 5);
4685 radeonfb_set_backlight(dp, level);
4686 }
4687