xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/kfd_topology.h (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: kfd_topology.h,v 1.3 2021/12/18 23:44:59 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2014 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef __KFD_TOPOLOGY_H__
26 #define __KFD_TOPOLOGY_H__
27 
28 #include <linux/types.h>
29 #include <linux/list.h>
30 #include "kfd_crat.h"
31 
32 #define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32
33 
34 #define HSA_CAP_HOT_PLUGGABLE			0x00000001
35 #define HSA_CAP_ATS_PRESENT			0x00000002
36 #define HSA_CAP_SHARED_WITH_GRAPHICS		0x00000004
37 #define HSA_CAP_QUEUE_SIZE_POW2			0x00000008
38 #define HSA_CAP_QUEUE_SIZE_32BIT		0x00000010
39 #define HSA_CAP_QUEUE_IDLE_EVENT		0x00000020
40 #define HSA_CAP_VA_LIMIT			0x00000040
41 #define HSA_CAP_WATCH_POINTS_SUPPORTED		0x00000080
42 #define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK	0x00000f00
43 #define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT	8
44 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK	0x00003000
45 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT	12
46 #define HSA_CAP_RESERVED			0xffffc000
47 
48 #define HSA_CAP_DOORBELL_TYPE_PRE_1_0		0x0
49 #define HSA_CAP_DOORBELL_TYPE_1_0		0x1
50 #define HSA_CAP_DOORBELL_TYPE_2_0		0x2
51 #define HSA_CAP_AQL_QUEUE_DOUBLE_MAP		0x00004000
52 
53 #define HSA_CAP_SRAM_EDCSUPPORTED		0x00080000
54 #define HSA_CAP_MEM_EDCSUPPORTED		0x00100000
55 #define HSA_CAP_RASEVENTNOTIFY			0x00200000
56 
57 struct kfd_node_properties {
58 	uint64_t hive_id;
59 	uint32_t cpu_cores_count;
60 	uint32_t simd_count;
61 	uint32_t mem_banks_count;
62 	uint32_t caches_count;
63 	uint32_t io_links_count;
64 	uint32_t cpu_core_id_base;
65 	uint32_t simd_id_base;
66 	uint32_t capability;
67 	uint32_t max_waves_per_simd;
68 	uint32_t lds_size_in_kb;
69 	uint32_t gds_size_in_kb;
70 	uint32_t num_gws;
71 	uint32_t wave_front_size;
72 	uint32_t array_count;
73 	uint32_t simd_arrays_per_engine;
74 	uint32_t cu_per_simd_array;
75 	uint32_t simd_per_cu;
76 	uint32_t max_slots_scratch_cu;
77 	uint32_t engine_id;
78 	uint32_t vendor_id;
79 	uint32_t device_id;
80 	uint32_t location_id;
81 	uint32_t max_engine_clk_fcompute;
82 	uint32_t max_engine_clk_ccompute;
83 	int32_t  drm_render_minor;
84 	uint32_t num_sdma_engines;
85 	uint32_t num_sdma_xgmi_engines;
86 	uint32_t num_sdma_queues_per_engine;
87 	uint32_t num_cp_queues;
88 	char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
89 };
90 
91 #define HSA_MEM_HEAP_TYPE_SYSTEM	0
92 #define HSA_MEM_HEAP_TYPE_FB_PUBLIC	1
93 #define HSA_MEM_HEAP_TYPE_FB_PRIVATE	2
94 #define HSA_MEM_HEAP_TYPE_GPU_GDS	3
95 #define HSA_MEM_HEAP_TYPE_GPU_LDS	4
96 #define HSA_MEM_HEAP_TYPE_GPU_SCRATCH	5
97 
98 #define HSA_MEM_FLAGS_HOT_PLUGGABLE	0x00000001
99 #define HSA_MEM_FLAGS_NON_VOLATILE	0x00000002
100 #define HSA_MEM_FLAGS_RESERVED		0xfffffffc
101 
102 struct kfd_mem_properties {
103 	struct list_head	list;
104 	uint32_t		heap_type;
105 	uint64_t		size_in_bytes;
106 	uint32_t		flags;
107 	uint32_t		width;
108 	uint32_t		mem_clk_max;
109 	struct kfd_dev		*gpu;
110 	struct kobject		*kobj;
111 	struct attribute	attr;
112 };
113 
114 #define HSA_CACHE_TYPE_DATA		0x00000001
115 #define HSA_CACHE_TYPE_INSTRUCTION	0x00000002
116 #define HSA_CACHE_TYPE_CPU		0x00000004
117 #define HSA_CACHE_TYPE_HSACU		0x00000008
118 #define HSA_CACHE_TYPE_RESERVED		0xfffffff0
119 
120 struct kfd_cache_properties {
121 	struct list_head	list;
122 	uint32_t		processor_id_low;
123 	uint32_t		cache_level;
124 	uint32_t		cache_size;
125 	uint32_t		cacheline_size;
126 	uint32_t		cachelines_per_tag;
127 	uint32_t		cache_assoc;
128 	uint32_t		cache_latency;
129 	uint32_t		cache_type;
130 	uint8_t			sibling_map[CRAT_SIBLINGMAP_SIZE];
131 	struct kfd_dev		*gpu;
132 	struct kobject		*kobj;
133 	struct attribute	attr;
134 };
135 
136 struct kfd_iolink_properties {
137 	struct list_head	list;
138 	uint32_t		iolink_type;
139 	uint32_t		ver_maj;
140 	uint32_t		ver_min;
141 	uint32_t		node_from;
142 	uint32_t		node_to;
143 	uint32_t		weight;
144 	uint32_t		min_latency;
145 	uint32_t		max_latency;
146 	uint32_t		min_bandwidth;
147 	uint32_t		max_bandwidth;
148 	uint32_t		rec_transfer_size;
149 	uint32_t		flags;
150 	struct kfd_dev		*gpu;
151 	struct kobject		*kobj;
152 	struct attribute	attr;
153 };
154 
155 struct kfd_perf_properties {
156 	struct list_head	list;
157 	char			block_name[16];
158 	uint32_t		max_concurrent;
159 	struct attribute_group	*attr_group;
160 };
161 
162 struct kfd_topology_device {
163 	struct list_head		list;
164 	uint32_t			gpu_id;
165 	uint32_t			proximity_domain;
166 	struct kfd_node_properties	node_props;
167 	struct list_head		mem_props;
168 	uint32_t			cache_count;
169 	struct list_head		cache_props;
170 	uint32_t			io_link_count;
171 	struct list_head		io_link_props;
172 	struct list_head		perf_props;
173 	struct kfd_dev			*gpu;
174 	struct kobject			*kobj_node;
175 	struct kobject			*kobj_mem;
176 	struct kobject			*kobj_cache;
177 	struct kobject			*kobj_iolink;
178 	struct kobject			*kobj_perf;
179 	struct attribute		attr_gpuid;
180 	struct attribute		attr_name;
181 	struct attribute		attr_props;
182 	uint8_t				oem_id[CRAT_OEMID_LENGTH];
183 	uint8_t				oem_table_id[CRAT_OEMTABLEID_LENGTH];
184 	uint32_t			oem_revision;
185 };
186 
187 struct kfd_system_properties {
188 	uint32_t		num_devices;     /* Number of H-NUMA nodes */
189 	uint32_t		generation_count;
190 	uint64_t		platform_oem;
191 	uint64_t		platform_id;
192 	uint64_t		platform_rev;
193 	struct kobject		*kobj_topology;
194 	struct kobject		*kobj_nodes;
195 	struct attribute	attr_genid;
196 	struct attribute	attr_props;
197 };
198 
199 struct kfd_topology_device *kfd_create_topology_device(
200 		struct list_head *device_list);
201 void kfd_release_topology_device_list(struct list_head *device_list);
202 
203 #endif /* __KFD_TOPOLOGY_H__ */
204