1 /* $NetBSD: intel_renderstate.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */
2
3 /*
4 * Copyright © 2014 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 *
25 * Authors:
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: intel_renderstate.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $");
32
33 #include "i915_drv.h"
34 #include "intel_renderstate.h"
35 #include "intel_ring.h"
36
37 #include <linux/nbsd-namespace.h>
38
39 static const struct intel_renderstate_rodata *
render_state_get_rodata(const struct intel_engine_cs * engine)40 render_state_get_rodata(const struct intel_engine_cs *engine)
41 {
42 if (engine->class != RENDER_CLASS)
43 return NULL;
44
45 switch (INTEL_GEN(engine->i915)) {
46 case 6:
47 return &gen6_null_state;
48 case 7:
49 return &gen7_null_state;
50 case 8:
51 return &gen8_null_state;
52 case 9:
53 return &gen9_null_state;
54 }
55
56 return NULL;
57 }
58
59 /*
60 * Macro to add commands to auxiliary batch.
61 * This macro only checks for page overflow before inserting the commands,
62 * this is sufficient as the null state generator makes the final batch
63 * with two passes to build command and state separately. At this point
64 * the size of both are known and it compacts them by relocating the state
65 * right after the commands taking care of alignment so we should sufficient
66 * space below them for adding new commands.
67 */
68 #define OUT_BATCH(batch, i, val) \
69 do { \
70 if ((i) >= PAGE_SIZE / sizeof(u32)) \
71 goto err; \
72 (batch)[(i)++] = (val); \
73 } while(0)
74
render_state_setup(struct intel_renderstate * so,struct drm_i915_private * i915)75 static int render_state_setup(struct intel_renderstate *so,
76 struct drm_i915_private *i915)
77 {
78 const struct intel_renderstate_rodata *rodata = so->rodata;
79 unsigned int i = 0, reloc_index = 0;
80 unsigned int needs_clflush;
81 u32 *d;
82 int ret;
83
84 ret = i915_gem_object_prepare_write(so->vma->obj, &needs_clflush);
85 if (ret)
86 return ret;
87
88 d = kmap_atomic(i915_gem_object_get_dirty_page(so->vma->obj, 0));
89
90 while (i < rodata->batch_items) {
91 u32 s = rodata->batch[i];
92
93 if (i * 4 == rodata->reloc[reloc_index]) {
94 u64 r = s + so->vma->node.start;
95 s = lower_32_bits(r);
96 if (HAS_64BIT_RELOC(i915)) {
97 if (i + 1 >= rodata->batch_items ||
98 rodata->batch[i + 1] != 0)
99 goto err;
100
101 d[i++] = s;
102 s = upper_32_bits(r);
103 }
104
105 reloc_index++;
106 }
107
108 d[i++] = s;
109 }
110
111 if (rodata->reloc[reloc_index] != -1) {
112 DRM_ERROR("only %d relocs resolved\n", reloc_index);
113 goto err;
114 }
115
116 so->batch_offset = i915_ggtt_offset(so->vma);
117 so->batch_size = rodata->batch_items * sizeof(u32);
118
119 while (i % CACHELINE_DWORDS)
120 OUT_BATCH(d, i, MI_NOOP);
121
122 so->aux_offset = i * sizeof(u32);
123
124 if (HAS_POOLED_EU(i915)) {
125 /*
126 * We always program 3x6 pool config but depending upon which
127 * subslice is disabled HW drops down to appropriate config
128 * shown below.
129 *
130 * In the below table 2x6 config always refers to
131 * fused-down version, native 2x6 is not available and can
132 * be ignored
133 *
134 * SNo subslices config eu pool configuration
135 * -----------------------------------------------------------
136 * 1 3 subslices enabled (3x6) - 0x00777000 (9+9)
137 * 2 ss0 disabled (2x6) - 0x00777000 (3+9)
138 * 3 ss1 disabled (2x6) - 0x00770000 (6+6)
139 * 4 ss2 disabled (2x6) - 0x00007000 (9+3)
140 */
141 u32 eu_pool_config = 0x00777000;
142
143 OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
144 OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
145 OUT_BATCH(d, i, eu_pool_config);
146 OUT_BATCH(d, i, 0);
147 OUT_BATCH(d, i, 0);
148 OUT_BATCH(d, i, 0);
149 }
150
151 OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
152 so->aux_size = i * sizeof(u32) - so->aux_offset;
153 so->aux_offset += so->batch_offset;
154 /*
155 * Since we are sending length, we need to strictly conform to
156 * all requirements. For Gen2 this must be a multiple of 8.
157 */
158 so->aux_size = ALIGN(so->aux_size, 8);
159
160 if (needs_clflush)
161 drm_clflush_virt_range(d, i * sizeof(u32));
162 kunmap_atomic(d);
163
164 ret = 0;
165 out:
166 i915_gem_object_finish_access(so->vma->obj);
167 return ret;
168
169 err:
170 kunmap_atomic(d);
171 ret = -EINVAL;
172 goto out;
173 }
174
175 #undef OUT_BATCH
176
intel_renderstate_init(struct intel_renderstate * so,struct intel_engine_cs * engine)177 int intel_renderstate_init(struct intel_renderstate *so,
178 struct intel_engine_cs *engine)
179 {
180 struct drm_i915_gem_object *obj;
181 int err;
182
183 memset(so, 0, sizeof(*so));
184
185 so->rodata = render_state_get_rodata(engine);
186 if (!so->rodata)
187 return 0;
188
189 if (so->rodata->batch_items * 4 > PAGE_SIZE)
190 return -EINVAL;
191
192 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
193 if (IS_ERR(obj))
194 return PTR_ERR(obj);
195
196 so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
197 if (IS_ERR(so->vma)) {
198 err = PTR_ERR(so->vma);
199 goto err_obj;
200 }
201
202 err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
203 if (err)
204 goto err_vma;
205
206 err = render_state_setup(so, engine->i915);
207 if (err)
208 goto err_unpin;
209
210 return 0;
211
212 err_unpin:
213 i915_vma_unpin(so->vma);
214 err_vma:
215 i915_vma_close(so->vma);
216 err_obj:
217 i915_gem_object_put(obj);
218 so->vma = NULL;
219 return err;
220 }
221
intel_renderstate_emit(struct intel_renderstate * so,struct i915_request * rq)222 int intel_renderstate_emit(struct intel_renderstate *so,
223 struct i915_request *rq)
224 {
225 struct intel_engine_cs *engine = rq->engine;
226 int err;
227
228 if (!so->vma)
229 return 0;
230
231 err = engine->emit_bb_start(rq,
232 so->batch_offset, so->batch_size,
233 I915_DISPATCH_SECURE);
234 if (err)
235 return err;
236
237 if (so->aux_size > 8) {
238 err = engine->emit_bb_start(rq,
239 so->aux_offset, so->aux_size,
240 I915_DISPATCH_SECURE);
241 if (err)
242 return err;
243 }
244
245 i915_vma_lock(so->vma);
246 err = i915_request_await_object(rq, so->vma->obj, false);
247 if (err == 0)
248 err = i915_vma_move_to_active(so->vma, rq, 0);
249 i915_vma_unlock(so->vma);
250
251 return err;
252 }
253
intel_renderstate_fini(struct intel_renderstate * so)254 void intel_renderstate_fini(struct intel_renderstate *so)
255 {
256 i915_vma_unpin_and_release(&so->vma, 0);
257 }
258