1 /* $NetBSD: intel_dp.c,v 1.7 2021/12/19 12:41:54 riastradh Exp $ */
2
3 /*
4 * Copyright © 2008 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 *
25 * Authors:
26 * Keith Packard <keithp@keithp.com>
27 *
28 */
29
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: intel_dp.c,v 1.7 2021/12/19 12:41:54 riastradh Exp $");
32
33 #include <linux/export.h>
34 #include <linux/i2c.h>
35 #include <linux/notifier.h>
36 #include <linux/reboot.h>
37 #include <linux/slab.h>
38 #include <linux/types.h>
39
40 #include <asm/byteorder.h>
41
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_crtc.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_edid.h>
46 #include <drm/drm_hdcp.h>
47 #include <drm/drm_probe_helper.h>
48 #include <drm/i915_drm.h>
49
50 #include "i915_debugfs.h"
51 #include "i915_drv.h"
52 #include "i915_trace.h"
53 #include "intel_atomic.h"
54 #include "intel_audio.h"
55 #include "intel_connector.h"
56 #include "intel_ddi.h"
57 #include "intel_display_types.h"
58 #include "intel_dp.h"
59 #include "intel_dp_link_training.h"
60 #include "intel_dp_mst.h"
61 #include "intel_dpio_phy.h"
62 #include "intel_fifo_underrun.h"
63 #include "intel_hdcp.h"
64 #include "intel_hdmi.h"
65 #include "intel_hotplug.h"
66 #include "intel_lspcon.h"
67 #include "intel_lvds.h"
68 #include "intel_panel.h"
69 #include "intel_psr.h"
70 #include "intel_sideband.h"
71 #include "intel_tc.h"
72 #include "intel_vdsc.h"
73
74 #define DP_DPRX_ESI_LEN 14
75
76 /* DP DSC throughput values used for slice count calculations KPixels/s */
77 #define DP_DSC_PEAK_PIXEL_RATE 2720000
78 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
79 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
80
81 /* DP DSC FEC Overhead factor = 1/(0.972261) */
82 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
83
84 /* Compliance test status bits */
85 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
86 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
87 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
88 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
89
90 struct dp_link_dpll {
91 int clock;
92 struct dpll dpll;
93 };
94
95 static const struct dp_link_dpll g4x_dpll[] = {
96 { 162000,
97 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
98 { 270000,
99 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
100 };
101
102 static const struct dp_link_dpll pch_dpll[] = {
103 { 162000,
104 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
105 { 270000,
106 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
107 };
108
109 static const struct dp_link_dpll vlv_dpll[] = {
110 { 162000,
111 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
112 { 270000,
113 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
114 };
115
116 /*
117 * CHV supports eDP 1.4 that have more link rates.
118 * Below only provides the fixed rate but exclude variable rate.
119 */
120 static const struct dp_link_dpll chv_dpll[] = {
121 /*
122 * CHV requires to program fractional division for m2.
123 * m2 is stored in fixed point format using formula below
124 * (m2_int << 22) | m2_fraction
125 */
126 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
127 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
128 { 270000, /* m2_int = 27, m2_fraction = 0 */
129 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
130 };
131
132 /* Constants for DP DSC configurations */
133 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
134
135 /* With Single pipe configuration, HW is capable of supporting maximum
136 * of 4 slices per line.
137 */
138 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
139
140 /**
141 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
142 * @intel_dp: DP struct
143 *
144 * If a CPU or PCH DP output is attached to an eDP panel, this function
145 * will return true, and false otherwise.
146 */
intel_dp_is_edp(struct intel_dp * intel_dp)147 bool intel_dp_is_edp(struct intel_dp *intel_dp)
148 {
149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
150
151 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
152 }
153
intel_attached_dp(struct intel_connector * connector)154 static struct intel_dp *intel_attached_dp(struct intel_connector *connector)
155 {
156 return enc_to_intel_dp(intel_attached_encoder(connector));
157 }
158
159 static void intel_dp_link_down(struct intel_encoder *encoder,
160 const struct intel_crtc_state *old_crtc_state);
161 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
162 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
163 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
164 const struct intel_crtc_state *crtc_state);
165 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
166 enum pipe pipe);
167 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
168
169 /* update sink rates from dpcd */
intel_dp_set_sink_rates(struct intel_dp * intel_dp)170 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
171 {
172 static const int dp_rates[] = {
173 162000, 270000, 540000, 810000
174 };
175 int i, max_rate;
176
177 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
178
179 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
180 if (dp_rates[i] > max_rate)
181 break;
182 intel_dp->sink_rates[i] = dp_rates[i];
183 }
184
185 intel_dp->num_sink_rates = i;
186 }
187
188 /* Get length of rates array potentially limited by max_rate. */
intel_dp_rate_limit_len(const int * rates,int len,int max_rate)189 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
190 {
191 int i;
192
193 /* Limit results by potentially reduced max rate */
194 for (i = 0; i < len; i++) {
195 if (rates[len - i - 1] <= max_rate)
196 return len - i;
197 }
198
199 return 0;
200 }
201
202 /* Get length of common rates array potentially limited by max_rate. */
intel_dp_common_len_rate_limit(const struct intel_dp * intel_dp,int max_rate)203 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
204 int max_rate)
205 {
206 return intel_dp_rate_limit_len(intel_dp->common_rates,
207 intel_dp->num_common_rates, max_rate);
208 }
209
210 /* Theoretical max between source and sink */
intel_dp_max_common_rate(struct intel_dp * intel_dp)211 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
212 {
213 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
214 }
215
216 /* Theoretical max between source and sink */
intel_dp_max_common_lane_count(struct intel_dp * intel_dp)217 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
218 {
219 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
220 int source_max = intel_dig_port->max_lanes;
221 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
222 int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
223
224 return min3(source_max, sink_max, fia_max);
225 }
226
intel_dp_max_lane_count(struct intel_dp * intel_dp)227 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
228 {
229 return intel_dp->max_link_lane_count;
230 }
231
232 int
intel_dp_link_required(int pixel_clock,int bpp)233 intel_dp_link_required(int pixel_clock, int bpp)
234 {
235 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
236 return DIV_ROUND_UP(pixel_clock * bpp, 8);
237 }
238
239 int
intel_dp_max_data_rate(int max_link_clock,int max_lanes)240 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
241 {
242 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
243 * link rate that is generally expressed in Gbps. Since, 8 bits of data
244 * is transmitted every LS_Clk per lane, there is no need to account for
245 * the channel encoding that is done in the PHY layer here.
246 */
247
248 return max_link_clock * max_lanes;
249 }
250
251 static int
intel_dp_downstream_max_dotclock(struct intel_dp * intel_dp)252 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
253 {
254 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
255 struct intel_encoder *encoder = &intel_dig_port->base;
256 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
257 int max_dotclk = dev_priv->max_dotclk_freq;
258 int ds_max_dotclk;
259
260 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
261
262 if (type != DP_DS_PORT_TYPE_VGA)
263 return max_dotclk;
264
265 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
266 intel_dp->downstream_ports);
267
268 if (ds_max_dotclk != 0)
269 max_dotclk = min(max_dotclk, ds_max_dotclk);
270
271 return max_dotclk;
272 }
273
cnl_max_source_rate(struct intel_dp * intel_dp)274 static int cnl_max_source_rate(struct intel_dp *intel_dp)
275 {
276 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
277 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
278 enum port port = dig_port->base.port;
279
280 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
281
282 /* Low voltage SKUs are limited to max of 5.4G */
283 if (voltage == VOLTAGE_INFO_0_85V)
284 return 540000;
285
286 /* For this SKU 8.1G is supported in all ports */
287 if (IS_CNL_WITH_PORT_F(dev_priv))
288 return 810000;
289
290 /* For other SKUs, max rate on ports A and D is 5.4G */
291 if (port == PORT_A || port == PORT_D)
292 return 540000;
293
294 return 810000;
295 }
296
icl_max_source_rate(struct intel_dp * intel_dp)297 static int icl_max_source_rate(struct intel_dp *intel_dp)
298 {
299 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
300 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
301 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
302
303 if (intel_phy_is_combo(dev_priv, phy) &&
304 !IS_ELKHARTLAKE(dev_priv) &&
305 !intel_dp_is_edp(intel_dp))
306 return 540000;
307
308 return 810000;
309 }
310
311 static void
intel_dp_set_source_rates(struct intel_dp * intel_dp)312 intel_dp_set_source_rates(struct intel_dp *intel_dp)
313 {
314 /* The values must be in increasing order */
315 static const int cnl_rates[] = {
316 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
317 };
318 static const int bxt_rates[] = {
319 162000, 216000, 243000, 270000, 324000, 432000, 540000
320 };
321 static const int skl_rates[] = {
322 162000, 216000, 270000, 324000, 432000, 540000
323 };
324 static const int hsw_rates[] = {
325 162000, 270000, 540000
326 };
327 static const int g4x_rates[] = {
328 162000, 270000
329 };
330 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
331 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
332 const struct ddi_vbt_port_info *info =
333 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
334 const int *source_rates;
335 int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
336
337 /* This should only be done once */
338 WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
339
340 if (INTEL_GEN(dev_priv) >= 10) {
341 source_rates = cnl_rates;
342 size = ARRAY_SIZE(cnl_rates);
343 if (IS_GEN(dev_priv, 10))
344 max_rate = cnl_max_source_rate(intel_dp);
345 else
346 max_rate = icl_max_source_rate(intel_dp);
347 } else if (IS_GEN9_LP(dev_priv)) {
348 source_rates = bxt_rates;
349 size = ARRAY_SIZE(bxt_rates);
350 } else if (IS_GEN9_BC(dev_priv)) {
351 source_rates = skl_rates;
352 size = ARRAY_SIZE(skl_rates);
353 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
354 IS_BROADWELL(dev_priv)) {
355 source_rates = hsw_rates;
356 size = ARRAY_SIZE(hsw_rates);
357 } else {
358 source_rates = g4x_rates;
359 size = ARRAY_SIZE(g4x_rates);
360 }
361
362 if (max_rate && vbt_max_rate)
363 max_rate = min(max_rate, vbt_max_rate);
364 else if (vbt_max_rate)
365 max_rate = vbt_max_rate;
366
367 if (max_rate)
368 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
369
370 intel_dp->source_rates = source_rates;
371 intel_dp->num_source_rates = size;
372 }
373
intersect_rates(const int * source_rates,int source_len,const int * sink_rates,int sink_len,int * common_rates)374 static int intersect_rates(const int *source_rates, int source_len,
375 const int *sink_rates, int sink_len,
376 int *common_rates)
377 {
378 int i = 0, j = 0, k = 0;
379
380 while (i < source_len && j < sink_len) {
381 if (source_rates[i] == sink_rates[j]) {
382 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
383 return k;
384 common_rates[k] = source_rates[i];
385 ++k;
386 ++i;
387 ++j;
388 } else if (source_rates[i] < sink_rates[j]) {
389 ++i;
390 } else {
391 ++j;
392 }
393 }
394 return k;
395 }
396
397 /* return index of rate in rates array, or -1 if not found */
intel_dp_rate_index(const int * rates,int len,int rate)398 static int intel_dp_rate_index(const int *rates, int len, int rate)
399 {
400 int i;
401
402 for (i = 0; i < len; i++)
403 if (rate == rates[i])
404 return i;
405
406 return -1;
407 }
408
intel_dp_set_common_rates(struct intel_dp * intel_dp)409 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
410 {
411 WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
412
413 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
414 intel_dp->num_source_rates,
415 intel_dp->sink_rates,
416 intel_dp->num_sink_rates,
417 intel_dp->common_rates);
418
419 /* Paranoia, there should always be something in common. */
420 if (WARN_ON(intel_dp->num_common_rates == 0)) {
421 intel_dp->common_rates[0] = 162000;
422 intel_dp->num_common_rates = 1;
423 }
424 }
425
intel_dp_link_params_valid(struct intel_dp * intel_dp,int link_rate,u8 lane_count)426 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
427 u8 lane_count)
428 {
429 /*
430 * FIXME: we need to synchronize the current link parameters with
431 * hardware readout. Currently fast link training doesn't work on
432 * boot-up.
433 */
434 if (link_rate == 0 ||
435 link_rate > intel_dp->max_link_rate)
436 return false;
437
438 if (lane_count == 0 ||
439 lane_count > intel_dp_max_lane_count(intel_dp))
440 return false;
441
442 return true;
443 }
444
intel_dp_can_link_train_fallback_for_edp(struct intel_dp * intel_dp,int link_rate,u8 lane_count)445 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
446 int link_rate,
447 u8 lane_count)
448 {
449 const struct drm_display_mode *fixed_mode =
450 intel_dp->attached_connector->panel.fixed_mode;
451 int mode_rate, max_rate;
452
453 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
454 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
455 if (mode_rate > max_rate)
456 return false;
457
458 return true;
459 }
460
intel_dp_get_link_train_fallback_values(struct intel_dp * intel_dp,int link_rate,u8 lane_count)461 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
462 int link_rate, u8 lane_count)
463 {
464 int index;
465
466 index = intel_dp_rate_index(intel_dp->common_rates,
467 intel_dp->num_common_rates,
468 link_rate);
469 if (index > 0) {
470 if (intel_dp_is_edp(intel_dp) &&
471 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
472 intel_dp->common_rates[index - 1],
473 lane_count)) {
474 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
475 return 0;
476 }
477 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
478 intel_dp->max_link_lane_count = lane_count;
479 } else if (lane_count > 1) {
480 if (intel_dp_is_edp(intel_dp) &&
481 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
482 intel_dp_max_common_rate(intel_dp),
483 lane_count >> 1)) {
484 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
485 return 0;
486 }
487 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
488 intel_dp->max_link_lane_count = lane_count >> 1;
489 } else {
490 DRM_ERROR("Link Training Unsuccessful\n");
491 return -1;
492 }
493
494 return 0;
495 }
496
intel_dp_mode_to_fec_clock(u32 mode_clock)497 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
498 {
499 return div_u64(mul_u32_u32(mode_clock, 1000000U),
500 DP_DSC_FEC_OVERHEAD_FACTOR);
501 }
502
503 static int
small_joiner_ram_size_bits(struct drm_i915_private * i915)504 small_joiner_ram_size_bits(struct drm_i915_private *i915)
505 {
506 if (INTEL_GEN(i915) >= 11)
507 return 7680 * 8;
508 else
509 return 6144 * 8;
510 }
511
intel_dp_dsc_get_output_bpp(struct drm_i915_private * i915,u32 link_clock,u32 lane_count,u32 mode_clock,u32 mode_hdisplay)512 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
513 u32 link_clock, u32 lane_count,
514 u32 mode_clock, u32 mode_hdisplay)
515 {
516 u32 bits_per_pixel, max_bpp_small_joiner_ram;
517 int i;
518
519 /*
520 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
521 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
522 * for SST -> TimeSlotsPerMTP is 1,
523 * for MST -> TimeSlotsPerMTP has to be calculated
524 */
525 bits_per_pixel = (link_clock * lane_count * 8) /
526 intel_dp_mode_to_fec_clock(mode_clock);
527 DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel);
528
529 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
530 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
531 mode_hdisplay;
532 DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
533
534 /*
535 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
536 * check, output bpp from small joiner RAM check)
537 */
538 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
539
540 /* Error out if the max bpp is less than smallest allowed valid bpp */
541 if (bits_per_pixel < valid_dsc_bpp[0]) {
542 DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
543 bits_per_pixel, valid_dsc_bpp[0]);
544 return 0;
545 }
546
547 /* Find the nearest match in the array of known BPPs from VESA */
548 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
549 if (bits_per_pixel < valid_dsc_bpp[i + 1])
550 break;
551 }
552 bits_per_pixel = valid_dsc_bpp[i];
553
554 /*
555 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
556 * fractional part is 0
557 */
558 return bits_per_pixel << 4;
559 }
560
intel_dp_dsc_get_slice_count(struct intel_dp * intel_dp,int mode_clock,int mode_hdisplay)561 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
562 int mode_clock, int mode_hdisplay)
563 {
564 u8 min_slice_count, i;
565 int max_slice_width;
566
567 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
568 min_slice_count = DIV_ROUND_UP(mode_clock,
569 DP_DSC_MAX_ENC_THROUGHPUT_0);
570 else
571 min_slice_count = DIV_ROUND_UP(mode_clock,
572 DP_DSC_MAX_ENC_THROUGHPUT_1);
573
574 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
575 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
576 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
577 max_slice_width);
578 return 0;
579 }
580 /* Also take into account max slice width */
581 min_slice_count = min_t(u8, min_slice_count,
582 DIV_ROUND_UP(mode_hdisplay,
583 max_slice_width));
584
585 /* Find the closest match to the valid slice count values */
586 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
587 if (valid_dsc_slicecount[i] >
588 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
589 false))
590 break;
591 if (min_slice_count <= valid_dsc_slicecount[i])
592 return valid_dsc_slicecount[i];
593 }
594
595 DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
596 return 0;
597 }
598
intel_dp_hdisplay_bad(struct drm_i915_private * dev_priv,int hdisplay)599 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
600 int hdisplay)
601 {
602 /*
603 * Older platforms don't like hdisplay==4096 with DP.
604 *
605 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
606 * and frame counter increment), but we don't get vblank interrupts,
607 * and the pipe underruns immediately. The link also doesn't seem
608 * to get trained properly.
609 *
610 * On CHV the vblank interrupts don't seem to disappear but
611 * otherwise the symptoms are similar.
612 *
613 * TODO: confirm the behaviour on HSW+
614 */
615 return hdisplay == 4096 && !HAS_DDI(dev_priv);
616 }
617
618 static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)619 intel_dp_mode_valid(struct drm_connector *connector,
620 struct drm_display_mode *mode)
621 {
622 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
623 struct intel_connector *intel_connector = to_intel_connector(connector);
624 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
625 struct drm_i915_private *dev_priv = to_i915(connector->dev);
626 int target_clock = mode->clock;
627 int max_rate, mode_rate, max_lanes, max_link_clock;
628 int max_dotclk;
629 u16 dsc_max_output_bpp = 0;
630 u8 dsc_slice_count = 0;
631
632 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
633 return MODE_NO_DBLESCAN;
634
635 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
636
637 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
638 if (mode->hdisplay > fixed_mode->hdisplay)
639 return MODE_PANEL;
640
641 if (mode->vdisplay > fixed_mode->vdisplay)
642 return MODE_PANEL;
643
644 target_clock = fixed_mode->clock;
645 }
646
647 max_link_clock = intel_dp_max_link_rate(intel_dp);
648 max_lanes = intel_dp_max_lane_count(intel_dp);
649
650 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
651 mode_rate = intel_dp_link_required(target_clock, 18);
652
653 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
654 return MODE_H_ILLEGAL;
655
656 /*
657 * Output bpp is stored in 6.4 format so right shift by 4 to get the
658 * integer value since we support only integer values of bpp.
659 */
660 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
661 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
662 if (intel_dp_is_edp(intel_dp)) {
663 dsc_max_output_bpp =
664 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
665 dsc_slice_count =
666 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
667 true);
668 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
669 dsc_max_output_bpp =
670 intel_dp_dsc_get_output_bpp(dev_priv,
671 max_link_clock,
672 max_lanes,
673 target_clock,
674 mode->hdisplay) >> 4;
675 dsc_slice_count =
676 intel_dp_dsc_get_slice_count(intel_dp,
677 target_clock,
678 mode->hdisplay);
679 }
680 }
681
682 if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
683 target_clock > max_dotclk)
684 return MODE_CLOCK_HIGH;
685
686 if (mode->clock < 10000)
687 return MODE_CLOCK_LOW;
688
689 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
690 return MODE_H_ILLEGAL;
691
692 return intel_mode_valid_max_plane_size(dev_priv, mode);
693 }
694
intel_dp_pack_aux(const u8 * src,int src_bytes)695 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
696 {
697 int i;
698 u32 v = 0;
699
700 if (src_bytes > 4)
701 src_bytes = 4;
702 for (i = 0; i < src_bytes; i++)
703 v |= ((u32)src[i]) << ((3 - i) * 8);
704 return v;
705 }
706
intel_dp_unpack_aux(u32 src,u8 * dst,int dst_bytes)707 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
708 {
709 int i;
710 if (dst_bytes > 4)
711 dst_bytes = 4;
712 for (i = 0; i < dst_bytes; i++)
713 dst[i] = src >> ((3-i) * 8);
714 }
715
716 static void
717 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
718 static void
719 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
720 bool force_disable_vdd);
721 static void
722 intel_dp_pps_init(struct intel_dp *intel_dp);
723
724 static intel_wakeref_t
pps_lock(struct intel_dp * intel_dp)725 pps_lock(struct intel_dp *intel_dp)
726 {
727 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
728 intel_wakeref_t wakeref;
729
730 /*
731 * See intel_power_sequencer_reset() why we need
732 * a power domain reference here.
733 */
734 wakeref = intel_display_power_get(dev_priv,
735 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
736
737 mutex_lock(&dev_priv->pps_mutex);
738
739 return wakeref;
740 }
741
742 static intel_wakeref_t
pps_unlock(struct intel_dp * intel_dp,intel_wakeref_t wakeref)743 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
744 {
745 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
746
747 mutex_unlock(&dev_priv->pps_mutex);
748 intel_display_power_put(dev_priv,
749 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
750 wakeref);
751 return 0;
752 }
753
754 #define with_pps_lock(dp, wf) \
755 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
756
757 static void
vlv_power_sequencer_kick(struct intel_dp * intel_dp)758 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
759 {
760 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
761 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
762 enum pipe pipe = intel_dp->pps_pipe;
763 bool pll_enabled, release_cl_override = false;
764 enum dpio_phy phy = DPIO_PHY(pipe);
765 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
766 u32 DP;
767
768 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
769 "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
770 pipe_name(pipe), intel_dig_port->base.base.base.id,
771 intel_dig_port->base.base.name))
772 return;
773
774 DRM_DEBUG_KMS("kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
775 pipe_name(pipe), intel_dig_port->base.base.base.id,
776 intel_dig_port->base.base.name);
777
778 /* Preserve the BIOS-computed detected bit. This is
779 * supposed to be read-only.
780 */
781 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
782 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
783 DP |= DP_PORT_WIDTH(1);
784 DP |= DP_LINK_TRAIN_PAT_1;
785
786 if (IS_CHERRYVIEW(dev_priv))
787 DP |= DP_PIPE_SEL_CHV(pipe);
788 else
789 DP |= DP_PIPE_SEL(pipe);
790
791 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
792
793 /*
794 * The DPLL for the pipe must be enabled for this to work.
795 * So enable temporarily it if it's not already enabled.
796 */
797 if (!pll_enabled) {
798 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
799 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
800
801 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
802 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
803 DRM_ERROR("Failed to force on pll for pipe %c!\n",
804 pipe_name(pipe));
805 return;
806 }
807 }
808
809 /*
810 * Similar magic as in intel_dp_enable_port().
811 * We _must_ do this port enable + disable trick
812 * to make this power sequencer lock onto the port.
813 * Otherwise even VDD force bit won't work.
814 */
815 I915_WRITE(intel_dp->output_reg, DP);
816 POSTING_READ(intel_dp->output_reg);
817
818 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
819 POSTING_READ(intel_dp->output_reg);
820
821 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
822 POSTING_READ(intel_dp->output_reg);
823
824 if (!pll_enabled) {
825 vlv_force_pll_off(dev_priv, pipe);
826
827 if (release_cl_override)
828 chv_phy_powergate_ch(dev_priv, phy, ch, false);
829 }
830 }
831
vlv_find_free_pps(struct drm_i915_private * dev_priv)832 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
833 {
834 struct intel_encoder *encoder;
835 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
836
837 /*
838 * We don't have power sequencer currently.
839 * Pick one that's not used by other ports.
840 */
841 for_each_intel_dp(&dev_priv->drm, encoder) {
842 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
843
844 if (encoder->type == INTEL_OUTPUT_EDP) {
845 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
846 intel_dp->active_pipe != intel_dp->pps_pipe);
847
848 if (intel_dp->pps_pipe != INVALID_PIPE)
849 pipes &= ~(1 << intel_dp->pps_pipe);
850 } else {
851 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
852
853 if (intel_dp->active_pipe != INVALID_PIPE)
854 pipes &= ~(1 << intel_dp->active_pipe);
855 }
856 }
857
858 if (pipes == 0)
859 return INVALID_PIPE;
860
861 return ffs(pipes) - 1;
862 }
863
864 static enum pipe
vlv_power_sequencer_pipe(struct intel_dp * intel_dp)865 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
866 {
867 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
868 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
869 enum pipe pipe;
870
871 lockdep_assert_held(&dev_priv->pps_mutex);
872
873 /* We should never land here with regular DP ports */
874 WARN_ON(!intel_dp_is_edp(intel_dp));
875
876 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
877 intel_dp->active_pipe != intel_dp->pps_pipe);
878
879 if (intel_dp->pps_pipe != INVALID_PIPE)
880 return intel_dp->pps_pipe;
881
882 pipe = vlv_find_free_pps(dev_priv);
883
884 /*
885 * Didn't find one. This should not happen since there
886 * are two power sequencers and up to two eDP ports.
887 */
888 if (WARN_ON(pipe == INVALID_PIPE))
889 pipe = PIPE_A;
890
891 vlv_steal_power_sequencer(dev_priv, pipe);
892 intel_dp->pps_pipe = pipe;
893
894 DRM_DEBUG_KMS("picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
895 pipe_name(intel_dp->pps_pipe),
896 intel_dig_port->base.base.base.id,
897 intel_dig_port->base.base.name);
898
899 /* init power sequencer on this pipe and port */
900 intel_dp_init_panel_power_sequencer(intel_dp);
901 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
902
903 /*
904 * Even vdd force doesn't work until we've made
905 * the power sequencer lock in on the port.
906 */
907 vlv_power_sequencer_kick(intel_dp);
908
909 return intel_dp->pps_pipe;
910 }
911
912 static int
bxt_power_sequencer_idx(struct intel_dp * intel_dp)913 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
914 {
915 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
916 int backlight_controller = dev_priv->vbt.backlight.controller;
917
918 lockdep_assert_held(&dev_priv->pps_mutex);
919
920 /* We should never land here with regular DP ports */
921 WARN_ON(!intel_dp_is_edp(intel_dp));
922
923 if (!intel_dp->pps_reset)
924 return backlight_controller;
925
926 intel_dp->pps_reset = false;
927
928 /*
929 * Only the HW needs to be reprogrammed, the SW state is fixed and
930 * has been setup during connector init.
931 */
932 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
933
934 return backlight_controller;
935 }
936
937 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
938 enum pipe pipe);
939
vlv_pipe_has_pp_on(struct drm_i915_private * dev_priv,enum pipe pipe)940 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942 {
943 return I915_READ(PP_STATUS(pipe)) & PP_ON;
944 }
945
vlv_pipe_has_vdd_on(struct drm_i915_private * dev_priv,enum pipe pipe)946 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
947 enum pipe pipe)
948 {
949 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
950 }
951
vlv_pipe_any(struct drm_i915_private * dev_priv,enum pipe pipe)952 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
953 enum pipe pipe)
954 {
955 return true;
956 }
957
958 static enum pipe
vlv_initial_pps_pipe(struct drm_i915_private * dev_priv,enum port port,vlv_pipe_check pipe_check)959 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
960 enum port port,
961 vlv_pipe_check pipe_check)
962 {
963 enum pipe pipe;
964
965 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
966 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
967 PANEL_PORT_SELECT_MASK;
968
969 if (port_sel != PANEL_PORT_SELECT_VLV(port))
970 continue;
971
972 if (!pipe_check(dev_priv, pipe))
973 continue;
974
975 return pipe;
976 }
977
978 return INVALID_PIPE;
979 }
980
981 static void
vlv_initial_power_sequencer_setup(struct intel_dp * intel_dp)982 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
983 {
984 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
985 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
986 enum port port = intel_dig_port->base.port;
987
988 lockdep_assert_held(&dev_priv->pps_mutex);
989
990 /* try to find a pipe with this port selected */
991 /* first pick one where the panel is on */
992 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
993 vlv_pipe_has_pp_on);
994 /* didn't find one? pick one where vdd is on */
995 if (intel_dp->pps_pipe == INVALID_PIPE)
996 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
997 vlv_pipe_has_vdd_on);
998 /* didn't find one? pick one with just the correct port */
999 if (intel_dp->pps_pipe == INVALID_PIPE)
1000 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1001 vlv_pipe_any);
1002
1003 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1004 if (intel_dp->pps_pipe == INVALID_PIPE) {
1005 DRM_DEBUG_KMS("no initial power sequencer for [ENCODER:%d:%s]\n",
1006 intel_dig_port->base.base.base.id,
1007 intel_dig_port->base.base.name);
1008 return;
1009 }
1010
1011 DRM_DEBUG_KMS("initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1012 intel_dig_port->base.base.base.id,
1013 intel_dig_port->base.base.name,
1014 pipe_name(intel_dp->pps_pipe));
1015
1016 intel_dp_init_panel_power_sequencer(intel_dp);
1017 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1018 }
1019
intel_power_sequencer_reset(struct drm_i915_private * dev_priv)1020 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1021 {
1022 struct intel_encoder *encoder;
1023
1024 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
1025 !IS_GEN9_LP(dev_priv)))
1026 return;
1027
1028 /*
1029 * We can't grab pps_mutex here due to deadlock with power_domain
1030 * mutex when power_domain functions are called while holding pps_mutex.
1031 * That also means that in order to use pps_pipe the code needs to
1032 * hold both a power domain reference and pps_mutex, and the power domain
1033 * reference get/put must be done while _not_ holding pps_mutex.
1034 * pps_{lock,unlock}() do these steps in the correct order, so one
1035 * should use them always.
1036 */
1037
1038 for_each_intel_dp(&dev_priv->drm, encoder) {
1039 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1040
1041 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
1042
1043 if (encoder->type != INTEL_OUTPUT_EDP)
1044 continue;
1045
1046 if (IS_GEN9_LP(dev_priv))
1047 intel_dp->pps_reset = true;
1048 else
1049 intel_dp->pps_pipe = INVALID_PIPE;
1050 }
1051 }
1052
1053 struct pps_registers {
1054 i915_reg_t pp_ctrl;
1055 i915_reg_t pp_stat;
1056 i915_reg_t pp_on;
1057 i915_reg_t pp_off;
1058 i915_reg_t pp_div;
1059 };
1060
intel_pps_get_registers(struct intel_dp * intel_dp,struct pps_registers * regs)1061 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1062 struct pps_registers *regs)
1063 {
1064 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1065 int pps_idx = 0;
1066
1067 memset(regs, 0, sizeof(*regs));
1068
1069 if (IS_GEN9_LP(dev_priv))
1070 pps_idx = bxt_power_sequencer_idx(intel_dp);
1071 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1072 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1073
1074 regs->pp_ctrl = PP_CONTROL(pps_idx);
1075 regs->pp_stat = PP_STATUS(pps_idx);
1076 regs->pp_on = PP_ON_DELAYS(pps_idx);
1077 regs->pp_off = PP_OFF_DELAYS(pps_idx);
1078
1079 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1080 if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1081 regs->pp_div = INVALID_MMIO_REG;
1082 else
1083 regs->pp_div = PP_DIVISOR(pps_idx);
1084 }
1085
1086 static i915_reg_t
_pp_ctrl_reg(struct intel_dp * intel_dp)1087 _pp_ctrl_reg(struct intel_dp *intel_dp)
1088 {
1089 struct pps_registers regs;
1090
1091 intel_pps_get_registers(intel_dp, ®s);
1092
1093 return regs.pp_ctrl;
1094 }
1095
1096 static i915_reg_t
_pp_stat_reg(struct intel_dp * intel_dp)1097 _pp_stat_reg(struct intel_dp *intel_dp)
1098 {
1099 struct pps_registers regs;
1100
1101 intel_pps_get_registers(intel_dp, ®s);
1102
1103 return regs.pp_stat;
1104 }
1105
1106 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1107 This function only applicable when panel PM state is not to be tracked */
edp_notify_handler(struct notifier_block * this,unsigned long code,void * unused)1108 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1109 void *unused)
1110 {
1111 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1112 edp_notifier);
1113 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1114 intel_wakeref_t wakeref;
1115
1116 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1117 return 0;
1118
1119 with_pps_lock(intel_dp, wakeref) {
1120 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1121 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1122 i915_reg_t pp_ctrl_reg, pp_div_reg;
1123 u32 pp_div;
1124
1125 pp_ctrl_reg = PP_CONTROL(pipe);
1126 pp_div_reg = PP_DIVISOR(pipe);
1127 pp_div = I915_READ(pp_div_reg);
1128 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1129
1130 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1131 I915_WRITE(pp_div_reg, pp_div | 0x1F);
1132 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1133 msleep(intel_dp->panel_power_cycle_delay);
1134 }
1135 }
1136
1137 return 0;
1138 }
1139
edp_have_panel_power(struct intel_dp * intel_dp)1140 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1141 {
1142 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1143
1144 lockdep_assert_held(&dev_priv->pps_mutex);
1145
1146 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1147 intel_dp->pps_pipe == INVALID_PIPE)
1148 return false;
1149
1150 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1151 }
1152
edp_have_panel_vdd(struct intel_dp * intel_dp)1153 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1154 {
1155 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1156
1157 lockdep_assert_held(&dev_priv->pps_mutex);
1158
1159 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1160 intel_dp->pps_pipe == INVALID_PIPE)
1161 return false;
1162
1163 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1164 }
1165
1166 static void
intel_dp_check_edp(struct intel_dp * intel_dp)1167 intel_dp_check_edp(struct intel_dp *intel_dp)
1168 {
1169 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1170
1171 if (!intel_dp_is_edp(intel_dp))
1172 return;
1173
1174 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1175 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1176 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1177 I915_READ(_pp_stat_reg(intel_dp)),
1178 I915_READ(_pp_ctrl_reg(intel_dp)));
1179 }
1180 }
1181
1182 static u32
intel_dp_aux_wait_done(struct intel_dp * intel_dp)1183 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1184 {
1185 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1186 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1187 const unsigned int timeout_ms = 10;
1188 u32 status;
1189 bool done;
1190
1191 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1192 #ifdef __NetBSD__
1193 if (!cold) {
1194 int ret;
1195 spin_lock(&i915->gmbus_wait_lock);
1196 DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret,
1197 &i915->gmbus_wait_queue, &i915->gmbus_wait_lock,
1198 msecs_to_jiffies_timeout(timeout_ms),
1199 C);
1200 /*
1201 * ret<0 on error (-ERESTARTSYS, interrupt); ret=0 on
1202 * timeout; ret>0 on success. We care about success
1203 * only.
1204 */
1205 done = (ret > 0);
1206 spin_unlock(&i915->gmbus_wait_lock);
1207 } else {
1208 done = wait_for_atomic(C, timeout_ms) == 0;
1209 }
1210 #else
1211 done = wait_event_timeout(i915->gmbus_wait_queue, C,
1212 msecs_to_jiffies_timeout(timeout_ms));
1213
1214 #endif
1215
1216 /* just trace the final value */
1217 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1218
1219 if (!done)
1220 DRM_ERROR("%s did not complete or timeout within %ums (status 0x%08x)\n",
1221 intel_dp->aux.name, timeout_ms, status);
1222 #undef C
1223
1224 return status;
1225 }
1226
g4x_get_aux_clock_divider(struct intel_dp * intel_dp,int index)1227 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1228 {
1229 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1230
1231 if (index)
1232 return 0;
1233
1234 /*
1235 * The clock divider is based off the hrawclk, and would like to run at
1236 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
1237 */
1238 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1239 }
1240
ilk_get_aux_clock_divider(struct intel_dp * intel_dp,int index)1241 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1242 {
1243 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1244 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1245
1246 if (index)
1247 return 0;
1248
1249 /*
1250 * The clock divider is based off the cdclk or PCH rawclk, and would
1251 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1252 * divide by 2000 and use that
1253 */
1254 if (dig_port->aux_ch == AUX_CH_A)
1255 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1256 else
1257 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1258 }
1259
hsw_get_aux_clock_divider(struct intel_dp * intel_dp,int index)1260 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1261 {
1262 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1263 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1264
1265 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1266 /* Workaround for non-ULT HSW */
1267 switch (index) {
1268 case 0: return 63;
1269 case 1: return 72;
1270 default: return 0;
1271 }
1272 }
1273
1274 return ilk_get_aux_clock_divider(intel_dp, index);
1275 }
1276
skl_get_aux_clock_divider(struct intel_dp * intel_dp,int index)1277 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1278 {
1279 /*
1280 * SKL doesn't need us to program the AUX clock divider (Hardware will
1281 * derive the clock from CDCLK automatically). We still implement the
1282 * get_aux_clock_divider vfunc to plug-in into the existing code.
1283 */
1284 return index ? 0 : 1;
1285 }
1286
g4x_get_aux_send_ctl(struct intel_dp * intel_dp,int send_bytes,u32 aux_clock_divider)1287 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1288 int send_bytes,
1289 u32 aux_clock_divider)
1290 {
1291 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1292 struct drm_i915_private *dev_priv =
1293 to_i915(intel_dig_port->base.base.dev);
1294 u32 precharge, timeout;
1295
1296 if (IS_GEN(dev_priv, 6))
1297 precharge = 3;
1298 else
1299 precharge = 5;
1300
1301 if (IS_BROADWELL(dev_priv))
1302 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1303 else
1304 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1305
1306 return DP_AUX_CH_CTL_SEND_BUSY |
1307 DP_AUX_CH_CTL_DONE |
1308 DP_AUX_CH_CTL_INTERRUPT |
1309 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1310 timeout |
1311 DP_AUX_CH_CTL_RECEIVE_ERROR |
1312 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1313 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1314 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1315 }
1316
skl_get_aux_send_ctl(struct intel_dp * intel_dp,int send_bytes,u32 unused)1317 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1318 int send_bytes,
1319 u32 unused)
1320 {
1321 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1322 struct drm_i915_private *i915 =
1323 to_i915(intel_dig_port->base.base.dev);
1324 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1325 u32 ret;
1326
1327 ret = DP_AUX_CH_CTL_SEND_BUSY |
1328 DP_AUX_CH_CTL_DONE |
1329 DP_AUX_CH_CTL_INTERRUPT |
1330 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1331 DP_AUX_CH_CTL_TIME_OUT_MAX |
1332 DP_AUX_CH_CTL_RECEIVE_ERROR |
1333 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1334 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1335 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1336
1337 if (intel_phy_is_tc(i915, phy) &&
1338 intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1339 ret |= DP_AUX_CH_CTL_TBT_IO;
1340
1341 return ret;
1342 }
1343
1344 static int
intel_dp_aux_xfer(struct intel_dp * intel_dp,const u8 * send,int send_bytes,u8 * recv,int recv_size,u32 aux_send_ctl_flags)1345 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1346 const u8 *send, int send_bytes,
1347 u8 *recv, int recv_size,
1348 u32 aux_send_ctl_flags)
1349 {
1350 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1351 struct drm_i915_private *i915 =
1352 to_i915(intel_dig_port->base.base.dev);
1353 struct intel_uncore *uncore = &i915->uncore;
1354 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1355 bool is_tc_port = intel_phy_is_tc(i915, phy);
1356 i915_reg_t ch_ctl, ch_data[5];
1357 u32 aux_clock_divider;
1358 enum intel_display_power_domain aux_domain =
1359 intel_aux_power_domain(intel_dig_port);
1360 intel_wakeref_t aux_wakeref;
1361 intel_wakeref_t pps_wakeref;
1362 int i, ret, recv_bytes;
1363 int try, clock = 0;
1364 u32 status;
1365 bool vdd;
1366
1367 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1368 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1369 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1370
1371 if (is_tc_port)
1372 intel_tc_port_lock(intel_dig_port);
1373
1374 aux_wakeref = intel_display_power_get(i915, aux_domain);
1375 pps_wakeref = pps_lock(intel_dp);
1376
1377 /*
1378 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1379 * In such cases we want to leave VDD enabled and it's up to upper layers
1380 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1381 * ourselves.
1382 */
1383 vdd = edp_panel_vdd_on(intel_dp);
1384
1385 /* dp aux is extremely sensitive to irq latency, hence request the
1386 * lowest possible wakeup latency and so prevent the cpu from going into
1387 * deep sleep states.
1388 */
1389 pm_qos_update_request(&i915->pm_qos, 0);
1390
1391 intel_dp_check_edp(intel_dp);
1392
1393 /* Try to wait for any previous AUX channel activity */
1394 for (try = 0; try < 3; try++) {
1395 status = intel_uncore_read_notrace(uncore, ch_ctl);
1396 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1397 break;
1398 msleep(1);
1399 }
1400 /* just trace the final value */
1401 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1402
1403 if (try == 3) {
1404 const u32 status = intel_uncore_read(uncore, ch_ctl);
1405
1406 if (status != intel_dp->aux_busy_last_status) {
1407 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1408 status);
1409 intel_dp->aux_busy_last_status = status;
1410 }
1411
1412 ret = -EBUSY;
1413 goto out;
1414 }
1415
1416 /* Only 5 data registers! */
1417 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1418 ret = -E2BIG;
1419 goto out;
1420 }
1421
1422 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1423 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1424 send_bytes,
1425 aux_clock_divider);
1426
1427 send_ctl |= aux_send_ctl_flags;
1428
1429 /* Must try at least 3 times according to DP spec */
1430 for (try = 0; try < 5; try++) {
1431 /* Load the send data into the aux channel data registers */
1432 for (i = 0; i < send_bytes; i += 4)
1433 intel_uncore_write(uncore,
1434 ch_data[i >> 2],
1435 intel_dp_pack_aux(send + i,
1436 send_bytes - i));
1437
1438 /* Send the command and wait for it to complete */
1439 intel_uncore_write(uncore, ch_ctl, send_ctl);
1440
1441 status = intel_dp_aux_wait_done(intel_dp);
1442
1443 /* Clear done status and any errors */
1444 intel_uncore_write(uncore,
1445 ch_ctl,
1446 status |
1447 DP_AUX_CH_CTL_DONE |
1448 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1449 DP_AUX_CH_CTL_RECEIVE_ERROR);
1450
1451 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1452 * 400us delay required for errors and timeouts
1453 * Timeout errors from the HW already meet this
1454 * requirement so skip to next iteration
1455 */
1456 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1457 continue;
1458
1459 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1460 usleep_range(400, 500);
1461 continue;
1462 }
1463 if (status & DP_AUX_CH_CTL_DONE)
1464 goto done;
1465 }
1466 }
1467
1468 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1469 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1470 ret = -EBUSY;
1471 goto out;
1472 }
1473
1474 done:
1475 /* Check for timeout or receive error.
1476 * Timeouts occur when the sink is not connected
1477 */
1478 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1479 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1480 ret = -EIO;
1481 goto out;
1482 }
1483
1484 /* Timeouts occur when the device isn't connected, so they're
1485 * "normal" -- don't fill the kernel log with these */
1486 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1487 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1488 ret = -ETIMEDOUT;
1489 goto out;
1490 }
1491
1492 /* Unload any bytes sent back from the other side */
1493 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1494 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1495
1496 /*
1497 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1498 * We have no idea of what happened so we return -EBUSY so
1499 * drm layer takes care for the necessary retries.
1500 */
1501 if (recv_bytes == 0 || recv_bytes > 20) {
1502 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1503 recv_bytes);
1504 ret = -EBUSY;
1505 goto out;
1506 }
1507
1508 if (recv_bytes > recv_size)
1509 recv_bytes = recv_size;
1510
1511 for (i = 0; i < recv_bytes; i += 4)
1512 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1513 recv + i, recv_bytes - i);
1514
1515 ret = recv_bytes;
1516 out:
1517 pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1518
1519 if (vdd)
1520 edp_panel_vdd_off(intel_dp, false);
1521
1522 pps_unlock(intel_dp, pps_wakeref);
1523 intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1524
1525 if (is_tc_port)
1526 intel_tc_port_unlock(intel_dig_port);
1527
1528 return ret;
1529 }
1530
1531 #define BARE_ADDRESS_SIZE 3
1532 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1533
1534 static void
intel_dp_aux_header(u8 txbuf[HEADER_SIZE],const struct drm_dp_aux_msg * msg)1535 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1536 const struct drm_dp_aux_msg *msg)
1537 {
1538 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1539 txbuf[1] = (msg->address >> 8) & 0xff;
1540 txbuf[2] = msg->address & 0xff;
1541 txbuf[3] = msg->size - 1;
1542 }
1543
1544 static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)1545 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1546 {
1547 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1548 u8 txbuf[20], rxbuf[20];
1549 size_t txsize, rxsize;
1550 int ret;
1551
1552 intel_dp_aux_header(txbuf, msg);
1553
1554 switch (msg->request & ~DP_AUX_I2C_MOT) {
1555 case DP_AUX_NATIVE_WRITE:
1556 case DP_AUX_I2C_WRITE:
1557 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1558 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1559 rxsize = 2; /* 0 or 1 data bytes */
1560
1561 if (WARN_ON(txsize > 20))
1562 return -E2BIG;
1563
1564 WARN_ON(!msg->buffer != !msg->size);
1565
1566 if (msg->buffer)
1567 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1568
1569 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1570 rxbuf, rxsize, 0);
1571 if (ret > 0) {
1572 msg->reply = rxbuf[0] >> 4;
1573
1574 if (ret > 1) {
1575 /* Number of bytes written in a short write. */
1576 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1577 } else {
1578 /* Return payload size. */
1579 ret = msg->size;
1580 }
1581 }
1582 break;
1583
1584 case DP_AUX_NATIVE_READ:
1585 case DP_AUX_I2C_READ:
1586 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1587 rxsize = msg->size + 1;
1588
1589 if (WARN_ON(rxsize > 20))
1590 return -E2BIG;
1591
1592 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1593 rxbuf, rxsize, 0);
1594 if (ret > 0) {
1595 msg->reply = rxbuf[0] >> 4;
1596 /*
1597 * Assume happy day, and copy the data. The caller is
1598 * expected to check msg->reply before touching it.
1599 *
1600 * Return payload size.
1601 */
1602 ret--;
1603 memcpy(msg->buffer, rxbuf + 1, ret);
1604 }
1605 break;
1606
1607 default:
1608 ret = -EINVAL;
1609 break;
1610 }
1611
1612 return ret;
1613 }
1614
1615
g4x_aux_ctl_reg(struct intel_dp * intel_dp)1616 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1617 {
1618 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1619 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1620 enum aux_ch aux_ch = dig_port->aux_ch;
1621
1622 switch (aux_ch) {
1623 case AUX_CH_B:
1624 case AUX_CH_C:
1625 case AUX_CH_D:
1626 return DP_AUX_CH_CTL(aux_ch);
1627 default:
1628 MISSING_CASE(aux_ch);
1629 return DP_AUX_CH_CTL(AUX_CH_B);
1630 }
1631 }
1632
g4x_aux_data_reg(struct intel_dp * intel_dp,int index)1633 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1634 {
1635 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1636 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1637 enum aux_ch aux_ch = dig_port->aux_ch;
1638
1639 switch (aux_ch) {
1640 case AUX_CH_B:
1641 case AUX_CH_C:
1642 case AUX_CH_D:
1643 return DP_AUX_CH_DATA(aux_ch, index);
1644 default:
1645 MISSING_CASE(aux_ch);
1646 return DP_AUX_CH_DATA(AUX_CH_B, index);
1647 }
1648 }
1649
ilk_aux_ctl_reg(struct intel_dp * intel_dp)1650 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1651 {
1652 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1653 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1654 enum aux_ch aux_ch = dig_port->aux_ch;
1655
1656 switch (aux_ch) {
1657 case AUX_CH_A:
1658 return DP_AUX_CH_CTL(aux_ch);
1659 case AUX_CH_B:
1660 case AUX_CH_C:
1661 case AUX_CH_D:
1662 return PCH_DP_AUX_CH_CTL(aux_ch);
1663 default:
1664 MISSING_CASE(aux_ch);
1665 return DP_AUX_CH_CTL(AUX_CH_A);
1666 }
1667 }
1668
ilk_aux_data_reg(struct intel_dp * intel_dp,int index)1669 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1670 {
1671 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1672 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1673 enum aux_ch aux_ch = dig_port->aux_ch;
1674
1675 switch (aux_ch) {
1676 case AUX_CH_A:
1677 return DP_AUX_CH_DATA(aux_ch, index);
1678 case AUX_CH_B:
1679 case AUX_CH_C:
1680 case AUX_CH_D:
1681 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1682 default:
1683 MISSING_CASE(aux_ch);
1684 return DP_AUX_CH_DATA(AUX_CH_A, index);
1685 }
1686 }
1687
skl_aux_ctl_reg(struct intel_dp * intel_dp)1688 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1689 {
1690 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1691 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1692 enum aux_ch aux_ch = dig_port->aux_ch;
1693
1694 switch (aux_ch) {
1695 case AUX_CH_A:
1696 case AUX_CH_B:
1697 case AUX_CH_C:
1698 case AUX_CH_D:
1699 case AUX_CH_E:
1700 case AUX_CH_F:
1701 case AUX_CH_G:
1702 return DP_AUX_CH_CTL(aux_ch);
1703 default:
1704 MISSING_CASE(aux_ch);
1705 return DP_AUX_CH_CTL(AUX_CH_A);
1706 }
1707 }
1708
skl_aux_data_reg(struct intel_dp * intel_dp,int index)1709 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1710 {
1711 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1712 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1713 enum aux_ch aux_ch = dig_port->aux_ch;
1714
1715 switch (aux_ch) {
1716 case AUX_CH_A:
1717 case AUX_CH_B:
1718 case AUX_CH_C:
1719 case AUX_CH_D:
1720 case AUX_CH_E:
1721 case AUX_CH_F:
1722 case AUX_CH_G:
1723 return DP_AUX_CH_DATA(aux_ch, index);
1724 default:
1725 MISSING_CASE(aux_ch);
1726 return DP_AUX_CH_DATA(AUX_CH_A, index);
1727 }
1728 }
1729
1730 static void
intel_dp_aux_fini(struct intel_dp * intel_dp)1731 intel_dp_aux_fini(struct intel_dp *intel_dp)
1732 {
1733 drm_dp_aux_fini(&intel_dp->aux);
1734 kfree(__UNCONST(intel_dp->aux.name));
1735 }
1736
1737 static void
intel_dp_aux_init(struct intel_dp * intel_dp)1738 intel_dp_aux_init(struct intel_dp *intel_dp)
1739 {
1740 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1741 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1742 struct intel_encoder *encoder = &dig_port->base;
1743
1744 if (INTEL_GEN(dev_priv) >= 9) {
1745 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1746 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1747 } else if (HAS_PCH_SPLIT(dev_priv)) {
1748 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1749 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1750 } else {
1751 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1752 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1753 }
1754
1755 if (INTEL_GEN(dev_priv) >= 9)
1756 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1757 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1758 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1759 else if (HAS_PCH_SPLIT(dev_priv))
1760 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1761 else
1762 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1763
1764 if (INTEL_GEN(dev_priv) >= 9)
1765 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1766 else
1767 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1768
1769 drm_dp_aux_init(&intel_dp->aux);
1770
1771 /* Failure to allocate our preferred name is not critical */
1772 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1773 port_name(encoder->port));
1774 intel_dp->aux.transfer = intel_dp_aux_transfer;
1775 }
1776
intel_dp_source_supports_hbr2(struct intel_dp * intel_dp)1777 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1778 {
1779 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1780
1781 return max_rate >= 540000;
1782 }
1783
intel_dp_source_supports_hbr3(struct intel_dp * intel_dp)1784 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1785 {
1786 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1787
1788 return max_rate >= 810000;
1789 }
1790
1791 static void
intel_dp_set_clock(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1792 intel_dp_set_clock(struct intel_encoder *encoder,
1793 struct intel_crtc_state *pipe_config)
1794 {
1795 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1796 const struct dp_link_dpll *divisor = NULL;
1797 int i, count = 0;
1798
1799 if (IS_G4X(dev_priv)) {
1800 divisor = g4x_dpll;
1801 count = ARRAY_SIZE(g4x_dpll);
1802 } else if (HAS_PCH_SPLIT(dev_priv)) {
1803 divisor = pch_dpll;
1804 count = ARRAY_SIZE(pch_dpll);
1805 } else if (IS_CHERRYVIEW(dev_priv)) {
1806 divisor = chv_dpll;
1807 count = ARRAY_SIZE(chv_dpll);
1808 } else if (IS_VALLEYVIEW(dev_priv)) {
1809 divisor = vlv_dpll;
1810 count = ARRAY_SIZE(vlv_dpll);
1811 }
1812
1813 if (divisor && count) {
1814 for (i = 0; i < count; i++) {
1815 if (pipe_config->port_clock == divisor[i].clock) {
1816 pipe_config->dpll = divisor[i].dpll;
1817 pipe_config->clock_set = true;
1818 break;
1819 }
1820 }
1821 }
1822 }
1823
snprintf_int_array(char * str,size_t len,const int * array,int nelem)1824 static void snprintf_int_array(char *str, size_t len,
1825 const int *array, int nelem)
1826 {
1827 int i;
1828
1829 str[0] = '\0';
1830
1831 for (i = 0; i < nelem; i++) {
1832 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1833 if (r >= len)
1834 return;
1835 str += r;
1836 len -= r;
1837 }
1838 }
1839
intel_dp_print_rates(struct intel_dp * intel_dp)1840 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1841 {
1842 char str[128]; /* FIXME: too big for stack? */
1843
1844 if (!drm_debug_enabled(DRM_UT_KMS))
1845 return;
1846
1847 snprintf_int_array(str, sizeof(str),
1848 intel_dp->source_rates, intel_dp->num_source_rates);
1849 DRM_DEBUG_KMS("source rates: %s\n", str);
1850
1851 snprintf_int_array(str, sizeof(str),
1852 intel_dp->sink_rates, intel_dp->num_sink_rates);
1853 DRM_DEBUG_KMS("sink rates: %s\n", str);
1854
1855 snprintf_int_array(str, sizeof(str),
1856 intel_dp->common_rates, intel_dp->num_common_rates);
1857 DRM_DEBUG_KMS("common rates: %s\n", str);
1858 }
1859
1860 int
intel_dp_max_link_rate(struct intel_dp * intel_dp)1861 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1862 {
1863 int len;
1864
1865 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1866 if (WARN_ON(len <= 0))
1867 return 162000;
1868
1869 return intel_dp->common_rates[len - 1];
1870 }
1871
intel_dp_rate_select(struct intel_dp * intel_dp,int rate)1872 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1873 {
1874 int i = intel_dp_rate_index(intel_dp->sink_rates,
1875 intel_dp->num_sink_rates, rate);
1876
1877 if (WARN_ON(i < 0))
1878 i = 0;
1879
1880 return i;
1881 }
1882
intel_dp_compute_rate(struct intel_dp * intel_dp,int port_clock,u8 * link_bw,u8 * rate_select)1883 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1884 u8 *link_bw, u8 *rate_select)
1885 {
1886 /* eDP 1.4 rate select method. */
1887 if (intel_dp->use_rate_select) {
1888 *link_bw = 0;
1889 *rate_select =
1890 intel_dp_rate_select(intel_dp, port_clock);
1891 } else {
1892 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1893 *rate_select = 0;
1894 }
1895 }
1896
intel_dp_source_supports_fec(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)1897 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1898 const struct intel_crtc_state *pipe_config)
1899 {
1900 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1901
1902 /* On TGL, FEC is supported on all Pipes */
1903 if (INTEL_GEN(dev_priv) >= 12)
1904 return true;
1905
1906 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1907 return true;
1908
1909 return false;
1910 }
1911
intel_dp_supports_fec(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)1912 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1913 const struct intel_crtc_state *pipe_config)
1914 {
1915 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1916 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1917 }
1918
intel_dp_supports_dsc(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1919 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1920 const struct intel_crtc_state *crtc_state)
1921 {
1922 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1923
1924 if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
1925 return false;
1926
1927 return intel_dsc_source_support(encoder, crtc_state) &&
1928 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1929 }
1930
intel_dp_compute_bpp(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config)1931 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1932 struct intel_crtc_state *pipe_config)
1933 {
1934 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1935 struct intel_connector *intel_connector = intel_dp->attached_connector;
1936 int bpp, bpc;
1937
1938 bpp = pipe_config->pipe_bpp;
1939 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1940
1941 if (bpc > 0)
1942 bpp = min(bpp, 3*bpc);
1943
1944 if (intel_dp_is_edp(intel_dp)) {
1945 /* Get bpp from vbt only for panels that dont have bpp in edid */
1946 if (intel_connector->base.display_info.bpc == 0 &&
1947 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1948 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1949 dev_priv->vbt.edp.bpp);
1950 bpp = dev_priv->vbt.edp.bpp;
1951 }
1952 }
1953
1954 return bpp;
1955 }
1956
1957 /* Adjust link config limits based on compliance test requests. */
1958 void
intel_dp_adjust_compliance_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct link_config_limits * limits)1959 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1960 struct intel_crtc_state *pipe_config,
1961 struct link_config_limits *limits)
1962 {
1963 /* For DP Compliance we override the computed bpp for the pipe */
1964 if (intel_dp->compliance.test_data.bpc != 0) {
1965 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1966
1967 limits->min_bpp = limits->max_bpp = bpp;
1968 pipe_config->dither_force_disable = bpp == 6 * 3;
1969
1970 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1971 }
1972
1973 /* Use values requested by Compliance Test Request */
1974 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1975 int index;
1976
1977 /* Validate the compliance test data since max values
1978 * might have changed due to link train fallback.
1979 */
1980 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1981 intel_dp->compliance.test_lane_count)) {
1982 index = intel_dp_rate_index(intel_dp->common_rates,
1983 intel_dp->num_common_rates,
1984 intel_dp->compliance.test_link_rate);
1985 if (index >= 0)
1986 limits->min_clock = limits->max_clock = index;
1987 limits->min_lane_count = limits->max_lane_count =
1988 intel_dp->compliance.test_lane_count;
1989 }
1990 }
1991 }
1992
intel_dp_output_bpp(const struct intel_crtc_state * crtc_state,int bpp)1993 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
1994 {
1995 /*
1996 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1997 * format of the number of bytes per pixel will be half the number
1998 * of bytes of RGB pixel.
1999 */
2000 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2001 bpp /= 2;
2002
2003 return bpp;
2004 }
2005
2006 /* Optimize link config in order: max bpp, min clock, min lanes */
2007 static int
intel_dp_compute_link_config_wide(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,const struct link_config_limits * limits)2008 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2009 struct intel_crtc_state *pipe_config,
2010 const struct link_config_limits *limits)
2011 {
2012 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2013 int bpp, clock, lane_count;
2014 int mode_rate, link_clock, link_avail;
2015
2016 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2017 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
2018
2019 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2020 output_bpp);
2021
2022 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2023 for (lane_count = limits->min_lane_count;
2024 lane_count <= limits->max_lane_count;
2025 lane_count <<= 1) {
2026 link_clock = intel_dp->common_rates[clock];
2027 link_avail = intel_dp_max_data_rate(link_clock,
2028 lane_count);
2029
2030 if (mode_rate <= link_avail) {
2031 pipe_config->lane_count = lane_count;
2032 pipe_config->pipe_bpp = bpp;
2033 pipe_config->port_clock = link_clock;
2034
2035 return 0;
2036 }
2037 }
2038 }
2039 }
2040
2041 return -EINVAL;
2042 }
2043
intel_dp_dsc_compute_bpp(struct intel_dp * intel_dp,u8 dsc_max_bpc)2044 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2045 {
2046 int i, num_bpc;
2047 u8 dsc_bpc[3] = {0};
2048
2049 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2050 dsc_bpc);
2051 for (i = 0; i < num_bpc; i++) {
2052 if (dsc_max_bpc >= dsc_bpc[i])
2053 return dsc_bpc[i] * 3;
2054 }
2055
2056 return 0;
2057 }
2058
2059 #define DSC_SUPPORTED_VERSION_MIN 1
2060
intel_dp_dsc_compute_params(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)2061 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2062 struct intel_crtc_state *crtc_state)
2063 {
2064 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2065 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2066 u8 line_buf_depth;
2067 int ret;
2068
2069 ret = intel_dsc_compute_params(encoder, crtc_state);
2070 if (ret)
2071 return ret;
2072
2073 /*
2074 * Slice Height of 8 works for all currently available panels. So start
2075 * with that if pic_height is an integral multiple of 8. Eventually add
2076 * logic to try multiple slice heights.
2077 */
2078 if (vdsc_cfg->pic_height % 8 == 0)
2079 vdsc_cfg->slice_height = 8;
2080 else if (vdsc_cfg->pic_height % 4 == 0)
2081 vdsc_cfg->slice_height = 4;
2082 else
2083 vdsc_cfg->slice_height = 2;
2084
2085 vdsc_cfg->dsc_version_major =
2086 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2087 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2088 vdsc_cfg->dsc_version_minor =
2089 min(DSC_SUPPORTED_VERSION_MIN,
2090 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2091 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2092
2093 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2094 DP_DSC_RGB;
2095
2096 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2097 if (!line_buf_depth) {
2098 DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
2099 return -EINVAL;
2100 }
2101
2102 if (vdsc_cfg->dsc_version_minor == 2)
2103 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2104 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2105 else
2106 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2107 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2108
2109 vdsc_cfg->block_pred_enable =
2110 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2111 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2112
2113 return drm_dsc_compute_rc_parameters(vdsc_cfg);
2114 }
2115
intel_dp_dsc_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,struct link_config_limits * limits)2116 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2117 struct intel_crtc_state *pipe_config,
2118 struct drm_connector_state *conn_state,
2119 struct link_config_limits *limits)
2120 {
2121 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2122 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2123 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2124 u8 dsc_max_bpc;
2125 int pipe_bpp;
2126 int ret;
2127
2128 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2129 intel_dp_supports_fec(intel_dp, pipe_config);
2130
2131 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2132 return -EINVAL;
2133
2134 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2135 if (INTEL_GEN(dev_priv) >= 12)
2136 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2137 else
2138 dsc_max_bpc = min_t(u8, 10,
2139 conn_state->max_requested_bpc);
2140
2141 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2142
2143 /* Min Input BPC for ICL+ is 8 */
2144 if (pipe_bpp < 8 * 3) {
2145 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
2146 return -EINVAL;
2147 }
2148
2149 /*
2150 * For now enable DSC for max bpp, max link rate, max lane count.
2151 * Optimize this later for the minimum possible link rate/lane count
2152 * with DSC enabled for the requested mode.
2153 */
2154 pipe_config->pipe_bpp = pipe_bpp;
2155 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2156 pipe_config->lane_count = limits->max_lane_count;
2157
2158 if (intel_dp_is_edp(intel_dp)) {
2159 pipe_config->dsc.compressed_bpp =
2160 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2161 pipe_config->pipe_bpp);
2162 pipe_config->dsc.slice_count =
2163 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2164 true);
2165 } else {
2166 u16 dsc_max_output_bpp;
2167 u8 dsc_dp_slice_count;
2168
2169 dsc_max_output_bpp =
2170 intel_dp_dsc_get_output_bpp(dev_priv,
2171 pipe_config->port_clock,
2172 pipe_config->lane_count,
2173 adjusted_mode->crtc_clock,
2174 adjusted_mode->crtc_hdisplay);
2175 dsc_dp_slice_count =
2176 intel_dp_dsc_get_slice_count(intel_dp,
2177 adjusted_mode->crtc_clock,
2178 adjusted_mode->crtc_hdisplay);
2179 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2180 DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
2181 return -EINVAL;
2182 }
2183 pipe_config->dsc.compressed_bpp = min_t(u16,
2184 dsc_max_output_bpp >> 4,
2185 pipe_config->pipe_bpp);
2186 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2187 }
2188 /*
2189 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2190 * is greater than the maximum Cdclock and if slice count is even
2191 * then we need to use 2 VDSC instances.
2192 */
2193 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2194 if (pipe_config->dsc.slice_count > 1) {
2195 pipe_config->dsc.dsc_split = true;
2196 } else {
2197 DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
2198 return -EINVAL;
2199 }
2200 }
2201
2202 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2203 if (ret < 0) {
2204 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
2205 "Compressed BPP = %d\n",
2206 pipe_config->pipe_bpp,
2207 pipe_config->dsc.compressed_bpp);
2208 return ret;
2209 }
2210
2211 pipe_config->dsc.compression_enable = true;
2212 DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
2213 "Compressed Bpp = %d Slice Count = %d\n",
2214 pipe_config->pipe_bpp,
2215 pipe_config->dsc.compressed_bpp,
2216 pipe_config->dsc.slice_count);
2217
2218 return 0;
2219 }
2220
intel_dp_min_bpp(const struct intel_crtc_state * crtc_state)2221 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2222 {
2223 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2224 return 6 * 3;
2225 else
2226 return 8 * 3;
2227 }
2228
2229 static int
intel_dp_compute_link_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)2230 intel_dp_compute_link_config(struct intel_encoder *encoder,
2231 struct intel_crtc_state *pipe_config,
2232 struct drm_connector_state *conn_state)
2233 {
2234 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2235 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2236 struct link_config_limits limits;
2237 int common_len;
2238 int ret;
2239
2240 common_len = intel_dp_common_len_rate_limit(intel_dp,
2241 intel_dp->max_link_rate);
2242
2243 /* No common link rates between source and sink */
2244 WARN_ON(common_len <= 0);
2245
2246 limits.min_clock = 0;
2247 limits.max_clock = common_len - 1;
2248
2249 limits.min_lane_count = 1;
2250 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2251
2252 limits.min_bpp = intel_dp_min_bpp(pipe_config);
2253 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2254
2255 if (intel_dp_is_edp(intel_dp)) {
2256 /*
2257 * Use the maximum clock and number of lanes the eDP panel
2258 * advertizes being capable of. The panels are generally
2259 * designed to support only a single clock and lane
2260 * configuration, and typically these values correspond to the
2261 * native resolution of the panel.
2262 */
2263 limits.min_lane_count = limits.max_lane_count;
2264 limits.min_clock = limits.max_clock;
2265 }
2266
2267 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2268
2269 DRM_DEBUG_KMS("DP link computation with max lane count %i "
2270 "max rate %d max bpp %d pixel clock %iKHz\n",
2271 limits.max_lane_count,
2272 intel_dp->common_rates[limits.max_clock],
2273 limits.max_bpp, adjusted_mode->crtc_clock);
2274
2275 /*
2276 * Optimize for slow and wide. This is the place to add alternative
2277 * optimization policy.
2278 */
2279 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2280
2281 /* enable compression if the mode doesn't fit available BW */
2282 DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2283 if (ret || intel_dp->force_dsc_en) {
2284 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2285 conn_state, &limits);
2286 if (ret < 0)
2287 return ret;
2288 }
2289
2290 if (pipe_config->dsc.compression_enable) {
2291 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2292 pipe_config->lane_count, pipe_config->port_clock,
2293 pipe_config->pipe_bpp,
2294 pipe_config->dsc.compressed_bpp);
2295
2296 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2297 intel_dp_link_required(adjusted_mode->crtc_clock,
2298 pipe_config->dsc.compressed_bpp),
2299 intel_dp_max_data_rate(pipe_config->port_clock,
2300 pipe_config->lane_count));
2301 } else {
2302 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2303 pipe_config->lane_count, pipe_config->port_clock,
2304 pipe_config->pipe_bpp);
2305
2306 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2307 intel_dp_link_required(adjusted_mode->crtc_clock,
2308 pipe_config->pipe_bpp),
2309 intel_dp_max_data_rate(pipe_config->port_clock,
2310 pipe_config->lane_count));
2311 }
2312 return 0;
2313 }
2314
2315 static int
intel_dp_ycbcr420_config(struct intel_dp * intel_dp,struct drm_connector * connector,struct intel_crtc_state * crtc_state)2316 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2317 struct drm_connector *connector,
2318 struct intel_crtc_state *crtc_state)
2319 {
2320 const struct drm_display_info *info = &connector->display_info;
2321 const struct drm_display_mode *adjusted_mode =
2322 &crtc_state->hw.adjusted_mode;
2323 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2324 int ret;
2325
2326 if (!drm_mode_is_420_only(info, adjusted_mode) ||
2327 !intel_dp_get_colorimetry_status(intel_dp) ||
2328 !connector->ycbcr_420_allowed)
2329 return 0;
2330
2331 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2332
2333 /* YCBCR 420 output conversion needs a scaler */
2334 ret = skl_update_scaler_crtc(crtc_state);
2335 if (ret) {
2336 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2337 return ret;
2338 }
2339
2340 intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2341
2342 return 0;
2343 }
2344
intel_dp_limited_color_range(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2345 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2346 const struct drm_connector_state *conn_state)
2347 {
2348 const struct intel_digital_connector_state *intel_conn_state =
2349 const_container_of(conn_state, struct intel_digital_connector_state, base);
2350 const struct drm_display_mode *adjusted_mode =
2351 &crtc_state->hw.adjusted_mode;
2352
2353 /*
2354 * Our YCbCr output is always limited range.
2355 * crtc_state->limited_color_range only applies to RGB,
2356 * and it must never be set for YCbCr or we risk setting
2357 * some conflicting bits in PIPECONF which will mess up
2358 * the colors on the monitor.
2359 */
2360 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2361 return false;
2362
2363 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2364 /*
2365 * See:
2366 * CEA-861-E - 5.1 Default Encoding Parameters
2367 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2368 */
2369 return crtc_state->pipe_bpp != 18 &&
2370 drm_default_rgb_quant_range(adjusted_mode) ==
2371 HDMI_QUANTIZATION_RANGE_LIMITED;
2372 } else {
2373 return intel_conn_state->broadcast_rgb ==
2374 INTEL_BROADCAST_RGB_LIMITED;
2375 }
2376 }
2377
intel_dp_port_has_audio(struct drm_i915_private * dev_priv,enum port port)2378 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2379 enum port port)
2380 {
2381 if (IS_G4X(dev_priv))
2382 return false;
2383 if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2384 return false;
2385
2386 return true;
2387 }
2388
2389 int
intel_dp_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)2390 intel_dp_compute_config(struct intel_encoder *encoder,
2391 struct intel_crtc_state *pipe_config,
2392 struct drm_connector_state *conn_state)
2393 {
2394 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2395 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2396 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2397 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
2398 enum port port = encoder->port;
2399 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
2400 struct intel_connector *intel_connector = intel_dp->attached_connector;
2401 struct intel_digital_connector_state *intel_conn_state =
2402 to_intel_digital_connector_state(conn_state);
2403 bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2404 DP_DPCD_QUIRK_CONSTANT_N);
2405 int ret = 0, output_bpp;
2406
2407 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2408 pipe_config->has_pch_encoder = true;
2409
2410 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2411
2412 if (lspcon->active)
2413 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2414 else
2415 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2416 pipe_config);
2417
2418 if (ret)
2419 return ret;
2420
2421 pipe_config->has_drrs = false;
2422 if (!intel_dp_port_has_audio(dev_priv, port))
2423 pipe_config->has_audio = false;
2424 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2425 pipe_config->has_audio = intel_dp->has_audio;
2426 else
2427 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2428
2429 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2430 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2431 adjusted_mode);
2432
2433 if (INTEL_GEN(dev_priv) >= 9) {
2434 ret = skl_update_scaler_crtc(pipe_config);
2435 if (ret)
2436 return ret;
2437 }
2438
2439 if (HAS_GMCH(dev_priv))
2440 intel_gmch_panel_fitting(intel_crtc, pipe_config,
2441 conn_state->scaling_mode);
2442 else
2443 intel_pch_panel_fitting(intel_crtc, pipe_config,
2444 conn_state->scaling_mode);
2445 }
2446
2447 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2448 return -EINVAL;
2449
2450 if (HAS_GMCH(dev_priv) &&
2451 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2452 return -EINVAL;
2453
2454 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2455 return -EINVAL;
2456
2457 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2458 return -EINVAL;
2459
2460 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2461 if (ret < 0)
2462 return ret;
2463
2464 pipe_config->limited_color_range =
2465 intel_dp_limited_color_range(pipe_config, conn_state);
2466
2467 if (pipe_config->dsc.compression_enable)
2468 output_bpp = pipe_config->dsc.compressed_bpp;
2469 else
2470 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2471
2472 intel_link_compute_m_n(output_bpp,
2473 pipe_config->lane_count,
2474 adjusted_mode->crtc_clock,
2475 pipe_config->port_clock,
2476 &pipe_config->dp_m_n,
2477 constant_n, pipe_config->fec_enable);
2478
2479 if (intel_connector->panel.downclock_mode != NULL &&
2480 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2481 pipe_config->has_drrs = true;
2482 intel_link_compute_m_n(output_bpp,
2483 pipe_config->lane_count,
2484 intel_connector->panel.downclock_mode->clock,
2485 pipe_config->port_clock,
2486 &pipe_config->dp_m2_n2,
2487 constant_n, pipe_config->fec_enable);
2488 }
2489
2490 if (!HAS_DDI(dev_priv))
2491 intel_dp_set_clock(encoder, pipe_config);
2492
2493 intel_psr_compute_config(intel_dp, pipe_config);
2494
2495 return 0;
2496 }
2497
intel_dp_set_link_params(struct intel_dp * intel_dp,int link_rate,u8 lane_count,bool link_mst)2498 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2499 int link_rate, u8 lane_count,
2500 bool link_mst)
2501 {
2502 intel_dp->link_trained = false;
2503 intel_dp->link_rate = link_rate;
2504 intel_dp->lane_count = lane_count;
2505 intel_dp->link_mst = link_mst;
2506 }
2507
intel_dp_prepare(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)2508 static void intel_dp_prepare(struct intel_encoder *encoder,
2509 const struct intel_crtc_state *pipe_config)
2510 {
2511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2512 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2513 enum port port = encoder->port;
2514 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2515 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2516
2517 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2518 pipe_config->lane_count,
2519 intel_crtc_has_type(pipe_config,
2520 INTEL_OUTPUT_DP_MST));
2521
2522 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
2523 intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
2524
2525 /*
2526 * There are four kinds of DP registers:
2527 *
2528 * IBX PCH
2529 * SNB CPU
2530 * IVB CPU
2531 * CPT PCH
2532 *
2533 * IBX PCH and CPU are the same for almost everything,
2534 * except that the CPU DP PLL is configured in this
2535 * register
2536 *
2537 * CPT PCH is quite different, having many bits moved
2538 * to the TRANS_DP_CTL register instead. That
2539 * configuration happens (oddly) in ilk_pch_enable
2540 */
2541
2542 /* Preserve the BIOS-computed detected bit. This is
2543 * supposed to be read-only.
2544 */
2545 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2546
2547 /* Handle DP bits in common between all three register formats */
2548 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2549 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2550
2551 /* Split out the IBX/CPU vs CPT settings */
2552
2553 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2554 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2555 intel_dp->DP |= DP_SYNC_HS_HIGH;
2556 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2557 intel_dp->DP |= DP_SYNC_VS_HIGH;
2558 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2559
2560 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2561 intel_dp->DP |= DP_ENHANCED_FRAMING;
2562
2563 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2564 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2565 u32 trans_dp;
2566
2567 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2568
2569 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2570 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2571 trans_dp |= TRANS_DP_ENH_FRAMING;
2572 else
2573 trans_dp &= ~TRANS_DP_ENH_FRAMING;
2574 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2575 } else {
2576 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2577 intel_dp->DP |= DP_COLOR_RANGE_16_235;
2578
2579 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2580 intel_dp->DP |= DP_SYNC_HS_HIGH;
2581 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2582 intel_dp->DP |= DP_SYNC_VS_HIGH;
2583 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2584
2585 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2586 intel_dp->DP |= DP_ENHANCED_FRAMING;
2587
2588 if (IS_CHERRYVIEW(dev_priv))
2589 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2590 else
2591 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2592 }
2593 }
2594
2595 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2596 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2597
2598 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2599 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2600
2601 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2602 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2603
2604 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2605
wait_panel_status(struct intel_dp * intel_dp,u32 mask,u32 value)2606 static void wait_panel_status(struct intel_dp *intel_dp,
2607 u32 mask,
2608 u32 value)
2609 {
2610 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2611 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2612
2613 lockdep_assert_held(&dev_priv->pps_mutex);
2614
2615 intel_pps_verify_state(intel_dp);
2616
2617 pp_stat_reg = _pp_stat_reg(intel_dp);
2618 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2619
2620 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2621 mask, value,
2622 I915_READ(pp_stat_reg),
2623 I915_READ(pp_ctrl_reg));
2624
2625 if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2626 mask, value, 5000))
2627 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2628 I915_READ(pp_stat_reg),
2629 I915_READ(pp_ctrl_reg));
2630
2631 DRM_DEBUG_KMS("Wait complete\n");
2632 }
2633
wait_panel_on(struct intel_dp * intel_dp)2634 static void wait_panel_on(struct intel_dp *intel_dp)
2635 {
2636 DRM_DEBUG_KMS("Wait for panel power on\n");
2637 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2638 }
2639
wait_panel_off(struct intel_dp * intel_dp)2640 static void wait_panel_off(struct intel_dp *intel_dp)
2641 {
2642 DRM_DEBUG_KMS("Wait for panel power off time\n");
2643 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2644 }
2645
wait_panel_power_cycle(struct intel_dp * intel_dp)2646 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2647 {
2648 ktime_t panel_power_on_time;
2649 s64 panel_power_off_duration;
2650
2651 DRM_DEBUG_KMS("Wait for panel power cycle\n");
2652
2653 /* take the difference of currrent time and panel power off time
2654 * and then make panel wait for t11_t12 if needed. */
2655 panel_power_on_time = ktime_get_boottime();
2656 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2657
2658 /* When we disable the VDD override bit last we have to do the manual
2659 * wait. */
2660 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2661 wait_remaining_ms_from_jiffies(jiffies,
2662 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2663
2664 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2665 }
2666
wait_backlight_on(struct intel_dp * intel_dp)2667 static void wait_backlight_on(struct intel_dp *intel_dp)
2668 {
2669 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2670 intel_dp->backlight_on_delay);
2671 }
2672
edp_wait_backlight_off(struct intel_dp * intel_dp)2673 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2674 {
2675 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2676 intel_dp->backlight_off_delay);
2677 }
2678
2679 /* Read the current pp_control value, unlocking the register if it
2680 * is locked
2681 */
2682
ilk_get_pp_control(struct intel_dp * intel_dp)2683 static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
2684 {
2685 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2686 u32 control;
2687
2688 lockdep_assert_held(&dev_priv->pps_mutex);
2689
2690 control = I915_READ(_pp_ctrl_reg(intel_dp));
2691 if (WARN_ON(!HAS_DDI(dev_priv) &&
2692 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2693 control &= ~PANEL_UNLOCK_MASK;
2694 control |= PANEL_UNLOCK_REGS;
2695 }
2696 return control;
2697 }
2698
2699 /*
2700 * Must be paired with edp_panel_vdd_off().
2701 * Must hold pps_mutex around the whole on/off sequence.
2702 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2703 */
edp_panel_vdd_on(struct intel_dp * intel_dp)2704 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2705 {
2706 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2707 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2708 u32 pp;
2709 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2710 bool need_to_disable = !intel_dp->want_panel_vdd;
2711
2712 lockdep_assert_held(&dev_priv->pps_mutex);
2713
2714 if (!intel_dp_is_edp(intel_dp))
2715 return false;
2716
2717 cancel_delayed_work(&intel_dp->panel_vdd_work);
2718 intel_dp->want_panel_vdd = true;
2719
2720 if (edp_have_panel_vdd(intel_dp))
2721 return need_to_disable;
2722
2723 intel_display_power_get(dev_priv,
2724 intel_aux_power_domain(intel_dig_port));
2725
2726 DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD on\n",
2727 intel_dig_port->base.base.base.id,
2728 intel_dig_port->base.base.name);
2729
2730 if (!edp_have_panel_power(intel_dp))
2731 wait_panel_power_cycle(intel_dp);
2732
2733 pp = ilk_get_pp_control(intel_dp);
2734 pp |= EDP_FORCE_VDD;
2735
2736 pp_stat_reg = _pp_stat_reg(intel_dp);
2737 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2738
2739 I915_WRITE(pp_ctrl_reg, pp);
2740 POSTING_READ(pp_ctrl_reg);
2741 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2742 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2743 /*
2744 * If the panel wasn't on, delay before accessing aux channel
2745 */
2746 if (!edp_have_panel_power(intel_dp)) {
2747 DRM_DEBUG_KMS("[ENCODER:%d:%s] panel power wasn't enabled\n",
2748 intel_dig_port->base.base.base.id,
2749 intel_dig_port->base.base.name);
2750 msleep(intel_dp->panel_power_up_delay);
2751 }
2752
2753 return need_to_disable;
2754 }
2755
2756 /*
2757 * Must be paired with intel_edp_panel_vdd_off() or
2758 * intel_edp_panel_off().
2759 * Nested calls to these functions are not allowed since
2760 * we drop the lock. Caller must use some higher level
2761 * locking to prevent nested calls from other threads.
2762 */
intel_edp_panel_vdd_on(struct intel_dp * intel_dp)2763 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2764 {
2765 intel_wakeref_t wakeref;
2766 bool vdd;
2767
2768 if (!intel_dp_is_edp(intel_dp))
2769 return;
2770
2771 vdd = false;
2772 with_pps_lock(intel_dp, wakeref)
2773 vdd = edp_panel_vdd_on(intel_dp);
2774 I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2775 dp_to_dig_port(intel_dp)->base.base.base.id,
2776 dp_to_dig_port(intel_dp)->base.base.name);
2777 }
2778
edp_panel_vdd_off_sync(struct intel_dp * intel_dp)2779 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2780 {
2781 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2782 struct intel_digital_port *intel_dig_port =
2783 dp_to_dig_port(intel_dp);
2784 u32 pp;
2785 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2786
2787 lockdep_assert_held(&dev_priv->pps_mutex);
2788
2789 WARN_ON(intel_dp->want_panel_vdd);
2790
2791 if (!edp_have_panel_vdd(intel_dp))
2792 return;
2793
2794 DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD off\n",
2795 intel_dig_port->base.base.base.id,
2796 intel_dig_port->base.base.name);
2797
2798 pp = ilk_get_pp_control(intel_dp);
2799 pp &= ~EDP_FORCE_VDD;
2800
2801 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2802 pp_stat_reg = _pp_stat_reg(intel_dp);
2803
2804 I915_WRITE(pp_ctrl_reg, pp);
2805 POSTING_READ(pp_ctrl_reg);
2806
2807 /* Make sure sequencer is idle before allowing subsequent activity */
2808 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2809 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2810
2811 if ((pp & PANEL_POWER_ON) == 0)
2812 intel_dp->panel_power_off_time = ktime_get_boottime();
2813
2814 intel_display_power_put_unchecked(dev_priv,
2815 intel_aux_power_domain(intel_dig_port));
2816 }
2817
edp_panel_vdd_work(struct work_struct * __work)2818 static void edp_panel_vdd_work(struct work_struct *__work)
2819 {
2820 struct intel_dp *intel_dp =
2821 container_of(to_delayed_work(__work),
2822 struct intel_dp, panel_vdd_work);
2823 intel_wakeref_t wakeref;
2824
2825 with_pps_lock(intel_dp, wakeref) {
2826 if (!intel_dp->want_panel_vdd)
2827 edp_panel_vdd_off_sync(intel_dp);
2828 }
2829 }
2830
edp_panel_vdd_schedule_off(struct intel_dp * intel_dp)2831 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2832 {
2833 unsigned long delay;
2834
2835 /*
2836 * Queue the timer to fire a long time from now (relative to the power
2837 * down delay) to keep the panel power up across a sequence of
2838 * operations.
2839 */
2840 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2841 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2842 }
2843
2844 /*
2845 * Must be paired with edp_panel_vdd_on().
2846 * Must hold pps_mutex around the whole on/off sequence.
2847 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2848 */
edp_panel_vdd_off(struct intel_dp * intel_dp,bool sync)2849 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2850 {
2851 struct drm_i915_private *dev_priv __lockdep_used = dp_to_i915(intel_dp);
2852
2853 lockdep_assert_held(&dev_priv->pps_mutex);
2854
2855 if (!intel_dp_is_edp(intel_dp))
2856 return;
2857
2858 I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
2859 dp_to_dig_port(intel_dp)->base.base.base.id,
2860 dp_to_dig_port(intel_dp)->base.base.name);
2861
2862 intel_dp->want_panel_vdd = false;
2863
2864 if (sync)
2865 edp_panel_vdd_off_sync(intel_dp);
2866 else
2867 edp_panel_vdd_schedule_off(intel_dp);
2868 }
2869
edp_panel_on(struct intel_dp * intel_dp)2870 static void edp_panel_on(struct intel_dp *intel_dp)
2871 {
2872 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2873 u32 pp;
2874 i915_reg_t pp_ctrl_reg;
2875
2876 lockdep_assert_held(&dev_priv->pps_mutex);
2877
2878 if (!intel_dp_is_edp(intel_dp))
2879 return;
2880
2881 DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power on\n",
2882 dp_to_dig_port(intel_dp)->base.base.base.id,
2883 dp_to_dig_port(intel_dp)->base.base.name);
2884
2885 if (WARN(edp_have_panel_power(intel_dp),
2886 "[ENCODER:%d:%s] panel power already on\n",
2887 dp_to_dig_port(intel_dp)->base.base.base.id,
2888 dp_to_dig_port(intel_dp)->base.base.name))
2889 return;
2890
2891 wait_panel_power_cycle(intel_dp);
2892
2893 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2894 pp = ilk_get_pp_control(intel_dp);
2895 if (IS_GEN(dev_priv, 5)) {
2896 /* ILK workaround: disable reset around power sequence */
2897 pp &= ~PANEL_POWER_RESET;
2898 I915_WRITE(pp_ctrl_reg, pp);
2899 POSTING_READ(pp_ctrl_reg);
2900 }
2901
2902 pp |= PANEL_POWER_ON;
2903 if (!IS_GEN(dev_priv, 5))
2904 pp |= PANEL_POWER_RESET;
2905
2906 I915_WRITE(pp_ctrl_reg, pp);
2907 POSTING_READ(pp_ctrl_reg);
2908
2909 wait_panel_on(intel_dp);
2910 intel_dp->last_power_on = jiffies;
2911
2912 if (IS_GEN(dev_priv, 5)) {
2913 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2914 I915_WRITE(pp_ctrl_reg, pp);
2915 POSTING_READ(pp_ctrl_reg);
2916 }
2917 }
2918
intel_edp_panel_on(struct intel_dp * intel_dp)2919 void intel_edp_panel_on(struct intel_dp *intel_dp)
2920 {
2921 intel_wakeref_t wakeref;
2922
2923 if (!intel_dp_is_edp(intel_dp))
2924 return;
2925
2926 with_pps_lock(intel_dp, wakeref)
2927 edp_panel_on(intel_dp);
2928 }
2929
2930
edp_panel_off(struct intel_dp * intel_dp)2931 static void edp_panel_off(struct intel_dp *intel_dp)
2932 {
2933 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2934 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2935 u32 pp;
2936 i915_reg_t pp_ctrl_reg;
2937
2938 lockdep_assert_held(&dev_priv->pps_mutex);
2939
2940 if (!intel_dp_is_edp(intel_dp))
2941 return;
2942
2943 DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power off\n",
2944 dig_port->base.base.base.id, dig_port->base.base.name);
2945
2946 WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n",
2947 dig_port->base.base.base.id, dig_port->base.base.name);
2948
2949 pp = ilk_get_pp_control(intel_dp);
2950 /* We need to switch off panel power _and_ force vdd, for otherwise some
2951 * panels get very unhappy and cease to work. */
2952 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2953 EDP_BLC_ENABLE);
2954
2955 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2956
2957 intel_dp->want_panel_vdd = false;
2958
2959 I915_WRITE(pp_ctrl_reg, pp);
2960 POSTING_READ(pp_ctrl_reg);
2961
2962 wait_panel_off(intel_dp);
2963 intel_dp->panel_power_off_time = ktime_get_boottime();
2964
2965 /* We got a reference when we enabled the VDD. */
2966 intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2967 }
2968
intel_edp_panel_off(struct intel_dp * intel_dp)2969 void intel_edp_panel_off(struct intel_dp *intel_dp)
2970 {
2971 intel_wakeref_t wakeref;
2972
2973 if (!intel_dp_is_edp(intel_dp))
2974 return;
2975
2976 with_pps_lock(intel_dp, wakeref)
2977 edp_panel_off(intel_dp);
2978 }
2979
2980 /* Enable backlight in the panel power control. */
_intel_edp_backlight_on(struct intel_dp * intel_dp)2981 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2982 {
2983 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2984 intel_wakeref_t wakeref;
2985
2986 /*
2987 * If we enable the backlight right away following a panel power
2988 * on, we may see slight flicker as the panel syncs with the eDP
2989 * link. So delay a bit to make sure the image is solid before
2990 * allowing it to appear.
2991 */
2992 wait_backlight_on(intel_dp);
2993
2994 with_pps_lock(intel_dp, wakeref) {
2995 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2996 u32 pp;
2997
2998 pp = ilk_get_pp_control(intel_dp);
2999 pp |= EDP_BLC_ENABLE;
3000
3001 I915_WRITE(pp_ctrl_reg, pp);
3002 POSTING_READ(pp_ctrl_reg);
3003 }
3004 }
3005
3006 /* Enable backlight PWM and backlight PP control. */
intel_edp_backlight_on(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3007 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3008 const struct drm_connector_state *conn_state)
3009 {
3010 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3011
3012 if (!intel_dp_is_edp(intel_dp))
3013 return;
3014
3015 DRM_DEBUG_KMS("\n");
3016
3017 intel_panel_enable_backlight(crtc_state, conn_state);
3018 _intel_edp_backlight_on(intel_dp);
3019 }
3020
3021 /* Disable backlight in the panel power control. */
_intel_edp_backlight_off(struct intel_dp * intel_dp)3022 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3023 {
3024 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3025 intel_wakeref_t wakeref;
3026
3027 if (!intel_dp_is_edp(intel_dp))
3028 return;
3029
3030 with_pps_lock(intel_dp, wakeref) {
3031 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3032 u32 pp;
3033
3034 pp = ilk_get_pp_control(intel_dp);
3035 pp &= ~EDP_BLC_ENABLE;
3036
3037 I915_WRITE(pp_ctrl_reg, pp);
3038 POSTING_READ(pp_ctrl_reg);
3039 }
3040
3041 intel_dp->last_backlight_off = jiffies;
3042 edp_wait_backlight_off(intel_dp);
3043 }
3044
3045 /* Disable backlight PP control and backlight PWM. */
intel_edp_backlight_off(const struct drm_connector_state * old_conn_state)3046 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3047 {
3048 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3049
3050 if (!intel_dp_is_edp(intel_dp))
3051 return;
3052
3053 DRM_DEBUG_KMS("\n");
3054
3055 _intel_edp_backlight_off(intel_dp);
3056 intel_panel_disable_backlight(old_conn_state);
3057 }
3058
3059 /*
3060 * Hook for controlling the panel power control backlight through the bl_power
3061 * sysfs attribute. Take care to handle multiple calls.
3062 */
intel_edp_backlight_power(struct intel_connector * connector,bool enable)3063 static void intel_edp_backlight_power(struct intel_connector *connector,
3064 bool enable)
3065 {
3066 struct intel_dp *intel_dp = intel_attached_dp(connector);
3067 intel_wakeref_t wakeref;
3068 bool is_enabled;
3069
3070 is_enabled = false;
3071 with_pps_lock(intel_dp, wakeref)
3072 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3073 if (is_enabled == enable)
3074 return;
3075
3076 DRM_DEBUG_KMS("panel power control backlight %s\n",
3077 enable ? "enable" : "disable");
3078
3079 if (enable)
3080 _intel_edp_backlight_on(intel_dp);
3081 else
3082 _intel_edp_backlight_off(intel_dp);
3083 }
3084
assert_dp_port(struct intel_dp * intel_dp,bool state)3085 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3086 {
3087 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3088 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3089 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
3090
3091 I915_STATE_WARN(cur_state != state,
3092 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3093 dig_port->base.base.base.id, dig_port->base.base.name,
3094 onoff(state), onoff(cur_state));
3095 }
3096 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3097
assert_edp_pll(struct drm_i915_private * dev_priv,bool state)3098 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3099 {
3100 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
3101
3102 I915_STATE_WARN(cur_state != state,
3103 "eDP PLL state assertion failure (expected %s, current %s)\n",
3104 onoff(state), onoff(cur_state));
3105 }
3106 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3107 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3108
ilk_edp_pll_on(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)3109 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3110 const struct intel_crtc_state *pipe_config)
3111 {
3112 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3113 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3114
3115 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3116 assert_dp_port_disabled(intel_dp);
3117 assert_edp_pll_disabled(dev_priv);
3118
3119 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
3120 pipe_config->port_clock);
3121
3122 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3123
3124 if (pipe_config->port_clock == 162000)
3125 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3126 else
3127 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3128
3129 I915_WRITE(DP_A, intel_dp->DP);
3130 POSTING_READ(DP_A);
3131 udelay(500);
3132
3133 /*
3134 * [DevILK] Work around required when enabling DP PLL
3135 * while a pipe is enabled going to FDI:
3136 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3137 * 2. Program DP PLL enable
3138 */
3139 if (IS_GEN(dev_priv, 5))
3140 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3141
3142 intel_dp->DP |= DP_PLL_ENABLE;
3143
3144 I915_WRITE(DP_A, intel_dp->DP);
3145 POSTING_READ(DP_A);
3146 udelay(200);
3147 }
3148
ilk_edp_pll_off(struct intel_dp * intel_dp,const struct intel_crtc_state * old_crtc_state)3149 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3150 const struct intel_crtc_state *old_crtc_state)
3151 {
3152 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3153 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3154
3155 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3156 assert_dp_port_disabled(intel_dp);
3157 assert_edp_pll_enabled(dev_priv);
3158
3159 DRM_DEBUG_KMS("disabling eDP PLL\n");
3160
3161 intel_dp->DP &= ~DP_PLL_ENABLE;
3162
3163 I915_WRITE(DP_A, intel_dp->DP);
3164 POSTING_READ(DP_A);
3165 udelay(200);
3166 }
3167
downstream_hpd_needs_d0(struct intel_dp * intel_dp)3168 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3169 {
3170 /*
3171 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3172 * be capable of signalling downstream hpd with a long pulse.
3173 * Whether or not that means D3 is safe to use is not clear,
3174 * but let's assume so until proven otherwise.
3175 *
3176 * FIXME should really check all downstream ports...
3177 */
3178 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3179 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
3180 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3181 }
3182
intel_dp_sink_set_decompression_state(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool enable)3183 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3184 const struct intel_crtc_state *crtc_state,
3185 bool enable)
3186 {
3187 int ret;
3188
3189 if (!crtc_state->dsc.compression_enable)
3190 return;
3191
3192 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3193 enable ? DP_DECOMPRESSION_EN : 0);
3194 if (ret < 0)
3195 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
3196 enable ? "enable" : "disable");
3197 }
3198
3199 /* If the sink supports it, try to set the power state appropriately */
intel_dp_sink_dpms(struct intel_dp * intel_dp,int mode)3200 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3201 {
3202 int ret, i;
3203
3204 /* Should have a valid DPCD by this point */
3205 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3206 return;
3207
3208 if (mode != DRM_MODE_DPMS_ON) {
3209 if (downstream_hpd_needs_d0(intel_dp))
3210 return;
3211
3212 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3213 DP_SET_POWER_D3);
3214 } else {
3215 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3216
3217 /*
3218 * When turning on, we need to retry for 1ms to give the sink
3219 * time to wake up.
3220 */
3221 for (i = 0; i < 3; i++) {
3222 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3223 DP_SET_POWER_D0);
3224 if (ret == 1)
3225 break;
3226 msleep(1);
3227 }
3228
3229 if (ret == 1 && lspcon->active)
3230 lspcon_wait_pcon_mode(lspcon);
3231 }
3232
3233 if (ret != 1)
3234 DRM_DEBUG_KMS("failed to %s sink power state\n",
3235 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3236 }
3237
cpt_dp_port_selected(struct drm_i915_private * dev_priv,enum port port,enum pipe * pipe)3238 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3239 enum port port, enum pipe *pipe)
3240 {
3241 enum pipe p;
3242
3243 for_each_pipe(dev_priv, p) {
3244 u32 val = I915_READ(TRANS_DP_CTL(p));
3245
3246 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3247 *pipe = p;
3248 return true;
3249 }
3250 }
3251
3252 DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
3253
3254 /* must initialize pipe to something for the asserts */
3255 *pipe = PIPE_A;
3256
3257 return false;
3258 }
3259
intel_dp_port_enabled(struct drm_i915_private * dev_priv,i915_reg_t dp_reg,enum port port,enum pipe * pipe)3260 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3261 i915_reg_t dp_reg, enum port port,
3262 enum pipe *pipe)
3263 {
3264 bool ret;
3265 u32 val;
3266
3267 val = I915_READ(dp_reg);
3268
3269 ret = val & DP_PORT_EN;
3270
3271 /* asserts want to know the pipe even if the port is disabled */
3272 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3273 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3274 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3275 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3276 else if (IS_CHERRYVIEW(dev_priv))
3277 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3278 else
3279 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3280
3281 return ret;
3282 }
3283
intel_dp_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)3284 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3285 enum pipe *pipe)
3286 {
3287 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3288 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3289 intel_wakeref_t wakeref;
3290 bool ret;
3291
3292 wakeref = intel_display_power_get_if_enabled(dev_priv,
3293 encoder->power_domain);
3294 if (!wakeref)
3295 return false;
3296
3297 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3298 encoder->port, pipe);
3299
3300 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3301
3302 return ret;
3303 }
3304
intel_dp_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)3305 static void intel_dp_get_config(struct intel_encoder *encoder,
3306 struct intel_crtc_state *pipe_config)
3307 {
3308 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3309 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3310 u32 tmp, flags = 0;
3311 enum port port = encoder->port;
3312 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3313
3314 if (encoder->type == INTEL_OUTPUT_EDP)
3315 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3316 else
3317 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3318
3319 tmp = I915_READ(intel_dp->output_reg);
3320
3321 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3322
3323 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3324 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3325
3326 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3327 flags |= DRM_MODE_FLAG_PHSYNC;
3328 else
3329 flags |= DRM_MODE_FLAG_NHSYNC;
3330
3331 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3332 flags |= DRM_MODE_FLAG_PVSYNC;
3333 else
3334 flags |= DRM_MODE_FLAG_NVSYNC;
3335 } else {
3336 if (tmp & DP_SYNC_HS_HIGH)
3337 flags |= DRM_MODE_FLAG_PHSYNC;
3338 else
3339 flags |= DRM_MODE_FLAG_NHSYNC;
3340
3341 if (tmp & DP_SYNC_VS_HIGH)
3342 flags |= DRM_MODE_FLAG_PVSYNC;
3343 else
3344 flags |= DRM_MODE_FLAG_NVSYNC;
3345 }
3346
3347 pipe_config->hw.adjusted_mode.flags |= flags;
3348
3349 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3350 pipe_config->limited_color_range = true;
3351
3352 pipe_config->lane_count =
3353 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3354
3355 intel_dp_get_m_n(crtc, pipe_config);
3356
3357 if (port == PORT_A) {
3358 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3359 pipe_config->port_clock = 162000;
3360 else
3361 pipe_config->port_clock = 270000;
3362 }
3363
3364 pipe_config->hw.adjusted_mode.crtc_clock =
3365 intel_dotclock_calculate(pipe_config->port_clock,
3366 &pipe_config->dp_m_n);
3367
3368 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3369 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3370 /*
3371 * This is a big fat ugly hack.
3372 *
3373 * Some machines in UEFI boot mode provide us a VBT that has 18
3374 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3375 * unknown we fail to light up. Yet the same BIOS boots up with
3376 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3377 * max, not what it tells us to use.
3378 *
3379 * Note: This will still be broken if the eDP panel is not lit
3380 * up by the BIOS, and thus we can't get the mode at module
3381 * load.
3382 */
3383 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3384 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3385 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3386 }
3387 }
3388
intel_disable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3389 static void intel_disable_dp(struct intel_encoder *encoder,
3390 const struct intel_crtc_state *old_crtc_state,
3391 const struct drm_connector_state *old_conn_state)
3392 {
3393 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3394
3395 intel_dp->link_trained = false;
3396
3397 if (old_crtc_state->has_audio)
3398 intel_audio_codec_disable(encoder,
3399 old_crtc_state, old_conn_state);
3400
3401 /* Make sure the panel is off before trying to change the mode. But also
3402 * ensure that we have vdd while we switch off the panel. */
3403 intel_edp_panel_vdd_on(intel_dp);
3404 intel_edp_backlight_off(old_conn_state);
3405 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3406 intel_edp_panel_off(intel_dp);
3407 }
3408
g4x_disable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3409 static void g4x_disable_dp(struct intel_encoder *encoder,
3410 const struct intel_crtc_state *old_crtc_state,
3411 const struct drm_connector_state *old_conn_state)
3412 {
3413 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3414 }
3415
vlv_disable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3416 static void vlv_disable_dp(struct intel_encoder *encoder,
3417 const struct intel_crtc_state *old_crtc_state,
3418 const struct drm_connector_state *old_conn_state)
3419 {
3420 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3421 }
3422
g4x_post_disable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3423 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3424 const struct intel_crtc_state *old_crtc_state,
3425 const struct drm_connector_state *old_conn_state)
3426 {
3427 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3428 enum port port = encoder->port;
3429
3430 /*
3431 * Bspec does not list a specific disable sequence for g4x DP.
3432 * Follow the ilk+ sequence (disable pipe before the port) for
3433 * g4x DP as it does not suffer from underruns like the normal
3434 * g4x modeset sequence (disable pipe after the port).
3435 */
3436 intel_dp_link_down(encoder, old_crtc_state);
3437
3438 /* Only ilk+ has port A */
3439 if (port == PORT_A)
3440 ilk_edp_pll_off(intel_dp, old_crtc_state);
3441 }
3442
vlv_post_disable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3443 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3444 const struct intel_crtc_state *old_crtc_state,
3445 const struct drm_connector_state *old_conn_state)
3446 {
3447 intel_dp_link_down(encoder, old_crtc_state);
3448 }
3449
chv_post_disable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3450 static void chv_post_disable_dp(struct intel_encoder *encoder,
3451 const struct intel_crtc_state *old_crtc_state,
3452 const struct drm_connector_state *old_conn_state)
3453 {
3454 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3455
3456 intel_dp_link_down(encoder, old_crtc_state);
3457
3458 vlv_dpio_get(dev_priv);
3459
3460 /* Assert data lane reset */
3461 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3462
3463 vlv_dpio_put(dev_priv);
3464 }
3465
3466 static void
_intel_dp_set_link_train(struct intel_dp * intel_dp,u32 * DP,u8 dp_train_pat)3467 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3468 u32 *DP,
3469 u8 dp_train_pat)
3470 {
3471 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3472 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3473 enum port port = intel_dig_port->base.port;
3474 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3475
3476 if (dp_train_pat & train_pat_mask)
3477 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3478 dp_train_pat & train_pat_mask);
3479
3480 if (HAS_DDI(dev_priv)) {
3481 u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl);
3482
3483 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3484 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3485 else
3486 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3487
3488 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3489 switch (dp_train_pat & train_pat_mask) {
3490 case DP_TRAINING_PATTERN_DISABLE:
3491 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3492
3493 break;
3494 case DP_TRAINING_PATTERN_1:
3495 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3496 break;
3497 case DP_TRAINING_PATTERN_2:
3498 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3499 break;
3500 case DP_TRAINING_PATTERN_3:
3501 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3502 break;
3503 case DP_TRAINING_PATTERN_4:
3504 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3505 break;
3506 }
3507 I915_WRITE(intel_dp->regs.dp_tp_ctl, temp);
3508
3509 } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3510 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3511 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3512
3513 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3514 case DP_TRAINING_PATTERN_DISABLE:
3515 *DP |= DP_LINK_TRAIN_OFF_CPT;
3516 break;
3517 case DP_TRAINING_PATTERN_1:
3518 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3519 break;
3520 case DP_TRAINING_PATTERN_2:
3521 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3522 break;
3523 case DP_TRAINING_PATTERN_3:
3524 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3525 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3526 break;
3527 }
3528
3529 } else {
3530 *DP &= ~DP_LINK_TRAIN_MASK;
3531
3532 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3533 case DP_TRAINING_PATTERN_DISABLE:
3534 *DP |= DP_LINK_TRAIN_OFF;
3535 break;
3536 case DP_TRAINING_PATTERN_1:
3537 *DP |= DP_LINK_TRAIN_PAT_1;
3538 break;
3539 case DP_TRAINING_PATTERN_2:
3540 *DP |= DP_LINK_TRAIN_PAT_2;
3541 break;
3542 case DP_TRAINING_PATTERN_3:
3543 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3544 *DP |= DP_LINK_TRAIN_PAT_2;
3545 break;
3546 }
3547 }
3548 }
3549
intel_dp_enable_port(struct intel_dp * intel_dp,const struct intel_crtc_state * old_crtc_state)3550 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3551 const struct intel_crtc_state *old_crtc_state)
3552 {
3553 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3554
3555 /* enable with pattern 1 (as per spec) */
3556
3557 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3558
3559 /*
3560 * Magic for VLV/CHV. We _must_ first set up the register
3561 * without actually enabling the port, and then do another
3562 * write to enable the port. Otherwise link training will
3563 * fail when the power sequencer is freshly used for this port.
3564 */
3565 intel_dp->DP |= DP_PORT_EN;
3566 if (old_crtc_state->has_audio)
3567 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3568
3569 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3570 POSTING_READ(intel_dp->output_reg);
3571 }
3572
intel_enable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)3573 static void intel_enable_dp(struct intel_encoder *encoder,
3574 const struct intel_crtc_state *pipe_config,
3575 const struct drm_connector_state *conn_state)
3576 {
3577 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3578 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3579 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3580 u32 dp_reg = I915_READ(intel_dp->output_reg);
3581 enum pipe pipe = crtc->pipe;
3582 intel_wakeref_t wakeref;
3583
3584 if (WARN_ON(dp_reg & DP_PORT_EN))
3585 return;
3586
3587 with_pps_lock(intel_dp, wakeref) {
3588 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3589 vlv_init_panel_power_sequencer(encoder, pipe_config);
3590
3591 intel_dp_enable_port(intel_dp, pipe_config);
3592
3593 edp_panel_vdd_on(intel_dp);
3594 edp_panel_on(intel_dp);
3595 edp_panel_vdd_off(intel_dp, true);
3596 }
3597
3598 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3599 unsigned int lane_mask = 0x0;
3600
3601 if (IS_CHERRYVIEW(dev_priv))
3602 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3603
3604 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3605 lane_mask);
3606 }
3607
3608 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3609 intel_dp_start_link_train(intel_dp);
3610 intel_dp_stop_link_train(intel_dp);
3611
3612 if (pipe_config->has_audio) {
3613 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3614 pipe_name(pipe));
3615 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3616 }
3617 }
3618
g4x_enable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)3619 static void g4x_enable_dp(struct intel_encoder *encoder,
3620 const struct intel_crtc_state *pipe_config,
3621 const struct drm_connector_state *conn_state)
3622 {
3623 intel_enable_dp(encoder, pipe_config, conn_state);
3624 intel_edp_backlight_on(pipe_config, conn_state);
3625 }
3626
vlv_enable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)3627 static void vlv_enable_dp(struct intel_encoder *encoder,
3628 const struct intel_crtc_state *pipe_config,
3629 const struct drm_connector_state *conn_state)
3630 {
3631 intel_edp_backlight_on(pipe_config, conn_state);
3632 }
3633
g4x_pre_enable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)3634 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3635 const struct intel_crtc_state *pipe_config,
3636 const struct drm_connector_state *conn_state)
3637 {
3638 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3639 enum port port = encoder->port;
3640
3641 intel_dp_prepare(encoder, pipe_config);
3642
3643 /* Only ilk+ has port A */
3644 if (port == PORT_A)
3645 ilk_edp_pll_on(intel_dp, pipe_config);
3646 }
3647
vlv_detach_power_sequencer(struct intel_dp * intel_dp)3648 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3649 {
3650 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3651 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3652 enum pipe pipe = intel_dp->pps_pipe;
3653 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3654
3655 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3656
3657 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3658 return;
3659
3660 edp_panel_vdd_off_sync(intel_dp);
3661
3662 /*
3663 * VLV seems to get confused when multiple power sequencers
3664 * have the same port selected (even if only one has power/vdd
3665 * enabled). The failure manifests as vlv_wait_port_ready() failing
3666 * CHV on the other hand doesn't seem to mind having the same port
3667 * selected in multiple power sequencers, but let's clear the
3668 * port select always when logically disconnecting a power sequencer
3669 * from a port.
3670 */
3671 DRM_DEBUG_KMS("detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3672 pipe_name(pipe), intel_dig_port->base.base.base.id,
3673 intel_dig_port->base.base.name);
3674 I915_WRITE(pp_on_reg, 0);
3675 POSTING_READ(pp_on_reg);
3676
3677 intel_dp->pps_pipe = INVALID_PIPE;
3678 }
3679
vlv_steal_power_sequencer(struct drm_i915_private * dev_priv,enum pipe pipe)3680 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3681 enum pipe pipe)
3682 {
3683 struct intel_encoder *encoder;
3684
3685 lockdep_assert_held(&dev_priv->pps_mutex);
3686
3687 for_each_intel_dp(&dev_priv->drm, encoder) {
3688 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3689
3690 WARN(intel_dp->active_pipe == pipe,
3691 "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3692 pipe_name(pipe), encoder->base.base.id,
3693 encoder->base.name);
3694
3695 if (intel_dp->pps_pipe != pipe)
3696 continue;
3697
3698 DRM_DEBUG_KMS("stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3699 pipe_name(pipe), encoder->base.base.id,
3700 encoder->base.name);
3701
3702 /* make sure vdd is off before we steal it */
3703 vlv_detach_power_sequencer(intel_dp);
3704 }
3705 }
3706
vlv_init_panel_power_sequencer(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3707 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3708 const struct intel_crtc_state *crtc_state)
3709 {
3710 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3711 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3712 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3713
3714 lockdep_assert_held(&dev_priv->pps_mutex);
3715
3716 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3717
3718 if (intel_dp->pps_pipe != INVALID_PIPE &&
3719 intel_dp->pps_pipe != crtc->pipe) {
3720 /*
3721 * If another power sequencer was being used on this
3722 * port previously make sure to turn off vdd there while
3723 * we still have control of it.
3724 */
3725 vlv_detach_power_sequencer(intel_dp);
3726 }
3727
3728 /*
3729 * We may be stealing the power
3730 * sequencer from another port.
3731 */
3732 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3733
3734 intel_dp->active_pipe = crtc->pipe;
3735
3736 if (!intel_dp_is_edp(intel_dp))
3737 return;
3738
3739 /* now it's all ours */
3740 intel_dp->pps_pipe = crtc->pipe;
3741
3742 DRM_DEBUG_KMS("initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3743 pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3744 encoder->base.name);
3745
3746 /* init power sequencer on this pipe and port */
3747 intel_dp_init_panel_power_sequencer(intel_dp);
3748 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3749 }
3750
vlv_pre_enable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)3751 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3752 const struct intel_crtc_state *pipe_config,
3753 const struct drm_connector_state *conn_state)
3754 {
3755 vlv_phy_pre_encoder_enable(encoder, pipe_config);
3756
3757 intel_enable_dp(encoder, pipe_config, conn_state);
3758 }
3759
vlv_dp_pre_pll_enable(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)3760 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3761 const struct intel_crtc_state *pipe_config,
3762 const struct drm_connector_state *conn_state)
3763 {
3764 intel_dp_prepare(encoder, pipe_config);
3765
3766 vlv_phy_pre_pll_enable(encoder, pipe_config);
3767 }
3768
chv_pre_enable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)3769 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3770 const struct intel_crtc_state *pipe_config,
3771 const struct drm_connector_state *conn_state)
3772 {
3773 chv_phy_pre_encoder_enable(encoder, pipe_config);
3774
3775 intel_enable_dp(encoder, pipe_config, conn_state);
3776
3777 /* Second common lane will stay alive on its own now */
3778 chv_phy_release_cl2_override(encoder);
3779 }
3780
chv_dp_pre_pll_enable(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)3781 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3782 const struct intel_crtc_state *pipe_config,
3783 const struct drm_connector_state *conn_state)
3784 {
3785 intel_dp_prepare(encoder, pipe_config);
3786
3787 chv_phy_pre_pll_enable(encoder, pipe_config);
3788 }
3789
chv_dp_post_pll_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3790 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3791 const struct intel_crtc_state *old_crtc_state,
3792 const struct drm_connector_state *old_conn_state)
3793 {
3794 chv_phy_post_pll_disable(encoder, old_crtc_state);
3795 }
3796
3797 /*
3798 * Fetch AUX CH registers 0x202 - 0x207 which contain
3799 * link status information
3800 */
3801 bool
intel_dp_get_link_status(struct intel_dp * intel_dp,u8 link_status[DP_LINK_STATUS_SIZE])3802 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3803 {
3804 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3805 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3806 }
3807
3808 /* These are source-specific values. */
3809 u8
intel_dp_voltage_max(struct intel_dp * intel_dp)3810 intel_dp_voltage_max(struct intel_dp *intel_dp)
3811 {
3812 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3813 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3814 enum port port = encoder->port;
3815
3816 if (HAS_DDI(dev_priv))
3817 return intel_ddi_dp_voltage_max(encoder);
3818 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3819 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3820 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3821 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3822 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3823 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3824 else
3825 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3826 }
3827
3828 u8
intel_dp_pre_emphasis_max(struct intel_dp * intel_dp,u8 voltage_swing)3829 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3830 {
3831 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3832 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3833 enum port port = encoder->port;
3834
3835 if (HAS_DDI(dev_priv)) {
3836 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3837 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3838 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3839 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3840 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3841 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3842 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3843 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3844 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3845 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3846 default:
3847 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3848 }
3849 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3850 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3851 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3852 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3853 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3854 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3855 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3856 default:
3857 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3858 }
3859 } else {
3860 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3861 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3862 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3863 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3864 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3866 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3868 default:
3869 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3870 }
3871 }
3872 }
3873
vlv_signal_levels(struct intel_dp * intel_dp)3874 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3875 {
3876 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3877 unsigned long demph_reg_value, preemph_reg_value,
3878 uniqtranscale_reg_value;
3879 u8 train_set = intel_dp->train_set[0];
3880
3881 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3882 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3883 preemph_reg_value = 0x0004000;
3884 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3885 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3886 demph_reg_value = 0x2B405555;
3887 uniqtranscale_reg_value = 0x552AB83A;
3888 break;
3889 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3890 demph_reg_value = 0x2B404040;
3891 uniqtranscale_reg_value = 0x5548B83A;
3892 break;
3893 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3894 demph_reg_value = 0x2B245555;
3895 uniqtranscale_reg_value = 0x5560B83A;
3896 break;
3897 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3898 demph_reg_value = 0x2B405555;
3899 uniqtranscale_reg_value = 0x5598DA3A;
3900 break;
3901 default:
3902 return 0;
3903 }
3904 break;
3905 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3906 preemph_reg_value = 0x0002000;
3907 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3908 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3909 demph_reg_value = 0x2B404040;
3910 uniqtranscale_reg_value = 0x5552B83A;
3911 break;
3912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3913 demph_reg_value = 0x2B404848;
3914 uniqtranscale_reg_value = 0x5580B83A;
3915 break;
3916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3917 demph_reg_value = 0x2B404040;
3918 uniqtranscale_reg_value = 0x55ADDA3A;
3919 break;
3920 default:
3921 return 0;
3922 }
3923 break;
3924 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3925 preemph_reg_value = 0x0000000;
3926 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3928 demph_reg_value = 0x2B305555;
3929 uniqtranscale_reg_value = 0x5570B83A;
3930 break;
3931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3932 demph_reg_value = 0x2B2B4040;
3933 uniqtranscale_reg_value = 0x55ADDA3A;
3934 break;
3935 default:
3936 return 0;
3937 }
3938 break;
3939 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3940 preemph_reg_value = 0x0006000;
3941 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3942 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3943 demph_reg_value = 0x1B405555;
3944 uniqtranscale_reg_value = 0x55ADDA3A;
3945 break;
3946 default:
3947 return 0;
3948 }
3949 break;
3950 default:
3951 return 0;
3952 }
3953
3954 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3955 uniqtranscale_reg_value, 0);
3956
3957 return 0;
3958 }
3959
chv_signal_levels(struct intel_dp * intel_dp)3960 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3961 {
3962 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3963 u32 deemph_reg_value, margin_reg_value;
3964 bool uniq_trans_scale = false;
3965 u8 train_set = intel_dp->train_set[0];
3966
3967 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3968 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3969 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3971 deemph_reg_value = 128;
3972 margin_reg_value = 52;
3973 break;
3974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3975 deemph_reg_value = 128;
3976 margin_reg_value = 77;
3977 break;
3978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3979 deemph_reg_value = 128;
3980 margin_reg_value = 102;
3981 break;
3982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3983 deemph_reg_value = 128;
3984 margin_reg_value = 154;
3985 uniq_trans_scale = true;
3986 break;
3987 default:
3988 return 0;
3989 }
3990 break;
3991 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3992 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3993 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3994 deemph_reg_value = 85;
3995 margin_reg_value = 78;
3996 break;
3997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3998 deemph_reg_value = 85;
3999 margin_reg_value = 116;
4000 break;
4001 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4002 deemph_reg_value = 85;
4003 margin_reg_value = 154;
4004 break;
4005 default:
4006 return 0;
4007 }
4008 break;
4009 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4010 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4012 deemph_reg_value = 64;
4013 margin_reg_value = 104;
4014 break;
4015 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4016 deemph_reg_value = 64;
4017 margin_reg_value = 154;
4018 break;
4019 default:
4020 return 0;
4021 }
4022 break;
4023 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4024 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4026 deemph_reg_value = 43;
4027 margin_reg_value = 154;
4028 break;
4029 default:
4030 return 0;
4031 }
4032 break;
4033 default:
4034 return 0;
4035 }
4036
4037 chv_set_phy_signal_level(encoder, deemph_reg_value,
4038 margin_reg_value, uniq_trans_scale);
4039
4040 return 0;
4041 }
4042
4043 static u32
g4x_signal_levels(u8 train_set)4044 g4x_signal_levels(u8 train_set)
4045 {
4046 u32 signal_levels = 0;
4047
4048 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4050 default:
4051 signal_levels |= DP_VOLTAGE_0_4;
4052 break;
4053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4054 signal_levels |= DP_VOLTAGE_0_6;
4055 break;
4056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4057 signal_levels |= DP_VOLTAGE_0_8;
4058 break;
4059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4060 signal_levels |= DP_VOLTAGE_1_2;
4061 break;
4062 }
4063 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4064 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4065 default:
4066 signal_levels |= DP_PRE_EMPHASIS_0;
4067 break;
4068 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4069 signal_levels |= DP_PRE_EMPHASIS_3_5;
4070 break;
4071 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4072 signal_levels |= DP_PRE_EMPHASIS_6;
4073 break;
4074 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4075 signal_levels |= DP_PRE_EMPHASIS_9_5;
4076 break;
4077 }
4078 return signal_levels;
4079 }
4080
4081 /* SNB CPU eDP voltage swing and pre-emphasis control */
4082 static u32
snb_cpu_edp_signal_levels(u8 train_set)4083 snb_cpu_edp_signal_levels(u8 train_set)
4084 {
4085 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4086 DP_TRAIN_PRE_EMPHASIS_MASK);
4087 switch (signal_levels) {
4088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4090 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4092 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4095 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4098 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4099 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4101 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4102 default:
4103 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4104 "0x%x\n", signal_levels);
4105 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4106 }
4107 }
4108
4109 /* IVB CPU eDP voltage swing and pre-emphasis control */
4110 static u32
ivb_cpu_edp_signal_levels(u8 train_set)4111 ivb_cpu_edp_signal_levels(u8 train_set)
4112 {
4113 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4114 DP_TRAIN_PRE_EMPHASIS_MASK);
4115 switch (signal_levels) {
4116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4117 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4118 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4119 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4121 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4122
4123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4124 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4126 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4127
4128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4129 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4131 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4132
4133 default:
4134 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4135 "0x%x\n", signal_levels);
4136 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4137 }
4138 }
4139
4140 void
intel_dp_set_signal_levels(struct intel_dp * intel_dp)4141 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4142 {
4143 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4145 enum port port = intel_dig_port->base.port;
4146 u32 signal_levels, mask = 0;
4147 u8 train_set = intel_dp->train_set[0];
4148
4149 if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
4150 signal_levels = bxt_signal_levels(intel_dp);
4151 } else if (HAS_DDI(dev_priv)) {
4152 signal_levels = ddi_signal_levels(intel_dp);
4153 mask = DDI_BUF_EMP_MASK;
4154 } else if (IS_CHERRYVIEW(dev_priv)) {
4155 signal_levels = chv_signal_levels(intel_dp);
4156 } else if (IS_VALLEYVIEW(dev_priv)) {
4157 signal_levels = vlv_signal_levels(intel_dp);
4158 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4159 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4160 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4161 } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
4162 signal_levels = snb_cpu_edp_signal_levels(train_set);
4163 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4164 } else {
4165 signal_levels = g4x_signal_levels(train_set);
4166 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
4167 }
4168
4169 if (mask)
4170 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
4171
4172 DRM_DEBUG_KMS("Using vswing level %d\n",
4173 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
4174 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
4175 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4176 DP_TRAIN_PRE_EMPHASIS_SHIFT);
4177
4178 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
4179
4180 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4181 POSTING_READ(intel_dp->output_reg);
4182 }
4183
4184 void
intel_dp_program_link_training_pattern(struct intel_dp * intel_dp,u8 dp_train_pat)4185 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4186 u8 dp_train_pat)
4187 {
4188 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4189 struct drm_i915_private *dev_priv =
4190 to_i915(intel_dig_port->base.base.dev);
4191
4192 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
4193
4194 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4195 POSTING_READ(intel_dp->output_reg);
4196 }
4197
intel_dp_set_idle_link_train(struct intel_dp * intel_dp)4198 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4199 {
4200 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4201 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4202 enum port port = intel_dig_port->base.port;
4203 u32 val;
4204
4205 if (!HAS_DDI(dev_priv))
4206 return;
4207
4208 val = I915_READ(intel_dp->regs.dp_tp_ctl);
4209 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4210 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4211 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
4212
4213 /*
4214 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4215 * reason we need to set idle transmission mode is to work around a HW
4216 * issue where we enable the pipe while not in idle link-training mode.
4217 * In this case there is requirement to wait for a minimum number of
4218 * idle patterns to be sent.
4219 */
4220 if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4221 return;
4222
4223 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4224 DP_TP_STATUS_IDLE_DONE, 1))
4225 DRM_ERROR("Timed out waiting for DP idle patterns\n");
4226 }
4227
4228 static void
intel_dp_link_down(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state)4229 intel_dp_link_down(struct intel_encoder *encoder,
4230 const struct intel_crtc_state *old_crtc_state)
4231 {
4232 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4233 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4234 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4235 enum port port = encoder->port;
4236 u32 DP = intel_dp->DP;
4237
4238 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
4239 return;
4240
4241 DRM_DEBUG_KMS("\n");
4242
4243 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4244 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4245 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4246 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4247 } else {
4248 DP &= ~DP_LINK_TRAIN_MASK;
4249 DP |= DP_LINK_TRAIN_PAT_IDLE;
4250 }
4251 I915_WRITE(intel_dp->output_reg, DP);
4252 POSTING_READ(intel_dp->output_reg);
4253
4254 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4255 I915_WRITE(intel_dp->output_reg, DP);
4256 POSTING_READ(intel_dp->output_reg);
4257
4258 /*
4259 * HW workaround for IBX, we need to move the port
4260 * to transcoder A after disabling it to allow the
4261 * matching HDMI port to be enabled on transcoder A.
4262 */
4263 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4264 /*
4265 * We get CPU/PCH FIFO underruns on the other pipe when
4266 * doing the workaround. Sweep them under the rug.
4267 */
4268 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4269 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4270
4271 /* always enable with pattern 1 (as per spec) */
4272 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4273 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4274 DP_LINK_TRAIN_PAT_1;
4275 I915_WRITE(intel_dp->output_reg, DP);
4276 POSTING_READ(intel_dp->output_reg);
4277
4278 DP &= ~DP_PORT_EN;
4279 I915_WRITE(intel_dp->output_reg, DP);
4280 POSTING_READ(intel_dp->output_reg);
4281
4282 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4283 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4284 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4285 }
4286
4287 msleep(intel_dp->panel_power_down_delay);
4288
4289 intel_dp->DP = DP;
4290
4291 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4292 intel_wakeref_t wakeref;
4293
4294 with_pps_lock(intel_dp, wakeref)
4295 intel_dp->active_pipe = INVALID_PIPE;
4296 }
4297 }
4298
4299 static void
intel_dp_extended_receiver_capabilities(struct intel_dp * intel_dp)4300 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4301 {
4302 u8 dpcd_ext[6];
4303
4304 /*
4305 * Prior to DP1.3 the bit represented by
4306 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4307 * if it is set DP_DPCD_REV at 0000h could be at a value less than
4308 * the true capability of the panel. The only way to check is to
4309 * then compare 0000h and 2200h.
4310 */
4311 if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4312 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4313 return;
4314
4315 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4316 &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4317 DRM_ERROR("DPCD failed read at extended capabilities\n");
4318 return;
4319 }
4320
4321 if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4322 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4323 return;
4324 }
4325
4326 if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4327 return;
4328
4329 DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4330 (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4331
4332 memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4333 }
4334
4335 bool
intel_dp_read_dpcd(struct intel_dp * intel_dp)4336 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4337 {
4338 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4339 sizeof(intel_dp->dpcd)) < 0)
4340 return false; /* aux transfer failed */
4341
4342 intel_dp_extended_receiver_capabilities(intel_dp);
4343
4344 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4345
4346 return intel_dp->dpcd[DP_DPCD_REV] != 0;
4347 }
4348
intel_dp_get_colorimetry_status(struct intel_dp * intel_dp)4349 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4350 {
4351 u8 dprx = 0;
4352
4353 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4354 &dprx) != 1)
4355 return false;
4356 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4357 }
4358
intel_dp_get_dsc_sink_cap(struct intel_dp * intel_dp)4359 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4360 {
4361 /*
4362 * Clear the cached register set to avoid using stale values
4363 * for the sinks that do not support DSC.
4364 */
4365 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4366
4367 /* Clear fec_capable to avoid using stale values */
4368 intel_dp->fec_capable = 0;
4369
4370 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4371 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4372 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4373 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4374 intel_dp->dsc_dpcd,
4375 sizeof(intel_dp->dsc_dpcd)) < 0)
4376 DRM_ERROR("Failed to read DPCD register 0x%x\n",
4377 DP_DSC_SUPPORT);
4378
4379 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4380 (int)sizeof(intel_dp->dsc_dpcd),
4381 intel_dp->dsc_dpcd);
4382
4383 /* FEC is supported only on DP 1.4 */
4384 if (!intel_dp_is_edp(intel_dp) &&
4385 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4386 &intel_dp->fec_capable) < 0)
4387 DRM_ERROR("Failed to read FEC DPCD register\n");
4388
4389 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4390 }
4391 }
4392
4393 static bool
intel_edp_init_dpcd(struct intel_dp * intel_dp)4394 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4395 {
4396 struct drm_i915_private *dev_priv =
4397 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4398
4399 /* this function is meant to be called only once */
4400 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4401
4402 if (!intel_dp_read_dpcd(intel_dp))
4403 return false;
4404
4405 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4406 drm_dp_is_branch(intel_dp->dpcd));
4407
4408 /*
4409 * Read the eDP display control registers.
4410 *
4411 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4412 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4413 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4414 * method). The display control registers should read zero if they're
4415 * not supported anyway.
4416 */
4417 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4418 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4419 sizeof(intel_dp->edp_dpcd))
4420 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4421 intel_dp->edp_dpcd);
4422
4423 /*
4424 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4425 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4426 */
4427 intel_psr_init_dpcd(intel_dp);
4428
4429 /* Read the eDP 1.4+ supported link rates. */
4430 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4431 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4432 int i;
4433
4434 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4435 sink_rates, sizeof(sink_rates));
4436
4437 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4438 int val = le16_to_cpu(sink_rates[i]);
4439
4440 if (val == 0)
4441 break;
4442
4443 /* Value read multiplied by 200kHz gives the per-lane
4444 * link rate in kHz. The source rates are, however,
4445 * stored in terms of LS_Clk kHz. The full conversion
4446 * back to symbols is
4447 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4448 */
4449 intel_dp->sink_rates[i] = (val * 200) / 10;
4450 }
4451 intel_dp->num_sink_rates = i;
4452 }
4453
4454 /*
4455 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4456 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4457 */
4458 if (intel_dp->num_sink_rates)
4459 intel_dp->use_rate_select = true;
4460 else
4461 intel_dp_set_sink_rates(intel_dp);
4462
4463 intel_dp_set_common_rates(intel_dp);
4464
4465 /* Read the eDP DSC DPCD registers */
4466 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4467 intel_dp_get_dsc_sink_cap(intel_dp);
4468
4469 return true;
4470 }
4471
4472
4473 static bool
intel_dp_get_dpcd(struct intel_dp * intel_dp)4474 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4475 {
4476 if (!intel_dp_read_dpcd(intel_dp))
4477 return false;
4478
4479 /*
4480 * Don't clobber cached eDP rates. Also skip re-reading
4481 * the OUI/ID since we know it won't change.
4482 */
4483 if (!intel_dp_is_edp(intel_dp)) {
4484 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4485 drm_dp_is_branch(intel_dp->dpcd));
4486
4487 intel_dp_set_sink_rates(intel_dp);
4488 intel_dp_set_common_rates(intel_dp);
4489 }
4490
4491 /*
4492 * Some eDP panels do not set a valid value for sink count, that is why
4493 * it don't care about read it here and in intel_edp_init_dpcd().
4494 */
4495 if (!intel_dp_is_edp(intel_dp) &&
4496 !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4497 u8 count;
4498 ssize_t r;
4499
4500 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4501 if (r < 1)
4502 return false;
4503
4504 /*
4505 * Sink count can change between short pulse hpd hence
4506 * a member variable in intel_dp will track any changes
4507 * between short pulse interrupts.
4508 */
4509 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4510
4511 /*
4512 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4513 * a dongle is present but no display. Unless we require to know
4514 * if a dongle is present or not, we don't need to update
4515 * downstream port information. So, an early return here saves
4516 * time from performing other operations which are not required.
4517 */
4518 if (!intel_dp->sink_count)
4519 return false;
4520 }
4521
4522 if (!drm_dp_is_branch(intel_dp->dpcd))
4523 return true; /* native DP sink */
4524
4525 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4526 return true; /* no per-port downstream info */
4527
4528 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4529 intel_dp->downstream_ports,
4530 DP_MAX_DOWNSTREAM_PORTS) < 0)
4531 return false; /* downstream port status fetch failed */
4532
4533 return true;
4534 }
4535
4536 static bool
intel_dp_sink_can_mst(struct intel_dp * intel_dp)4537 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4538 {
4539 u8 mstm_cap;
4540
4541 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4542 return false;
4543
4544 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4545 return false;
4546
4547 return mstm_cap & DP_MST_CAP;
4548 }
4549
4550 static bool
intel_dp_can_mst(struct intel_dp * intel_dp)4551 intel_dp_can_mst(struct intel_dp *intel_dp)
4552 {
4553 return i915_modparams.enable_dp_mst &&
4554 intel_dp->can_mst &&
4555 intel_dp_sink_can_mst(intel_dp);
4556 }
4557
4558 static void
intel_dp_configure_mst(struct intel_dp * intel_dp)4559 intel_dp_configure_mst(struct intel_dp *intel_dp)
4560 {
4561 struct intel_encoder *encoder =
4562 &dp_to_dig_port(intel_dp)->base;
4563 bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4564
4565 DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4566 encoder->base.base.id, encoder->base.name,
4567 yesno(intel_dp->can_mst), yesno(sink_can_mst),
4568 yesno(i915_modparams.enable_dp_mst));
4569
4570 if (!intel_dp->can_mst)
4571 return;
4572
4573 intel_dp->is_mst = sink_can_mst &&
4574 i915_modparams.enable_dp_mst;
4575
4576 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4577 intel_dp->is_mst);
4578 }
4579
4580 static bool
intel_dp_get_sink_irq_esi(struct intel_dp * intel_dp,u8 * sink_irq_vector)4581 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4582 {
4583 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4584 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4585 DP_DPRX_ESI_LEN;
4586 }
4587
4588 bool
intel_dp_needs_vsc_sdp(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4589 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4590 const struct drm_connector_state *conn_state)
4591 {
4592 /*
4593 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4594 * of Color Encoding Format and Content Color Gamut], in order to
4595 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4596 */
4597 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4598 return true;
4599
4600 switch (conn_state->colorspace) {
4601 case DRM_MODE_COLORIMETRY_SYCC_601:
4602 case DRM_MODE_COLORIMETRY_OPYCC_601:
4603 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4604 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4605 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4606 return true;
4607 default:
4608 break;
4609 }
4610
4611 return false;
4612 }
4613
4614 static void
intel_dp_setup_vsc_sdp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4615 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
4616 const struct intel_crtc_state *crtc_state,
4617 const struct drm_connector_state *conn_state)
4618 {
4619 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4620 struct dp_sdp vsc_sdp = {};
4621
4622 /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
4623 vsc_sdp.sdp_header.HB0 = 0;
4624 vsc_sdp.sdp_header.HB1 = 0x7;
4625
4626 /*
4627 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
4628 * Colorimetry Format indication.
4629 */
4630 vsc_sdp.sdp_header.HB2 = 0x5;
4631
4632 /*
4633 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
4634 * Colorimetry Format indication (HB2 = 05h).
4635 */
4636 vsc_sdp.sdp_header.HB3 = 0x13;
4637
4638 /* DP 1.4a spec, Table 2-120 */
4639 switch (crtc_state->output_format) {
4640 case INTEL_OUTPUT_FORMAT_YCBCR444:
4641 vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
4642 break;
4643 case INTEL_OUTPUT_FORMAT_YCBCR420:
4644 vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
4645 break;
4646 case INTEL_OUTPUT_FORMAT_RGB:
4647 default:
4648 /* RGB: DB16[7:4] = 0h */
4649 break;
4650 }
4651
4652 switch (conn_state->colorspace) {
4653 case DRM_MODE_COLORIMETRY_BT709_YCC:
4654 vsc_sdp.db[16] |= 0x1;
4655 break;
4656 case DRM_MODE_COLORIMETRY_XVYCC_601:
4657 vsc_sdp.db[16] |= 0x2;
4658 break;
4659 case DRM_MODE_COLORIMETRY_XVYCC_709:
4660 vsc_sdp.db[16] |= 0x3;
4661 break;
4662 case DRM_MODE_COLORIMETRY_SYCC_601:
4663 vsc_sdp.db[16] |= 0x4;
4664 break;
4665 case DRM_MODE_COLORIMETRY_OPYCC_601:
4666 vsc_sdp.db[16] |= 0x5;
4667 break;
4668 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4669 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4670 vsc_sdp.db[16] |= 0x6;
4671 break;
4672 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4673 vsc_sdp.db[16] |= 0x7;
4674 break;
4675 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
4676 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
4677 vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
4678 break;
4679 default:
4680 /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
4681
4682 /* RGB->YCBCR color conversion uses the BT.709 color space. */
4683 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4684 vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
4685 break;
4686 }
4687
4688 /*
4689 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
4690 * the following Component Bit Depth values are defined:
4691 * 001b = 8bpc.
4692 * 010b = 10bpc.
4693 * 011b = 12bpc.
4694 * 100b = 16bpc.
4695 */
4696 switch (crtc_state->pipe_bpp) {
4697 case 24: /* 8bpc */
4698 vsc_sdp.db[17] = 0x1;
4699 break;
4700 case 30: /* 10bpc */
4701 vsc_sdp.db[17] = 0x2;
4702 break;
4703 case 36: /* 12bpc */
4704 vsc_sdp.db[17] = 0x3;
4705 break;
4706 case 48: /* 16bpc */
4707 vsc_sdp.db[17] = 0x4;
4708 break;
4709 default:
4710 MISSING_CASE(crtc_state->pipe_bpp);
4711 break;
4712 }
4713
4714 /*
4715 * Dynamic Range (Bit 7)
4716 * 0 = VESA range, 1 = CTA range.
4717 * all YCbCr are always limited range
4718 */
4719 vsc_sdp.db[17] |= 0x80;
4720
4721 /*
4722 * Content Type (Bits 2:0)
4723 * 000b = Not defined.
4724 * 001b = Graphics.
4725 * 010b = Photo.
4726 * 011b = Video.
4727 * 100b = Game
4728 * All other values are RESERVED.
4729 * Note: See CTA-861-G for the definition and expected
4730 * processing by a stream sink for the above contect types.
4731 */
4732 vsc_sdp.db[18] = 0;
4733
4734 intel_dig_port->write_infoframe(&intel_dig_port->base,
4735 crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
4736 }
4737
4738 static void
intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4739 intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
4740 const struct intel_crtc_state *crtc_state,
4741 const struct drm_connector_state *conn_state)
4742 {
4743 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4744 struct dp_sdp infoframe_sdp = {};
4745 struct hdmi_drm_infoframe drm_infoframe = {};
4746 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4747 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4748 ssize_t len;
4749 int ret;
4750
4751 ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
4752 if (ret) {
4753 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
4754 return;
4755 }
4756
4757 len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
4758 if (len < 0) {
4759 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
4760 return;
4761 }
4762
4763 if (len != infoframe_size) {
4764 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
4765 return;
4766 }
4767
4768 /*
4769 * Set up the infoframe sdp packet for HDR static metadata.
4770 * Prepare VSC Header for SU as per DP 1.4a spec,
4771 * Table 2-100 and Table 2-101
4772 */
4773
4774 /* Packet ID, 00h for non-Audio INFOFRAME */
4775 infoframe_sdp.sdp_header.HB0 = 0;
4776 /*
4777 * Packet Type 80h + Non-audio INFOFRAME Type value
4778 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
4779 */
4780 infoframe_sdp.sdp_header.HB1 = drm_infoframe.header.type;
4781 /*
4782 * Least Significant Eight Bits of (Data Byte Count – 1)
4783 * infoframe_size - 1,
4784 */
4785 infoframe_sdp.sdp_header.HB2 = 0x1D;
4786 /* INFOFRAME SDP Version Number */
4787 infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
4788 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4789 infoframe_sdp.db[0] = drm_infoframe.header.version;
4790 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4791 infoframe_sdp.db[1] = drm_infoframe.header.length;
4792 /*
4793 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4794 * HDMI_INFOFRAME_HEADER_SIZE
4795 */
4796 BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4797 memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4798 HDMI_DRM_INFOFRAME_SIZE);
4799
4800 /*
4801 * Size of DP infoframe sdp packet for HDR static metadata is consist of
4802 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4803 * - Two Data Blocks: 2 bytes
4804 * CTA Header Byte2 (INFOFRAME Version Number)
4805 * CTA Header Byte3 (Length of INFOFRAME)
4806 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4807 *
4808 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4809 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4810 * will pad rest of the size.
4811 */
4812 intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
4813 HDMI_PACKET_TYPE_GAMUT_METADATA,
4814 &infoframe_sdp,
4815 sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
4816 }
4817
intel_dp_vsc_enable(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4818 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
4819 const struct intel_crtc_state *crtc_state,
4820 const struct drm_connector_state *conn_state)
4821 {
4822 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
4823 return;
4824
4825 intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
4826 }
4827
intel_dp_hdr_metadata_enable(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4828 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
4829 const struct intel_crtc_state *crtc_state,
4830 const struct drm_connector_state *conn_state)
4831 {
4832 if (!conn_state->hdr_output_metadata)
4833 return;
4834
4835 intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
4836 crtc_state,
4837 conn_state);
4838 }
4839
intel_dp_autotest_link_training(struct intel_dp * intel_dp)4840 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4841 {
4842 int status = 0;
4843 int test_link_rate;
4844 u8 test_lane_count, test_link_bw;
4845 /* (DP CTS 1.2)
4846 * 4.3.1.11
4847 */
4848 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4849 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4850 &test_lane_count);
4851
4852 if (status <= 0) {
4853 DRM_DEBUG_KMS("Lane count read failed\n");
4854 return DP_TEST_NAK;
4855 }
4856 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4857
4858 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4859 &test_link_bw);
4860 if (status <= 0) {
4861 DRM_DEBUG_KMS("Link Rate read failed\n");
4862 return DP_TEST_NAK;
4863 }
4864 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4865
4866 /* Validate the requested link rate and lane count */
4867 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4868 test_lane_count))
4869 return DP_TEST_NAK;
4870
4871 intel_dp->compliance.test_lane_count = test_lane_count;
4872 intel_dp->compliance.test_link_rate = test_link_rate;
4873
4874 return DP_TEST_ACK;
4875 }
4876
intel_dp_autotest_video_pattern(struct intel_dp * intel_dp)4877 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4878 {
4879 u8 test_pattern;
4880 u8 test_misc;
4881 __be16 h_width, v_height;
4882 int status = 0;
4883
4884 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4885 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4886 &test_pattern);
4887 if (status <= 0) {
4888 DRM_DEBUG_KMS("Test pattern read failed\n");
4889 return DP_TEST_NAK;
4890 }
4891 if (test_pattern != DP_COLOR_RAMP)
4892 return DP_TEST_NAK;
4893
4894 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4895 &h_width, 2);
4896 if (status <= 0) {
4897 DRM_DEBUG_KMS("H Width read failed\n");
4898 return DP_TEST_NAK;
4899 }
4900
4901 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4902 &v_height, 2);
4903 if (status <= 0) {
4904 DRM_DEBUG_KMS("V Height read failed\n");
4905 return DP_TEST_NAK;
4906 }
4907
4908 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4909 &test_misc);
4910 if (status <= 0) {
4911 DRM_DEBUG_KMS("TEST MISC read failed\n");
4912 return DP_TEST_NAK;
4913 }
4914 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4915 return DP_TEST_NAK;
4916 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4917 return DP_TEST_NAK;
4918 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4919 case DP_TEST_BIT_DEPTH_6:
4920 intel_dp->compliance.test_data.bpc = 6;
4921 break;
4922 case DP_TEST_BIT_DEPTH_8:
4923 intel_dp->compliance.test_data.bpc = 8;
4924 break;
4925 default:
4926 return DP_TEST_NAK;
4927 }
4928
4929 intel_dp->compliance.test_data.video_pattern = test_pattern;
4930 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4931 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4932 /* Set test active flag here so userspace doesn't interrupt things */
4933 intel_dp->compliance.test_active = true;
4934
4935 return DP_TEST_ACK;
4936 }
4937
intel_dp_autotest_edid(struct intel_dp * intel_dp)4938 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4939 {
4940 u8 test_result = DP_TEST_ACK;
4941 struct intel_connector *intel_connector = intel_dp->attached_connector;
4942 struct drm_connector *connector = &intel_connector->base;
4943
4944 if (intel_connector->detect_edid == NULL ||
4945 connector->edid_corrupt ||
4946 intel_dp->aux.i2c_defer_count > 6) {
4947 /* Check EDID read for NACKs, DEFERs and corruption
4948 * (DP CTS 1.2 Core r1.1)
4949 * 4.2.2.4 : Failed EDID read, I2C_NAK
4950 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4951 * 4.2.2.6 : EDID corruption detected
4952 * Use failsafe mode for all cases
4953 */
4954 if (intel_dp->aux.i2c_nack_count > 0 ||
4955 intel_dp->aux.i2c_defer_count > 0)
4956 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4957 intel_dp->aux.i2c_nack_count,
4958 intel_dp->aux.i2c_defer_count);
4959 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4960 } else {
4961 struct edid *block = intel_connector->detect_edid;
4962
4963 /* We have to write the checksum
4964 * of the last block read
4965 */
4966 block += intel_connector->detect_edid->extensions;
4967
4968 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4969 block->checksum) <= 0)
4970 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4971
4972 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4973 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4974 }
4975
4976 /* Set test active flag here so userspace doesn't interrupt things */
4977 intel_dp->compliance.test_active = true;
4978
4979 return test_result;
4980 }
4981
intel_dp_autotest_phy_pattern(struct intel_dp * intel_dp)4982 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4983 {
4984 u8 test_result = DP_TEST_NAK;
4985 return test_result;
4986 }
4987
intel_dp_handle_test_request(struct intel_dp * intel_dp)4988 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4989 {
4990 u8 response = DP_TEST_NAK;
4991 u8 request = 0;
4992 int status;
4993
4994 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4995 if (status <= 0) {
4996 DRM_DEBUG_KMS("Could not read test request from sink\n");
4997 goto update_status;
4998 }
4999
5000 switch (request) {
5001 case DP_TEST_LINK_TRAINING:
5002 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
5003 response = intel_dp_autotest_link_training(intel_dp);
5004 break;
5005 case DP_TEST_LINK_VIDEO_PATTERN:
5006 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
5007 response = intel_dp_autotest_video_pattern(intel_dp);
5008 break;
5009 case DP_TEST_LINK_EDID_READ:
5010 DRM_DEBUG_KMS("EDID test requested\n");
5011 response = intel_dp_autotest_edid(intel_dp);
5012 break;
5013 case DP_TEST_LINK_PHY_TEST_PATTERN:
5014 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
5015 response = intel_dp_autotest_phy_pattern(intel_dp);
5016 break;
5017 default:
5018 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
5019 break;
5020 }
5021
5022 if (response & DP_TEST_ACK)
5023 intel_dp->compliance.test_type = request;
5024
5025 update_status:
5026 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5027 if (status <= 0)
5028 DRM_DEBUG_KMS("Could not write test response to sink\n");
5029 }
5030
5031 static int
intel_dp_check_mst_status(struct intel_dp * intel_dp)5032 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5033 {
5034 bool bret;
5035
5036 if (intel_dp->is_mst) {
5037 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
5038 int ret = 0;
5039 int retry;
5040 bool handled;
5041
5042 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
5043 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5044 go_again:
5045 if (bret == true) {
5046
5047 /* check link status - esi[10] = 0x200c */
5048 if (intel_dp->active_mst_links > 0 &&
5049 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5050 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
5051 intel_dp_start_link_train(intel_dp);
5052 intel_dp_stop_link_train(intel_dp);
5053 }
5054
5055 DRM_DEBUG_KMS("got esi %3ph\n", esi);
5056 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5057
5058 if (handled) {
5059 for (retry = 0; retry < 3; retry++) {
5060 int wret;
5061 wret = drm_dp_dpcd_write(&intel_dp->aux,
5062 DP_SINK_COUNT_ESI+1,
5063 &esi[1], 3);
5064 if (wret == 3) {
5065 break;
5066 }
5067 }
5068
5069 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5070 if (bret == true) {
5071 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
5072 goto go_again;
5073 }
5074 } else
5075 ret = 0;
5076
5077 return ret;
5078 } else {
5079 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
5080 intel_dp->is_mst = false;
5081 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5082 intel_dp->is_mst);
5083 }
5084 }
5085 return -EINVAL;
5086 }
5087
5088 static bool
intel_dp_needs_link_retrain(struct intel_dp * intel_dp)5089 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5090 {
5091 u8 link_status[DP_LINK_STATUS_SIZE];
5092
5093 if (!intel_dp->link_trained)
5094 return false;
5095
5096 /*
5097 * While PSR source HW is enabled, it will control main-link sending
5098 * frames, enabling and disabling it so trying to do a retrain will fail
5099 * as the link would or not be on or it could mix training patterns
5100 * and frame data at the same time causing retrain to fail.
5101 * Also when exiting PSR, HW will retrain the link anyways fixing
5102 * any link status error.
5103 */
5104 if (intel_psr_enabled(intel_dp))
5105 return false;
5106
5107 if (!intel_dp_get_link_status(intel_dp, link_status))
5108 return false;
5109
5110 /*
5111 * Validate the cached values of intel_dp->link_rate and
5112 * intel_dp->lane_count before attempting to retrain.
5113 */
5114 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5115 intel_dp->lane_count))
5116 return false;
5117
5118 /* Retrain if Channel EQ or CR not ok */
5119 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5120 }
5121
intel_dp_retrain_link(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)5122 int intel_dp_retrain_link(struct intel_encoder *encoder,
5123 struct drm_modeset_acquire_ctx *ctx)
5124 {
5125 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5126 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5127 struct intel_connector *connector = intel_dp->attached_connector;
5128 struct drm_connector_state *conn_state;
5129 struct intel_crtc_state *crtc_state;
5130 struct intel_crtc *crtc;
5131 int ret;
5132
5133 /* FIXME handle the MST connectors as well */
5134
5135 if (!connector || connector->base.status != connector_status_connected)
5136 return 0;
5137
5138 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5139 ctx);
5140 if (ret)
5141 return ret;
5142
5143 conn_state = connector->base.state;
5144
5145 crtc = to_intel_crtc(conn_state->crtc);
5146 if (!crtc)
5147 return 0;
5148
5149 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5150 if (ret)
5151 return ret;
5152
5153 crtc_state = to_intel_crtc_state(crtc->base.state);
5154
5155 WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
5156
5157 if (!crtc_state->hw.active)
5158 return 0;
5159
5160 if (conn_state->commit &&
5161 !try_wait_for_completion(&conn_state->commit->hw_done))
5162 return 0;
5163
5164 if (!intel_dp_needs_link_retrain(intel_dp))
5165 return 0;
5166
5167 /* Suppress underruns caused by re-training */
5168 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5169 if (crtc_state->has_pch_encoder)
5170 intel_set_pch_fifo_underrun_reporting(dev_priv,
5171 intel_crtc_pch_transcoder(crtc), false);
5172
5173 intel_dp_start_link_train(intel_dp);
5174 intel_dp_stop_link_train(intel_dp);
5175
5176 /* Keep underrun reporting disabled until things are stable */
5177 intel_wait_for_vblank(dev_priv, crtc->pipe);
5178
5179 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5180 if (crtc_state->has_pch_encoder)
5181 intel_set_pch_fifo_underrun_reporting(dev_priv,
5182 intel_crtc_pch_transcoder(crtc), true);
5183
5184 return 0;
5185 }
5186
5187 /*
5188 * If display is now connected check links status,
5189 * there has been known issues of link loss triggering
5190 * long pulse.
5191 *
5192 * Some sinks (eg. ASUS PB287Q) seem to perform some
5193 * weird HPD ping pong during modesets. So we can apparently
5194 * end up with HPD going low during a modeset, and then
5195 * going back up soon after. And once that happens we must
5196 * retrain the link to get a picture. That's in case no
5197 * userspace component reacted to intermittent HPD dip.
5198 */
5199 static enum intel_hotplug_state
intel_dp_hotplug(struct intel_encoder * encoder,struct intel_connector * connector,bool irq_received)5200 intel_dp_hotplug(struct intel_encoder *encoder,
5201 struct intel_connector *connector,
5202 bool irq_received)
5203 {
5204 struct drm_modeset_acquire_ctx ctx;
5205 enum intel_hotplug_state state;
5206 int ret;
5207
5208 state = intel_encoder_hotplug(encoder, connector, irq_received);
5209
5210 drm_modeset_acquire_init(&ctx, 0);
5211
5212 for (;;) {
5213 ret = intel_dp_retrain_link(encoder, &ctx);
5214
5215 if (ret == -EDEADLK) {
5216 drm_modeset_backoff(&ctx);
5217 continue;
5218 }
5219
5220 break;
5221 }
5222
5223 drm_modeset_drop_locks(&ctx);
5224 drm_modeset_acquire_fini(&ctx);
5225 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
5226
5227 /*
5228 * Keeping it consistent with intel_ddi_hotplug() and
5229 * intel_hdmi_hotplug().
5230 */
5231 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
5232 state = INTEL_HOTPLUG_RETRY;
5233
5234 return state;
5235 }
5236
intel_dp_check_service_irq(struct intel_dp * intel_dp)5237 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
5238 {
5239 u8 val;
5240
5241 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5242 return;
5243
5244 if (drm_dp_dpcd_readb(&intel_dp->aux,
5245 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5246 return;
5247
5248 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5249
5250 if (val & DP_AUTOMATED_TEST_REQUEST)
5251 intel_dp_handle_test_request(intel_dp);
5252
5253 if (val & DP_CP_IRQ)
5254 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5255
5256 if (val & DP_SINK_SPECIFIC_IRQ)
5257 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
5258 }
5259
5260 /*
5261 * According to DP spec
5262 * 5.1.2:
5263 * 1. Read DPCD
5264 * 2. Configure link according to Receiver Capabilities
5265 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5266 * 4. Check link status on receipt of hot-plug interrupt
5267 *
5268 * intel_dp_short_pulse - handles short pulse interrupts
5269 * when full detection is not required.
5270 * Returns %true if short pulse is handled and full detection
5271 * is NOT required and %false otherwise.
5272 */
5273 static bool
intel_dp_short_pulse(struct intel_dp * intel_dp)5274 intel_dp_short_pulse(struct intel_dp *intel_dp)
5275 {
5276 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5277 u8 old_sink_count = intel_dp->sink_count;
5278 bool ret;
5279
5280 /*
5281 * Clearing compliance test variables to allow capturing
5282 * of values for next automated test request.
5283 */
5284 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5285
5286 /*
5287 * Now read the DPCD to see if it's actually running
5288 * If the current value of sink count doesn't match with
5289 * the value that was stored earlier or dpcd read failed
5290 * we need to do full detection
5291 */
5292 ret = intel_dp_get_dpcd(intel_dp);
5293
5294 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5295 /* No need to proceed if we are going to do full detect */
5296 return false;
5297 }
5298
5299 intel_dp_check_service_irq(intel_dp);
5300
5301 /* Handle CEC interrupts, if any */
5302 drm_dp_cec_irq(&intel_dp->aux);
5303
5304 /* defer to the hotplug work for link retraining if needed */
5305 if (intel_dp_needs_link_retrain(intel_dp))
5306 return false;
5307
5308 intel_psr_short_pulse(intel_dp);
5309
5310 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5311 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
5312 /* Send a Hotplug Uevent to userspace to start modeset */
5313 drm_kms_helper_hotplug_event(&dev_priv->drm);
5314 }
5315
5316 return true;
5317 }
5318
5319 /* XXX this is probably wrong for multiple downstream ports */
5320 static enum drm_connector_status
intel_dp_detect_dpcd(struct intel_dp * intel_dp)5321 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5322 {
5323 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5324 u8 *dpcd = intel_dp->dpcd;
5325 u8 type;
5326
5327 if (WARN_ON(intel_dp_is_edp(intel_dp)))
5328 return connector_status_connected;
5329
5330 if (lspcon->active)
5331 lspcon_resume(lspcon);
5332
5333 if (!intel_dp_get_dpcd(intel_dp))
5334 return connector_status_disconnected;
5335
5336 /* if there's no downstream port, we're done */
5337 if (!drm_dp_is_branch(dpcd))
5338 return connector_status_connected;
5339
5340 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5341 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5342 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5343
5344 return intel_dp->sink_count ?
5345 connector_status_connected : connector_status_disconnected;
5346 }
5347
5348 if (intel_dp_can_mst(intel_dp))
5349 return connector_status_connected;
5350
5351 /* If no HPD, poke DDC gently */
5352 if (drm_probe_ddc(&intel_dp->aux.ddc))
5353 return connector_status_connected;
5354
5355 /* Well we tried, say unknown for unreliable port types */
5356 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5357 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5358 if (type == DP_DS_PORT_TYPE_VGA ||
5359 type == DP_DS_PORT_TYPE_NON_EDID)
5360 return connector_status_unknown;
5361 } else {
5362 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5363 DP_DWN_STRM_PORT_TYPE_MASK;
5364 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5365 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5366 return connector_status_unknown;
5367 }
5368
5369 /* Anything else is out of spec, warn and ignore */
5370 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
5371 return connector_status_disconnected;
5372 }
5373
5374 static enum drm_connector_status
edp_detect(struct intel_dp * intel_dp)5375 edp_detect(struct intel_dp *intel_dp)
5376 {
5377 return connector_status_connected;
5378 }
5379
ibx_digital_port_connected(struct intel_encoder * encoder)5380 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5381 {
5382 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5383 u32 bit;
5384
5385 switch (encoder->hpd_pin) {
5386 case HPD_PORT_B:
5387 bit = SDE_PORTB_HOTPLUG;
5388 break;
5389 case HPD_PORT_C:
5390 bit = SDE_PORTC_HOTPLUG;
5391 break;
5392 case HPD_PORT_D:
5393 bit = SDE_PORTD_HOTPLUG;
5394 break;
5395 default:
5396 MISSING_CASE(encoder->hpd_pin);
5397 return false;
5398 }
5399
5400 return I915_READ(SDEISR) & bit;
5401 }
5402
cpt_digital_port_connected(struct intel_encoder * encoder)5403 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
5404 {
5405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5406 u32 bit;
5407
5408 switch (encoder->hpd_pin) {
5409 case HPD_PORT_B:
5410 bit = SDE_PORTB_HOTPLUG_CPT;
5411 break;
5412 case HPD_PORT_C:
5413 bit = SDE_PORTC_HOTPLUG_CPT;
5414 break;
5415 case HPD_PORT_D:
5416 bit = SDE_PORTD_HOTPLUG_CPT;
5417 break;
5418 default:
5419 MISSING_CASE(encoder->hpd_pin);
5420 return false;
5421 }
5422
5423 return I915_READ(SDEISR) & bit;
5424 }
5425
spt_digital_port_connected(struct intel_encoder * encoder)5426 static bool spt_digital_port_connected(struct intel_encoder *encoder)
5427 {
5428 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5429 u32 bit;
5430
5431 switch (encoder->hpd_pin) {
5432 case HPD_PORT_A:
5433 bit = SDE_PORTA_HOTPLUG_SPT;
5434 break;
5435 case HPD_PORT_E:
5436 bit = SDE_PORTE_HOTPLUG_SPT;
5437 break;
5438 default:
5439 return cpt_digital_port_connected(encoder);
5440 }
5441
5442 return I915_READ(SDEISR) & bit;
5443 }
5444
g4x_digital_port_connected(struct intel_encoder * encoder)5445 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5446 {
5447 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5448 u32 bit;
5449
5450 switch (encoder->hpd_pin) {
5451 case HPD_PORT_B:
5452 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5453 break;
5454 case HPD_PORT_C:
5455 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5456 break;
5457 case HPD_PORT_D:
5458 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5459 break;
5460 default:
5461 MISSING_CASE(encoder->hpd_pin);
5462 return false;
5463 }
5464
5465 return I915_READ(PORT_HOTPLUG_STAT) & bit;
5466 }
5467
gm45_digital_port_connected(struct intel_encoder * encoder)5468 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5469 {
5470 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5471 u32 bit;
5472
5473 switch (encoder->hpd_pin) {
5474 case HPD_PORT_B:
5475 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5476 break;
5477 case HPD_PORT_C:
5478 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5479 break;
5480 case HPD_PORT_D:
5481 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5482 break;
5483 default:
5484 MISSING_CASE(encoder->hpd_pin);
5485 return false;
5486 }
5487
5488 return I915_READ(PORT_HOTPLUG_STAT) & bit;
5489 }
5490
ilk_digital_port_connected(struct intel_encoder * encoder)5491 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5492 {
5493 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5494
5495 if (encoder->hpd_pin == HPD_PORT_A)
5496 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5497 else
5498 return ibx_digital_port_connected(encoder);
5499 }
5500
snb_digital_port_connected(struct intel_encoder * encoder)5501 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5502 {
5503 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5504
5505 if (encoder->hpd_pin == HPD_PORT_A)
5506 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5507 else
5508 return cpt_digital_port_connected(encoder);
5509 }
5510
ivb_digital_port_connected(struct intel_encoder * encoder)5511 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5512 {
5513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5514
5515 if (encoder->hpd_pin == HPD_PORT_A)
5516 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5517 else
5518 return cpt_digital_port_connected(encoder);
5519 }
5520
bdw_digital_port_connected(struct intel_encoder * encoder)5521 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5522 {
5523 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5524
5525 if (encoder->hpd_pin == HPD_PORT_A)
5526 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5527 else
5528 return cpt_digital_port_connected(encoder);
5529 }
5530
bxt_digital_port_connected(struct intel_encoder * encoder)5531 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5532 {
5533 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5534 u32 bit;
5535
5536 switch (encoder->hpd_pin) {
5537 case HPD_PORT_A:
5538 bit = BXT_DE_PORT_HP_DDIA;
5539 break;
5540 case HPD_PORT_B:
5541 bit = BXT_DE_PORT_HP_DDIB;
5542 break;
5543 case HPD_PORT_C:
5544 bit = BXT_DE_PORT_HP_DDIC;
5545 break;
5546 default:
5547 MISSING_CASE(encoder->hpd_pin);
5548 return false;
5549 }
5550
5551 return I915_READ(GEN8_DE_PORT_ISR) & bit;
5552 }
5553
intel_combo_phy_connected(struct drm_i915_private * dev_priv,enum phy phy)5554 static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv,
5555 enum phy phy)
5556 {
5557 if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
5558 return I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1);
5559
5560 return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
5561 }
5562
icp_digital_port_connected(struct intel_encoder * encoder)5563 static bool icp_digital_port_connected(struct intel_encoder *encoder)
5564 {
5565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5566 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5567 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
5568
5569 if (intel_phy_is_combo(dev_priv, phy))
5570 return intel_combo_phy_connected(dev_priv, phy);
5571 else if (intel_phy_is_tc(dev_priv, phy))
5572 return intel_tc_port_connected(dig_port);
5573 else
5574 MISSING_CASE(encoder->hpd_pin);
5575
5576 return false;
5577 }
5578
5579 /*
5580 * intel_digital_port_connected - is the specified port connected?
5581 * @encoder: intel_encoder
5582 *
5583 * In cases where there's a connector physically connected but it can't be used
5584 * by our hardware we also return false, since the rest of the driver should
5585 * pretty much treat the port as disconnected. This is relevant for type-C
5586 * (starting on ICL) where there's ownership involved.
5587 *
5588 * Return %true if port is connected, %false otherwise.
5589 */
__intel_digital_port_connected(struct intel_encoder * encoder)5590 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
5591 {
5592 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5593
5594 if (HAS_GMCH(dev_priv)) {
5595 if (IS_GM45(dev_priv))
5596 return gm45_digital_port_connected(encoder);
5597 else
5598 return g4x_digital_port_connected(encoder);
5599 }
5600
5601 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
5602 return icp_digital_port_connected(encoder);
5603 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
5604 return spt_digital_port_connected(encoder);
5605 else if (IS_GEN9_LP(dev_priv))
5606 return bxt_digital_port_connected(encoder);
5607 else if (IS_GEN(dev_priv, 8))
5608 return bdw_digital_port_connected(encoder);
5609 else if (IS_GEN(dev_priv, 7))
5610 return ivb_digital_port_connected(encoder);
5611 else if (IS_GEN(dev_priv, 6))
5612 return snb_digital_port_connected(encoder);
5613 else if (IS_GEN(dev_priv, 5))
5614 return ilk_digital_port_connected(encoder);
5615
5616 MISSING_CASE(INTEL_GEN(dev_priv));
5617 return false;
5618 }
5619
intel_digital_port_connected(struct intel_encoder * encoder)5620 bool intel_digital_port_connected(struct intel_encoder *encoder)
5621 {
5622 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5623 bool is_connected = false;
5624 intel_wakeref_t wakeref;
5625
5626 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5627 is_connected = __intel_digital_port_connected(encoder);
5628
5629 return is_connected;
5630 }
5631
5632 static struct edid *
intel_dp_get_edid(struct intel_dp * intel_dp)5633 intel_dp_get_edid(struct intel_dp *intel_dp)
5634 {
5635 struct intel_connector *intel_connector = intel_dp->attached_connector;
5636
5637 /* use cached edid if we have one */
5638 if (intel_connector->edid) {
5639 /* invalid edid */
5640 if (IS_ERR(intel_connector->edid))
5641 return NULL;
5642
5643 return drm_edid_duplicate(intel_connector->edid);
5644 } else
5645 return drm_get_edid(&intel_connector->base,
5646 &intel_dp->aux.ddc);
5647 }
5648
5649 static void
intel_dp_set_edid(struct intel_dp * intel_dp)5650 intel_dp_set_edid(struct intel_dp *intel_dp)
5651 {
5652 struct intel_connector *intel_connector = intel_dp->attached_connector;
5653 struct edid *edid;
5654
5655 intel_dp_unset_edid(intel_dp);
5656 edid = intel_dp_get_edid(intel_dp);
5657 intel_connector->detect_edid = edid;
5658
5659 intel_dp->has_audio = drm_detect_monitor_audio(edid);
5660 drm_dp_cec_set_edid(&intel_dp->aux, edid);
5661 }
5662
5663 static void
intel_dp_unset_edid(struct intel_dp * intel_dp)5664 intel_dp_unset_edid(struct intel_dp *intel_dp)
5665 {
5666 struct intel_connector *intel_connector = intel_dp->attached_connector;
5667
5668 drm_dp_cec_unset_edid(&intel_dp->aux);
5669 kfree(intel_connector->detect_edid);
5670 intel_connector->detect_edid = NULL;
5671
5672 intel_dp->has_audio = false;
5673 }
5674
5675 static int
intel_dp_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)5676 intel_dp_detect(struct drm_connector *connector,
5677 struct drm_modeset_acquire_ctx *ctx,
5678 bool force)
5679 {
5680 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5681 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5682 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5683 struct intel_encoder *encoder = &dig_port->base;
5684 enum drm_connector_status status;
5685
5686 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5687 connector->base.id, connector->name);
5688 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5689
5690 /* Can't disconnect eDP */
5691 if (intel_dp_is_edp(intel_dp))
5692 status = edp_detect(intel_dp);
5693 else if (intel_digital_port_connected(encoder))
5694 status = intel_dp_detect_dpcd(intel_dp);
5695 else
5696 status = connector_status_disconnected;
5697
5698 if (status == connector_status_disconnected) {
5699 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5700 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5701
5702 if (intel_dp->is_mst) {
5703 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5704 intel_dp->is_mst,
5705 intel_dp->mst_mgr.mst_state);
5706 intel_dp->is_mst = false;
5707 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5708 intel_dp->is_mst);
5709 }
5710
5711 goto out;
5712 }
5713
5714 if (intel_dp->reset_link_params) {
5715 /* Initial max link lane count */
5716 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5717
5718 /* Initial max link rate */
5719 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5720
5721 intel_dp->reset_link_params = false;
5722 }
5723
5724 intel_dp_print_rates(intel_dp);
5725
5726 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5727 if (INTEL_GEN(dev_priv) >= 11)
5728 intel_dp_get_dsc_sink_cap(intel_dp);
5729
5730 intel_dp_configure_mst(intel_dp);
5731
5732 if (intel_dp->is_mst) {
5733 /*
5734 * If we are in MST mode then this connector
5735 * won't appear connected or have anything
5736 * with EDID on it
5737 */
5738 status = connector_status_disconnected;
5739 goto out;
5740 }
5741
5742 /*
5743 * Some external monitors do not signal loss of link synchronization
5744 * with an IRQ_HPD, so force a link status check.
5745 */
5746 if (!intel_dp_is_edp(intel_dp)) {
5747 int ret;
5748
5749 ret = intel_dp_retrain_link(encoder, ctx);
5750 if (ret)
5751 return ret;
5752 }
5753
5754 /*
5755 * Clearing NACK and defer counts to get their exact values
5756 * while reading EDID which are required by Compliance tests
5757 * 4.2.2.4 and 4.2.2.5
5758 */
5759 intel_dp->aux.i2c_nack_count = 0;
5760 intel_dp->aux.i2c_defer_count = 0;
5761
5762 intel_dp_set_edid(intel_dp);
5763 if (intel_dp_is_edp(intel_dp) ||
5764 to_intel_connector(connector)->detect_edid)
5765 status = connector_status_connected;
5766
5767 intel_dp_check_service_irq(intel_dp);
5768
5769 out:
5770 if (status != connector_status_connected && !intel_dp->is_mst)
5771 intel_dp_unset_edid(intel_dp);
5772
5773 /*
5774 * Make sure the refs for power wells enabled during detect are
5775 * dropped to avoid a new detect cycle triggered by HPD polling.
5776 */
5777 intel_display_power_flush_work(dev_priv);
5778
5779 return status;
5780 }
5781
5782 static void
intel_dp_force(struct drm_connector * connector)5783 intel_dp_force(struct drm_connector *connector)
5784 {
5785 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5786 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5787 struct intel_encoder *intel_encoder = &dig_port->base;
5788 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5789 enum intel_display_power_domain aux_domain =
5790 intel_aux_power_domain(dig_port);
5791 intel_wakeref_t wakeref;
5792
5793 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5794 connector->base.id, connector->name);
5795 intel_dp_unset_edid(intel_dp);
5796
5797 if (connector->status != connector_status_connected)
5798 return;
5799
5800 wakeref = intel_display_power_get(dev_priv, aux_domain);
5801
5802 intel_dp_set_edid(intel_dp);
5803
5804 intel_display_power_put(dev_priv, aux_domain, wakeref);
5805 }
5806
intel_dp_get_modes(struct drm_connector * connector)5807 static int intel_dp_get_modes(struct drm_connector *connector)
5808 {
5809 struct intel_connector *intel_connector = to_intel_connector(connector);
5810 struct edid *edid;
5811
5812 edid = intel_connector->detect_edid;
5813 if (edid) {
5814 int ret = intel_connector_update_modes(connector, edid);
5815 if (ret)
5816 return ret;
5817 }
5818
5819 /* if eDP has no EDID, fall back to fixed mode */
5820 if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) &&
5821 intel_connector->panel.fixed_mode) {
5822 struct drm_display_mode *mode;
5823
5824 mode = drm_mode_duplicate(connector->dev,
5825 intel_connector->panel.fixed_mode);
5826 if (mode) {
5827 drm_mode_probed_add(connector, mode);
5828 return 1;
5829 }
5830 }
5831
5832 return 0;
5833 }
5834
5835 static int
intel_dp_connector_register(struct drm_connector * connector)5836 intel_dp_connector_register(struct drm_connector *connector)
5837 {
5838 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5839 int ret;
5840
5841 ret = intel_connector_register(connector);
5842 if (ret)
5843 return ret;
5844
5845 i915_debugfs_connector_add(connector);
5846
5847 #ifdef __NetBSD__
5848 DRM_DEBUG_KMS("registering %s bus for %s\n",
5849 intel_dp->aux.name, connector->name);
5850 #else
5851 DRM_DEBUG_KMS("registering %s bus for %s\n",
5852 intel_dp->aux.name, connector->kdev->kobj.name);
5853 #endif
5854
5855 intel_dp->aux.dev = connector->kdev;
5856 ret = drm_dp_aux_register(&intel_dp->aux);
5857 if (!ret)
5858 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5859 return ret;
5860 }
5861
5862 static void
intel_dp_connector_unregister(struct drm_connector * connector)5863 intel_dp_connector_unregister(struct drm_connector *connector)
5864 {
5865 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5866
5867 drm_dp_cec_unregister_connector(&intel_dp->aux);
5868 drm_dp_aux_unregister(&intel_dp->aux);
5869 intel_connector_unregister(connector);
5870 }
5871
intel_dp_encoder_flush_work(struct drm_encoder * encoder)5872 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5873 {
5874 struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5875 struct intel_dp *intel_dp = &intel_dig_port->dp;
5876
5877 intel_dp_mst_encoder_cleanup(intel_dig_port);
5878 if (intel_dp_is_edp(intel_dp)) {
5879 intel_wakeref_t wakeref;
5880
5881 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5882 /*
5883 * vdd might still be enabled do to the delayed vdd off.
5884 * Make sure vdd is actually turned off here.
5885 */
5886 with_pps_lock(intel_dp, wakeref)
5887 edp_panel_vdd_off_sync(intel_dp);
5888
5889 if (intel_dp->edp_notifier.notifier_call) {
5890 unregister_reboot_notifier(&intel_dp->edp_notifier);
5891 intel_dp->edp_notifier.notifier_call = NULL;
5892 }
5893 }
5894
5895 intel_dp_aux_fini(intel_dp);
5896 }
5897
intel_dp_encoder_destroy(struct drm_encoder * encoder)5898 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5899 {
5900 intel_dp_encoder_flush_work(encoder);
5901
5902 drm_encoder_cleanup(encoder);
5903 kfree(enc_to_dig_port(to_intel_encoder(encoder)));
5904 }
5905
intel_dp_encoder_suspend(struct intel_encoder * intel_encoder)5906 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5907 {
5908 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5909 intel_wakeref_t wakeref;
5910
5911 if (!intel_dp_is_edp(intel_dp))
5912 return;
5913
5914 /*
5915 * vdd might still be enabled do to the delayed vdd off.
5916 * Make sure vdd is actually turned off here.
5917 */
5918 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5919 with_pps_lock(intel_dp, wakeref)
5920 edp_panel_vdd_off_sync(intel_dp);
5921 }
5922
intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp * hdcp,int timeout)5923 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5924 {
5925 long ret;
5926
5927 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5928 unsigned long irqflags;
5929 spin_lock_irqsave(&hdcp->cp_irq_lock, irqflags);
5930 DRM_SPIN_TIMED_WAIT_UNTIL(ret, &hdcp->cp_irq_queue,
5931 &hdcp->cp_irq_lock,
5932 msecs_to_jiffies(timeout),
5933 C);
5934 if (!ret)
5935 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5936 spin_unlock_irqrestore(&hdcp->cp_irq_lock, irqflags);
5937 }
5938
5939 static
intel_dp_hdcp_write_an_aksv(struct intel_digital_port * intel_dig_port,u8 * an)5940 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5941 u8 *an)
5942 {
5943 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base));
5944 static const struct drm_dp_aux_msg msg = {
5945 .request = DP_AUX_NATIVE_WRITE,
5946 .address = DP_AUX_HDCP_AKSV,
5947 .size = DRM_HDCP_KSV_LEN,
5948 };
5949 u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5950 ssize_t dpcd_ret;
5951 int ret;
5952
5953 /* Output An first, that's easy */
5954 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5955 an, DRM_HDCP_AN_LEN);
5956 if (dpcd_ret != DRM_HDCP_AN_LEN) {
5957 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5958 dpcd_ret);
5959 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5960 }
5961
5962 /*
5963 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5964 * order to get it on the wire, we need to create the AUX header as if
5965 * we were writing the data, and then tickle the hardware to output the
5966 * data once the header is sent out.
5967 */
5968 intel_dp_aux_header(txbuf, &msg);
5969
5970 ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5971 rxbuf, sizeof(rxbuf),
5972 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5973 if (ret < 0) {
5974 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5975 return ret;
5976 } else if (ret == 0) {
5977 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5978 return -EIO;
5979 }
5980
5981 reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5982 if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5983 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5984 reply);
5985 return -EIO;
5986 }
5987 return 0;
5988 }
5989
intel_dp_hdcp_read_bksv(struct intel_digital_port * intel_dig_port,u8 * bksv)5990 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5991 u8 *bksv)
5992 {
5993 ssize_t ret;
5994 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5995 DRM_HDCP_KSV_LEN);
5996 if (ret != DRM_HDCP_KSV_LEN) {
5997 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5998 return ret >= 0 ? -EIO : ret;
5999 }
6000 return 0;
6001 }
6002
intel_dp_hdcp_read_bstatus(struct intel_digital_port * intel_dig_port,u8 * bstatus)6003 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
6004 u8 *bstatus)
6005 {
6006 ssize_t ret;
6007 /*
6008 * For some reason the HDMI and DP HDCP specs call this register
6009 * definition by different names. In the HDMI spec, it's called BSTATUS,
6010 * but in DP it's called BINFO.
6011 */
6012 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
6013 bstatus, DRM_HDCP_BSTATUS_LEN);
6014 if (ret != DRM_HDCP_BSTATUS_LEN) {
6015 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6016 return ret >= 0 ? -EIO : ret;
6017 }
6018 return 0;
6019 }
6020
6021 static
intel_dp_hdcp_read_bcaps(struct intel_digital_port * intel_dig_port,u8 * bcaps)6022 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
6023 u8 *bcaps)
6024 {
6025 ssize_t ret;
6026
6027 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
6028 bcaps, 1);
6029 if (ret != 1) {
6030 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
6031 return ret >= 0 ? -EIO : ret;
6032 }
6033
6034 return 0;
6035 }
6036
6037 static
intel_dp_hdcp_repeater_present(struct intel_digital_port * intel_dig_port,bool * repeater_present)6038 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
6039 bool *repeater_present)
6040 {
6041 ssize_t ret;
6042 u8 bcaps;
6043
6044 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6045 if (ret)
6046 return ret;
6047
6048 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
6049 return 0;
6050 }
6051
6052 static
intel_dp_hdcp_read_ri_prime(struct intel_digital_port * intel_dig_port,u8 * ri_prime)6053 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
6054 u8 *ri_prime)
6055 {
6056 ssize_t ret;
6057 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
6058 ri_prime, DRM_HDCP_RI_LEN);
6059 if (ret != DRM_HDCP_RI_LEN) {
6060 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
6061 return ret >= 0 ? -EIO : ret;
6062 }
6063 return 0;
6064 }
6065
6066 static
intel_dp_hdcp_read_ksv_ready(struct intel_digital_port * intel_dig_port,bool * ksv_ready)6067 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
6068 bool *ksv_ready)
6069 {
6070 ssize_t ret;
6071 u8 bstatus;
6072 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6073 &bstatus, 1);
6074 if (ret != 1) {
6075 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6076 return ret >= 0 ? -EIO : ret;
6077 }
6078 *ksv_ready = bstatus & DP_BSTATUS_READY;
6079 return 0;
6080 }
6081
6082 static
intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port * intel_dig_port,int num_downstream,u8 * ksv_fifo)6083 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
6084 int num_downstream, u8 *ksv_fifo)
6085 {
6086 ssize_t ret;
6087 int i;
6088
6089 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
6090 for (i = 0; i < num_downstream; i += 3) {
6091 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
6092 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6093 DP_AUX_HDCP_KSV_FIFO,
6094 ksv_fifo + i * DRM_HDCP_KSV_LEN,
6095 len);
6096 if (ret != len) {
6097 DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
6098 i, ret);
6099 return ret >= 0 ? -EIO : ret;
6100 }
6101 }
6102 return 0;
6103 }
6104
6105 static
intel_dp_hdcp_read_v_prime_part(struct intel_digital_port * intel_dig_port,int i,u32 * part)6106 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
6107 int i, u32 *part)
6108 {
6109 ssize_t ret;
6110
6111 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
6112 return -EINVAL;
6113
6114 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6115 DP_AUX_HDCP_V_PRIME(i), part,
6116 DRM_HDCP_V_PRIME_PART_LEN);
6117 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
6118 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
6119 return ret >= 0 ? -EIO : ret;
6120 }
6121 return 0;
6122 }
6123
6124 static
intel_dp_hdcp_toggle_signalling(struct intel_digital_port * intel_dig_port,bool enable)6125 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
6126 bool enable)
6127 {
6128 /* Not used for single stream DisplayPort setups */
6129 return 0;
6130 }
6131
6132 static
intel_dp_hdcp_check_link(struct intel_digital_port * intel_dig_port)6133 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
6134 {
6135 ssize_t ret;
6136 u8 bstatus;
6137
6138 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6139 &bstatus, 1);
6140 if (ret != 1) {
6141 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6142 return false;
6143 }
6144
6145 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
6146 }
6147
6148 static
intel_dp_hdcp_capable(struct intel_digital_port * intel_dig_port,bool * hdcp_capable)6149 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
6150 bool *hdcp_capable)
6151 {
6152 ssize_t ret;
6153 u8 bcaps;
6154
6155 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6156 if (ret)
6157 return ret;
6158
6159 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
6160 return 0;
6161 }
6162
6163 struct hdcp2_dp_errata_stream_type {
6164 u8 msg_id;
6165 u8 stream_type;
6166 } __packed;
6167
6168 struct hdcp2_dp_msg_data {
6169 u8 msg_id;
6170 u32 offset;
6171 bool msg_detectable;
6172 u32 timeout;
6173 u32 timeout2; /* Added for non_paired situation */
6174 };
6175
6176 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
6177 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
6178 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
6179 false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
6180 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
6181 false, 0, 0 },
6182 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
6183 false, 0, 0 },
6184 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
6185 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
6186 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
6187 { HDCP_2_2_AKE_SEND_PAIRING_INFO,
6188 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
6189 HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
6190 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
6191 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
6192 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
6193 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
6194 0, 0 },
6195 { HDCP_2_2_REP_SEND_RECVID_LIST,
6196 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
6197 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
6198 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
6199 0, 0 },
6200 { HDCP_2_2_REP_STREAM_MANAGE,
6201 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
6202 0, 0 },
6203 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
6204 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
6205 /* local define to shovel this through the write_2_2 interface */
6206 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
6207 { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
6208 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
6209 0, 0 },
6210 };
6211
6212 static inline
intel_dp_hdcp2_read_rx_status(struct intel_digital_port * intel_dig_port,u8 * rx_status)6213 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
6214 u8 *rx_status)
6215 {
6216 ssize_t ret;
6217
6218 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6219 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
6220 HDCP_2_2_DP_RXSTATUS_LEN);
6221 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
6222 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6223 return ret >= 0 ? -EIO : ret;
6224 }
6225
6226 return 0;
6227 }
6228
6229 static
hdcp2_detect_msg_availability(struct intel_digital_port * intel_dig_port,u8 msg_id,bool * msg_ready)6230 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
6231 u8 msg_id, bool *msg_ready)
6232 {
6233 u8 rx_status;
6234 int ret;
6235
6236 *msg_ready = false;
6237 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6238 if (ret < 0)
6239 return ret;
6240
6241 switch (msg_id) {
6242 case HDCP_2_2_AKE_SEND_HPRIME:
6243 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
6244 *msg_ready = true;
6245 break;
6246 case HDCP_2_2_AKE_SEND_PAIRING_INFO:
6247 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
6248 *msg_ready = true;
6249 break;
6250 case HDCP_2_2_REP_SEND_RECVID_LIST:
6251 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6252 *msg_ready = true;
6253 break;
6254 default:
6255 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
6256 return -EINVAL;
6257 }
6258
6259 return 0;
6260 }
6261
6262 static ssize_t
intel_dp_hdcp2_wait_for_msg(struct intel_digital_port * intel_dig_port,const struct hdcp2_dp_msg_data * hdcp2_msg_data)6263 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
6264 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
6265 {
6266 struct intel_dp *dp = &intel_dig_port->dp;
6267 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6268 u8 msg_id = hdcp2_msg_data->msg_id;
6269 int ret, timeout;
6270 bool msg_ready = false;
6271
6272 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
6273 timeout = hdcp2_msg_data->timeout2;
6274 else
6275 timeout = hdcp2_msg_data->timeout;
6276
6277 /*
6278 * There is no way to detect the CERT, LPRIME and STREAM_READY
6279 * availability. So Wait for timeout and read the msg.
6280 */
6281 if (!hdcp2_msg_data->msg_detectable) {
6282 mdelay(timeout);
6283 ret = 0;
6284 } else {
6285 /*
6286 * As we want to check the msg availability at timeout, Ignoring
6287 * the timeout at wait for CP_IRQ.
6288 */
6289 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
6290 ret = hdcp2_detect_msg_availability(intel_dig_port,
6291 msg_id, &msg_ready);
6292 if (!msg_ready)
6293 ret = -ETIMEDOUT;
6294 }
6295
6296 if (ret)
6297 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
6298 hdcp2_msg_data->msg_id, ret, timeout);
6299
6300 return ret;
6301 }
6302
get_hdcp2_dp_msg_data(u8 msg_id)6303 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6304 {
6305 int i;
6306
6307 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6308 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6309 return &hdcp2_dp_msg_data[i];
6310
6311 return NULL;
6312 }
6313
6314 static
intel_dp_hdcp2_write_msg(struct intel_digital_port * intel_dig_port,void * buf,size_t size)6315 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6316 void *buf, size_t size)
6317 {
6318 struct intel_dp *dp = &intel_dig_port->dp;
6319 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6320 unsigned int offset;
6321 u8 *byte = buf;
6322 ssize_t ret, bytes_to_write, len;
6323 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6324
6325 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6326 if (!hdcp2_msg_data)
6327 return -EINVAL;
6328
6329 offset = hdcp2_msg_data->offset;
6330
6331 /* No msg_id in DP HDCP2.2 msgs */
6332 bytes_to_write = size - 1;
6333 byte++;
6334
6335 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6336
6337 while (bytes_to_write) {
6338 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6339 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6340
6341 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6342 offset, (void *)byte, len);
6343 if (ret < 0)
6344 return ret;
6345
6346 bytes_to_write -= ret;
6347 byte += ret;
6348 offset += ret;
6349 }
6350
6351 return size;
6352 }
6353
6354 static
get_receiver_id_list_size(struct intel_digital_port * intel_dig_port)6355 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6356 {
6357 u8 rx_info[HDCP_2_2_RXINFO_LEN];
6358 u32 dev_cnt;
6359 ssize_t ret;
6360
6361 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6362 DP_HDCP_2_2_REG_RXINFO_OFFSET,
6363 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6364 if (ret != HDCP_2_2_RXINFO_LEN)
6365 return ret >= 0 ? -EIO : ret;
6366
6367 dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6368 HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6369
6370 if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6371 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6372
6373 ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6374 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6375 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6376
6377 return ret;
6378 }
6379
6380 static
intel_dp_hdcp2_read_msg(struct intel_digital_port * intel_dig_port,u8 msg_id,void * buf,size_t size)6381 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6382 u8 msg_id, void *buf, size_t size)
6383 {
6384 unsigned int offset;
6385 u8 *byte = buf;
6386 ssize_t ret, bytes_to_recv, len;
6387 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6388
6389 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6390 if (!hdcp2_msg_data)
6391 return -EINVAL;
6392 offset = hdcp2_msg_data->offset;
6393
6394 ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6395 if (ret < 0)
6396 return ret;
6397
6398 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6399 ret = get_receiver_id_list_size(intel_dig_port);
6400 if (ret < 0)
6401 return ret;
6402
6403 size = ret;
6404 }
6405 bytes_to_recv = size - 1;
6406
6407 /* DP adaptation msgs has no msg_id */
6408 byte++;
6409
6410 while (bytes_to_recv) {
6411 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6412 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6413
6414 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6415 (void *)byte, len);
6416 if (ret < 0) {
6417 DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6418 return ret;
6419 }
6420
6421 bytes_to_recv -= ret;
6422 byte += ret;
6423 offset += ret;
6424 }
6425 byte = buf;
6426 *byte = msg_id;
6427
6428 return size;
6429 }
6430
6431 static
intel_dp_hdcp2_config_stream_type(struct intel_digital_port * intel_dig_port,bool is_repeater,u8 content_type)6432 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6433 bool is_repeater, u8 content_type)
6434 {
6435 struct hdcp2_dp_errata_stream_type stream_type_msg;
6436
6437 if (is_repeater)
6438 return 0;
6439
6440 /*
6441 * Errata for DP: As Stream type is used for encryption, Receiver
6442 * should be communicated with stream type for the decryption of the
6443 * content.
6444 * Repeater will be communicated with stream type as a part of it's
6445 * auth later in time.
6446 */
6447 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6448 stream_type_msg.stream_type = content_type;
6449
6450 return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6451 sizeof(stream_type_msg));
6452 }
6453
6454 static
intel_dp_hdcp2_check_link(struct intel_digital_port * intel_dig_port)6455 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6456 {
6457 u8 rx_status;
6458 int ret;
6459
6460 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6461 if (ret)
6462 return ret;
6463
6464 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6465 ret = HDCP_REAUTH_REQUEST;
6466 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6467 ret = HDCP_LINK_INTEGRITY_FAILURE;
6468 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6469 ret = HDCP_TOPOLOGY_CHANGE;
6470
6471 return ret;
6472 }
6473
6474 static
intel_dp_hdcp2_capable(struct intel_digital_port * intel_dig_port,bool * capable)6475 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6476 bool *capable)
6477 {
6478 u8 rx_caps[3];
6479 int ret;
6480
6481 *capable = false;
6482 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6483 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6484 rx_caps, HDCP_2_2_RXCAPS_LEN);
6485 if (ret != HDCP_2_2_RXCAPS_LEN)
6486 return ret >= 0 ? -EIO : ret;
6487
6488 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6489 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6490 *capable = true;
6491
6492 return 0;
6493 }
6494
6495 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6496 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6497 .read_bksv = intel_dp_hdcp_read_bksv,
6498 .read_bstatus = intel_dp_hdcp_read_bstatus,
6499 .repeater_present = intel_dp_hdcp_repeater_present,
6500 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6501 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6502 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6503 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6504 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6505 .check_link = intel_dp_hdcp_check_link,
6506 .hdcp_capable = intel_dp_hdcp_capable,
6507 .write_2_2_msg = intel_dp_hdcp2_write_msg,
6508 .read_2_2_msg = intel_dp_hdcp2_read_msg,
6509 .config_stream_type = intel_dp_hdcp2_config_stream_type,
6510 .check_2_2_link = intel_dp_hdcp2_check_link,
6511 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6512 .protocol = HDCP_PROTOCOL_DP,
6513 };
6514
intel_edp_panel_vdd_sanitize(struct intel_dp * intel_dp)6515 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6516 {
6517 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6518 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6519
6520 lockdep_assert_held(&dev_priv->pps_mutex);
6521
6522 if (!edp_have_panel_vdd(intel_dp))
6523 return;
6524
6525 /*
6526 * The VDD bit needs a power domain reference, so if the bit is
6527 * already enabled when we boot or resume, grab this reference and
6528 * schedule a vdd off, so we don't hold on to the reference
6529 * indefinitely.
6530 */
6531 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6532 intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6533
6534 edp_panel_vdd_schedule_off(intel_dp);
6535 }
6536
vlv_active_pipe(struct intel_dp * intel_dp)6537 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6538 {
6539 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6540 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6541 enum pipe pipe;
6542
6543 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6544 encoder->port, &pipe))
6545 return pipe;
6546
6547 return INVALID_PIPE;
6548 }
6549
intel_dp_encoder_reset(struct drm_encoder * encoder)6550 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6551 {
6552 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6553 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
6554 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6555 intel_wakeref_t wakeref;
6556
6557 if (!HAS_DDI(dev_priv))
6558 intel_dp->DP = I915_READ(intel_dp->output_reg);
6559
6560 if (lspcon->active)
6561 lspcon_resume(lspcon);
6562
6563 intel_dp->reset_link_params = true;
6564
6565 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6566 !intel_dp_is_edp(intel_dp))
6567 return;
6568
6569 with_pps_lock(intel_dp, wakeref) {
6570 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6571 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6572
6573 if (intel_dp_is_edp(intel_dp)) {
6574 /*
6575 * Reinit the power sequencer, in case BIOS did
6576 * something nasty with it.
6577 */
6578 intel_dp_pps_init(intel_dp);
6579 intel_edp_panel_vdd_sanitize(intel_dp);
6580 }
6581 }
6582 }
6583
6584 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6585 .force = intel_dp_force,
6586 .fill_modes = drm_helper_probe_single_connector_modes,
6587 .atomic_get_property = intel_digital_connector_atomic_get_property,
6588 .atomic_set_property = intel_digital_connector_atomic_set_property,
6589 .late_register = intel_dp_connector_register,
6590 .early_unregister = intel_dp_connector_unregister,
6591 .destroy = intel_connector_destroy,
6592 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6593 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6594 };
6595
6596 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6597 .detect_ctx = intel_dp_detect,
6598 .get_modes = intel_dp_get_modes,
6599 .mode_valid = intel_dp_mode_valid,
6600 .atomic_check = intel_digital_connector_atomic_check,
6601 };
6602
6603 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6604 .reset = intel_dp_encoder_reset,
6605 .destroy = intel_dp_encoder_destroy,
6606 };
6607
6608 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port * intel_dig_port,bool long_hpd)6609 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6610 {
6611 struct intel_dp *intel_dp = &intel_dig_port->dp;
6612
6613 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6614 /*
6615 * vdd off can generate a long pulse on eDP which
6616 * would require vdd on to handle it, and thus we
6617 * would end up in an endless cycle of
6618 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6619 */
6620 DRM_DEBUG_KMS("ignoring long hpd on eDP [ENCODER:%d:%s]\n",
6621 intel_dig_port->base.base.base.id,
6622 intel_dig_port->base.base.name);
6623 return IRQ_HANDLED;
6624 }
6625
6626 DRM_DEBUG_KMS("got hpd irq on [ENCODER:%d:%s] - %s\n",
6627 intel_dig_port->base.base.base.id,
6628 intel_dig_port->base.base.name,
6629 long_hpd ? "long" : "short");
6630
6631 if (long_hpd) {
6632 intel_dp->reset_link_params = true;
6633 return IRQ_NONE;
6634 }
6635
6636 if (intel_dp->is_mst) {
6637 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6638 /*
6639 * If we were in MST mode, and device is not
6640 * there, get out of MST mode
6641 */
6642 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6643 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6644 intel_dp->is_mst = false;
6645 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6646 intel_dp->is_mst);
6647
6648 return IRQ_NONE;
6649 }
6650 }
6651
6652 if (!intel_dp->is_mst) {
6653 bool handled;
6654
6655 handled = intel_dp_short_pulse(intel_dp);
6656
6657 if (!handled)
6658 return IRQ_NONE;
6659 }
6660
6661 return IRQ_HANDLED;
6662 }
6663
6664 /* check the VBT to see whether the eDP is on another port */
intel_dp_is_port_edp(struct drm_i915_private * dev_priv,enum port port)6665 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6666 {
6667 /*
6668 * eDP not supported on g4x. so bail out early just
6669 * for a bit extra safety in case the VBT is bonkers.
6670 */
6671 if (INTEL_GEN(dev_priv) < 5)
6672 return false;
6673
6674 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6675 return true;
6676
6677 return intel_bios_is_port_edp(dev_priv, port);
6678 }
6679
6680 static void
intel_dp_add_properties(struct intel_dp * intel_dp,struct drm_connector * connector)6681 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6682 {
6683 struct drm_i915_private *dev_priv = to_i915(connector->dev);
6684 enum port port = dp_to_dig_port(intel_dp)->base.port;
6685
6686 if (!IS_G4X(dev_priv) && port != PORT_A)
6687 intel_attach_force_audio_property(connector);
6688
6689 intel_attach_broadcast_rgb_property(connector);
6690 if (HAS_GMCH(dev_priv))
6691 drm_connector_attach_max_bpc_property(connector, 6, 10);
6692 else if (INTEL_GEN(dev_priv) >= 5)
6693 drm_connector_attach_max_bpc_property(connector, 6, 12);
6694
6695 intel_attach_colorspace_property(connector);
6696
6697 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
6698 drm_object_attach_property(&connector->base,
6699 connector->dev->mode_config.hdr_output_metadata_property,
6700 0);
6701
6702 if (intel_dp_is_edp(intel_dp)) {
6703 u32 allowed_scalers;
6704
6705 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6706 if (!HAS_GMCH(dev_priv))
6707 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6708
6709 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6710
6711 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6712
6713 }
6714 }
6715
intel_dp_init_panel_power_timestamps(struct intel_dp * intel_dp)6716 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6717 {
6718 intel_dp->panel_power_off_time = ktime_get_boottime();
6719 intel_dp->last_power_on = jiffies;
6720 intel_dp->last_backlight_off = jiffies;
6721 }
6722
6723 static void
intel_pps_readout_hw_state(struct intel_dp * intel_dp,struct edp_power_seq * seq)6724 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6725 {
6726 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6727 u32 pp_on, pp_off, pp_ctl;
6728 struct pps_registers regs;
6729
6730 intel_pps_get_registers(intel_dp, ®s);
6731
6732 pp_ctl = ilk_get_pp_control(intel_dp);
6733
6734 /* Ensure PPS is unlocked */
6735 if (!HAS_DDI(dev_priv))
6736 I915_WRITE(regs.pp_ctrl, pp_ctl);
6737
6738 pp_on = I915_READ(regs.pp_on);
6739 pp_off = I915_READ(regs.pp_off);
6740
6741 /* Pull timing values out of registers */
6742 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6743 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6744 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6745 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6746
6747 if (i915_mmio_reg_valid(regs.pp_div)) {
6748 u32 pp_div;
6749
6750 pp_div = I915_READ(regs.pp_div);
6751
6752 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6753 } else {
6754 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6755 }
6756 }
6757
6758 static void
intel_pps_dump_state(const char * state_name,const struct edp_power_seq * seq)6759 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6760 {
6761 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6762 state_name,
6763 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6764 }
6765
6766 static void
intel_pps_verify_state(struct intel_dp * intel_dp)6767 intel_pps_verify_state(struct intel_dp *intel_dp)
6768 {
6769 struct edp_power_seq hw;
6770 struct edp_power_seq *sw = &intel_dp->pps_delays;
6771
6772 intel_pps_readout_hw_state(intel_dp, &hw);
6773
6774 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6775 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6776 DRM_ERROR("PPS state mismatch\n");
6777 intel_pps_dump_state("sw", sw);
6778 intel_pps_dump_state("hw", &hw);
6779 }
6780 }
6781
6782 static void
intel_dp_init_panel_power_sequencer(struct intel_dp * intel_dp)6783 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6784 {
6785 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6786 struct edp_power_seq cur, vbt, spec,
6787 *final = &intel_dp->pps_delays;
6788
6789 lockdep_assert_held(&dev_priv->pps_mutex);
6790
6791 /* already initialized? */
6792 if (final->t11_t12 != 0)
6793 return;
6794
6795 intel_pps_readout_hw_state(intel_dp, &cur);
6796
6797 intel_pps_dump_state("cur", &cur);
6798
6799 vbt = dev_priv->vbt.edp.pps;
6800 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6801 * of 500ms appears to be too short. Ocassionally the panel
6802 * just fails to power back on. Increasing the delay to 800ms
6803 * seems sufficient to avoid this problem.
6804 */
6805 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6806 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6807 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6808 vbt.t11_t12);
6809 }
6810 /* T11_T12 delay is special and actually in units of 100ms, but zero
6811 * based in the hw (so we need to add 100 ms). But the sw vbt
6812 * table multiplies it with 1000 to make it in units of 100usec,
6813 * too. */
6814 vbt.t11_t12 += 100 * 10;
6815
6816 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6817 * our hw here, which are all in 100usec. */
6818 spec.t1_t3 = 210 * 10;
6819 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6820 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6821 spec.t10 = 500 * 10;
6822 /* This one is special and actually in units of 100ms, but zero
6823 * based in the hw (so we need to add 100 ms). But the sw vbt
6824 * table multiplies it with 1000 to make it in units of 100usec,
6825 * too. */
6826 spec.t11_t12 = (510 + 100) * 10;
6827
6828 intel_pps_dump_state("vbt", &vbt);
6829
6830 /* Use the max of the register settings and vbt. If both are
6831 * unset, fall back to the spec limits. */
6832 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
6833 spec.field : \
6834 max(cur.field, vbt.field))
6835 assign_final(t1_t3);
6836 assign_final(t8);
6837 assign_final(t9);
6838 assign_final(t10);
6839 assign_final(t11_t12);
6840 #undef assign_final
6841
6842 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
6843 intel_dp->panel_power_up_delay = get_delay(t1_t3);
6844 intel_dp->backlight_on_delay = get_delay(t8);
6845 intel_dp->backlight_off_delay = get_delay(t9);
6846 intel_dp->panel_power_down_delay = get_delay(t10);
6847 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6848 #undef get_delay
6849
6850 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6851 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6852 intel_dp->panel_power_cycle_delay);
6853
6854 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6855 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6856
6857 /*
6858 * We override the HW backlight delays to 1 because we do manual waits
6859 * on them. For T8, even BSpec recommends doing it. For T9, if we
6860 * don't do this, we'll end up waiting for the backlight off delay
6861 * twice: once when we do the manual sleep, and once when we disable
6862 * the panel and wait for the PP_STATUS bit to become zero.
6863 */
6864 final->t8 = 1;
6865 final->t9 = 1;
6866
6867 /*
6868 * HW has only a 100msec granularity for t11_t12 so round it up
6869 * accordingly.
6870 */
6871 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6872 }
6873
6874 static void
intel_dp_init_panel_power_sequencer_registers(struct intel_dp * intel_dp,bool force_disable_vdd)6875 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6876 bool force_disable_vdd)
6877 {
6878 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6879 u32 pp_on, pp_off, port_sel = 0;
6880 int div = dev_priv->rawclk_freq / 1000;
6881 struct pps_registers regs;
6882 enum port port = dp_to_dig_port(intel_dp)->base.port;
6883 const struct edp_power_seq *seq = &intel_dp->pps_delays;
6884
6885 lockdep_assert_held(&dev_priv->pps_mutex);
6886
6887 intel_pps_get_registers(intel_dp, ®s);
6888
6889 /*
6890 * On some VLV machines the BIOS can leave the VDD
6891 * enabled even on power sequencers which aren't
6892 * hooked up to any port. This would mess up the
6893 * power domain tracking the first time we pick
6894 * one of these power sequencers for use since
6895 * edp_panel_vdd_on() would notice that the VDD was
6896 * already on and therefore wouldn't grab the power
6897 * domain reference. Disable VDD first to avoid this.
6898 * This also avoids spuriously turning the VDD on as
6899 * soon as the new power sequencer gets initialized.
6900 */
6901 if (force_disable_vdd) {
6902 u32 pp = ilk_get_pp_control(intel_dp);
6903
6904 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6905
6906 if (pp & EDP_FORCE_VDD)
6907 DRM_DEBUG_KMS("VDD already on, disabling first\n");
6908
6909 pp &= ~EDP_FORCE_VDD;
6910
6911 I915_WRITE(regs.pp_ctrl, pp);
6912 }
6913
6914 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6915 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6916 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6917 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6918
6919 /* Haswell doesn't have any port selection bits for the panel
6920 * power sequencer any more. */
6921 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6922 port_sel = PANEL_PORT_SELECT_VLV(port);
6923 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6924 switch (port) {
6925 case PORT_A:
6926 port_sel = PANEL_PORT_SELECT_DPA;
6927 break;
6928 case PORT_C:
6929 port_sel = PANEL_PORT_SELECT_DPC;
6930 break;
6931 case PORT_D:
6932 port_sel = PANEL_PORT_SELECT_DPD;
6933 break;
6934 default:
6935 MISSING_CASE(port);
6936 break;
6937 }
6938 }
6939
6940 pp_on |= port_sel;
6941
6942 I915_WRITE(regs.pp_on, pp_on);
6943 I915_WRITE(regs.pp_off, pp_off);
6944
6945 /*
6946 * Compute the divisor for the pp clock, simply match the Bspec formula.
6947 */
6948 if (i915_mmio_reg_valid(regs.pp_div)) {
6949 I915_WRITE(regs.pp_div,
6950 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6951 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6952 } else {
6953 u32 pp_ctl;
6954
6955 pp_ctl = I915_READ(regs.pp_ctrl);
6956 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6957 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6958 I915_WRITE(regs.pp_ctrl, pp_ctl);
6959 }
6960
6961 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6962 I915_READ(regs.pp_on),
6963 I915_READ(regs.pp_off),
6964 i915_mmio_reg_valid(regs.pp_div) ?
6965 I915_READ(regs.pp_div) :
6966 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6967 }
6968
intel_dp_pps_init(struct intel_dp * intel_dp)6969 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6970 {
6971 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6972
6973 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6974 vlv_initial_power_sequencer_setup(intel_dp);
6975 } else {
6976 intel_dp_init_panel_power_sequencer(intel_dp);
6977 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6978 }
6979 }
6980
6981 /**
6982 * intel_dp_set_drrs_state - program registers for RR switch to take effect
6983 * @dev_priv: i915 device
6984 * @crtc_state: a pointer to the active intel_crtc_state
6985 * @refresh_rate: RR to be programmed
6986 *
6987 * This function gets called when refresh rate (RR) has to be changed from
6988 * one frequency to another. Switches can be between high and low RR
6989 * supported by the panel or to any other RR based on media playback (in
6990 * this case, RR value needs to be passed from user space).
6991 *
6992 * The caller of this function needs to take a lock on dev_priv->drrs.
6993 */
intel_dp_set_drrs_state(struct drm_i915_private * dev_priv,const struct intel_crtc_state * crtc_state,int refresh_rate)6994 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6995 const struct intel_crtc_state *crtc_state,
6996 int refresh_rate)
6997 {
6998 struct intel_dp *intel_dp = dev_priv->drrs.dp;
6999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7000 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7001
7002 if (refresh_rate <= 0) {
7003 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
7004 return;
7005 }
7006
7007 if (intel_dp == NULL) {
7008 DRM_DEBUG_KMS("DRRS not supported.\n");
7009 return;
7010 }
7011
7012 if (!intel_crtc) {
7013 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
7014 return;
7015 }
7016
7017 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7018 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
7019 return;
7020 }
7021
7022 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
7023 refresh_rate)
7024 index = DRRS_LOW_RR;
7025
7026 if (index == dev_priv->drrs.refresh_rate_type) {
7027 DRM_DEBUG_KMS(
7028 "DRRS requested for previously set RR...ignoring\n");
7029 return;
7030 }
7031
7032 if (!crtc_state->hw.active) {
7033 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
7034 return;
7035 }
7036
7037 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7038 switch (index) {
7039 case DRRS_HIGH_RR:
7040 intel_dp_set_m_n(crtc_state, M1_N1);
7041 break;
7042 case DRRS_LOW_RR:
7043 intel_dp_set_m_n(crtc_state, M2_N2);
7044 break;
7045 case DRRS_MAX_RR:
7046 default:
7047 DRM_ERROR("Unsupported refreshrate type\n");
7048 }
7049 } else if (INTEL_GEN(dev_priv) > 6) {
7050 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7051 u32 val;
7052
7053 val = I915_READ(reg);
7054 if (index > DRRS_HIGH_RR) {
7055 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7056 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7057 else
7058 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7059 } else {
7060 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7061 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7062 else
7063 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7064 }
7065 I915_WRITE(reg, val);
7066 }
7067
7068 dev_priv->drrs.refresh_rate_type = index;
7069
7070 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
7071 }
7072
7073 /**
7074 * intel_edp_drrs_enable - init drrs struct if supported
7075 * @intel_dp: DP struct
7076 * @crtc_state: A pointer to the active crtc state.
7077 *
7078 * Initializes frontbuffer_bits and drrs.dp
7079 */
intel_edp_drrs_enable(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)7080 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7081 const struct intel_crtc_state *crtc_state)
7082 {
7083 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7084
7085 if (!crtc_state->has_drrs) {
7086 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
7087 return;
7088 }
7089
7090 if (dev_priv->psr.enabled) {
7091 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
7092 return;
7093 }
7094
7095 mutex_lock(&dev_priv->drrs.mutex);
7096 if (dev_priv->drrs.dp) {
7097 DRM_DEBUG_KMS("DRRS already enabled\n");
7098 goto unlock;
7099 }
7100
7101 dev_priv->drrs.busy_frontbuffer_bits = 0;
7102
7103 dev_priv->drrs.dp = intel_dp;
7104
7105 unlock:
7106 mutex_unlock(&dev_priv->drrs.mutex);
7107 }
7108
7109 /**
7110 * intel_edp_drrs_disable - Disable DRRS
7111 * @intel_dp: DP struct
7112 * @old_crtc_state: Pointer to old crtc_state.
7113 *
7114 */
intel_edp_drrs_disable(struct intel_dp * intel_dp,const struct intel_crtc_state * old_crtc_state)7115 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7116 const struct intel_crtc_state *old_crtc_state)
7117 {
7118 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7119
7120 if (!old_crtc_state->has_drrs)
7121 return;
7122
7123 mutex_lock(&dev_priv->drrs.mutex);
7124 if (!dev_priv->drrs.dp) {
7125 mutex_unlock(&dev_priv->drrs.mutex);
7126 return;
7127 }
7128
7129 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7130 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
7131 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
7132
7133 dev_priv->drrs.dp = NULL;
7134 mutex_unlock(&dev_priv->drrs.mutex);
7135
7136 cancel_delayed_work_sync(&dev_priv->drrs.work);
7137 }
7138
intel_edp_drrs_downclock_work(struct work_struct * work)7139 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7140 {
7141 struct drm_i915_private *dev_priv =
7142 container_of(work, typeof(*dev_priv), drrs.work.work);
7143 struct intel_dp *intel_dp;
7144
7145 mutex_lock(&dev_priv->drrs.mutex);
7146
7147 intel_dp = dev_priv->drrs.dp;
7148
7149 if (!intel_dp)
7150 goto unlock;
7151
7152 /*
7153 * The delayed work can race with an invalidate hence we need to
7154 * recheck.
7155 */
7156
7157 if (dev_priv->drrs.busy_frontbuffer_bits)
7158 goto unlock;
7159
7160 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7161 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7162
7163 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7164 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
7165 }
7166
7167 unlock:
7168 mutex_unlock(&dev_priv->drrs.mutex);
7169 }
7170
7171 /**
7172 * intel_edp_drrs_invalidate - Disable Idleness DRRS
7173 * @dev_priv: i915 device
7174 * @frontbuffer_bits: frontbuffer plane tracking bits
7175 *
7176 * This function gets called everytime rendering on the given planes start.
7177 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7178 *
7179 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7180 */
intel_edp_drrs_invalidate(struct drm_i915_private * dev_priv,unsigned int frontbuffer_bits)7181 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7182 unsigned int frontbuffer_bits)
7183 {
7184 struct drm_crtc *crtc;
7185 enum pipe pipe;
7186
7187 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7188 return;
7189
7190 cancel_delayed_work(&dev_priv->drrs.work);
7191
7192 mutex_lock(&dev_priv->drrs.mutex);
7193 if (!dev_priv->drrs.dp) {
7194 mutex_unlock(&dev_priv->drrs.mutex);
7195 return;
7196 }
7197
7198 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7199 pipe = to_intel_crtc(crtc)->pipe;
7200
7201 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7202 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
7203
7204 /* invalidate means busy screen hence upclock */
7205 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7206 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7207 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7208
7209 mutex_unlock(&dev_priv->drrs.mutex);
7210 }
7211
7212 /**
7213 * intel_edp_drrs_flush - Restart Idleness DRRS
7214 * @dev_priv: i915 device
7215 * @frontbuffer_bits: frontbuffer plane tracking bits
7216 *
7217 * This function gets called every time rendering on the given planes has
7218 * completed or flip on a crtc is completed. So DRRS should be upclocked
7219 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
7220 * if no other planes are dirty.
7221 *
7222 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7223 */
intel_edp_drrs_flush(struct drm_i915_private * dev_priv,unsigned int frontbuffer_bits)7224 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
7225 unsigned int frontbuffer_bits)
7226 {
7227 struct drm_crtc *crtc;
7228 enum pipe pipe;
7229
7230 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7231 return;
7232
7233 cancel_delayed_work(&dev_priv->drrs.work);
7234
7235 mutex_lock(&dev_priv->drrs.mutex);
7236 if (!dev_priv->drrs.dp) {
7237 mutex_unlock(&dev_priv->drrs.mutex);
7238 return;
7239 }
7240
7241 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7242 pipe = to_intel_crtc(crtc)->pipe;
7243
7244 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7245 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
7246
7247 /* flush means busy screen hence upclock */
7248 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7249 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7250 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7251
7252 /*
7253 * flush also means no more activity hence schedule downclock, if all
7254 * other fbs are quiescent too
7255 */
7256 if (!dev_priv->drrs.busy_frontbuffer_bits)
7257 schedule_delayed_work(&dev_priv->drrs.work,
7258 msecs_to_jiffies(1000));
7259 mutex_unlock(&dev_priv->drrs.mutex);
7260 }
7261
7262 /**
7263 * DOC: Display Refresh Rate Switching (DRRS)
7264 *
7265 * Display Refresh Rate Switching (DRRS) is a power conservation feature
7266 * which enables swtching between low and high refresh rates,
7267 * dynamically, based on the usage scenario. This feature is applicable
7268 * for internal panels.
7269 *
7270 * Indication that the panel supports DRRS is given by the panel EDID, which
7271 * would list multiple refresh rates for one resolution.
7272 *
7273 * DRRS is of 2 types - static and seamless.
7274 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
7275 * (may appear as a blink on screen) and is used in dock-undock scenario.
7276 * Seamless DRRS involves changing RR without any visual effect to the user
7277 * and can be used during normal system usage. This is done by programming
7278 * certain registers.
7279 *
7280 * Support for static/seamless DRRS may be indicated in the VBT based on
7281 * inputs from the panel spec.
7282 *
7283 * DRRS saves power by switching to low RR based on usage scenarios.
7284 *
7285 * The implementation is based on frontbuffer tracking implementation. When
7286 * there is a disturbance on the screen triggered by user activity or a periodic
7287 * system activity, DRRS is disabled (RR is changed to high RR). When there is
7288 * no movement on screen, after a timeout of 1 second, a switch to low RR is
7289 * made.
7290 *
7291 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7292 * and intel_edp_drrs_flush() are called.
7293 *
7294 * DRRS can be further extended to support other internal panels and also
7295 * the scenario of video playback wherein RR is set based on the rate
7296 * requested by userspace.
7297 */
7298
7299 /**
7300 * intel_dp_drrs_init - Init basic DRRS work and mutex.
7301 * @connector: eDP connector
7302 * @fixed_mode: preferred mode of panel
7303 *
7304 * This function is called only once at driver load to initialize basic
7305 * DRRS stuff.
7306 *
7307 * Returns:
7308 * Downclock mode if panel supports it, else return NULL.
7309 * DRRS support is determined by the presence of downclock mode (apart
7310 * from VBT setting).
7311 */
7312 static struct drm_display_mode *
intel_dp_drrs_init(struct intel_connector * connector,struct drm_display_mode * fixed_mode)7313 intel_dp_drrs_init(struct intel_connector *connector,
7314 struct drm_display_mode *fixed_mode)
7315 {
7316 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7317 struct drm_display_mode *downclock_mode = NULL;
7318
7319 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7320
7321 if (INTEL_GEN(dev_priv) <= 6) {
7322 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
7323 return NULL;
7324 }
7325
7326 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7327 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
7328 return NULL;
7329 }
7330
7331 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7332 if (!downclock_mode) {
7333 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
7334 return NULL;
7335 }
7336
7337 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7338
7339 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7340 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
7341 return downclock_mode;
7342 }
7343
intel_edp_init_connector(struct intel_dp * intel_dp,struct intel_connector * intel_connector)7344 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7345 struct intel_connector *intel_connector)
7346 {
7347 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7348 struct drm_device *dev = &dev_priv->drm;
7349 struct drm_connector *connector = &intel_connector->base;
7350 struct drm_display_mode *fixed_mode = NULL;
7351 struct drm_display_mode *downclock_mode = NULL;
7352 bool has_dpcd;
7353 enum pipe pipe = INVALID_PIPE;
7354 intel_wakeref_t wakeref;
7355 struct edid *edid;
7356
7357 if (!intel_dp_is_edp(intel_dp))
7358 return true;
7359
7360 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7361
7362 /*
7363 * On IBX/CPT we may get here with LVDS already registered. Since the
7364 * driver uses the only internal power sequencer available for both
7365 * eDP and LVDS bail out early in this case to prevent interfering
7366 * with an already powered-on LVDS power sequencer.
7367 */
7368 if (intel_get_lvds_encoder(dev_priv)) {
7369 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7370 DRM_INFO("LVDS was detected, not registering eDP\n");
7371
7372 return false;
7373 }
7374
7375 with_pps_lock(intel_dp, wakeref) {
7376 intel_dp_init_panel_power_timestamps(intel_dp);
7377 intel_dp_pps_init(intel_dp);
7378 intel_edp_panel_vdd_sanitize(intel_dp);
7379 }
7380
7381 /* Cache DPCD and EDID for edp. */
7382 has_dpcd = intel_edp_init_dpcd(intel_dp);
7383
7384 if (!has_dpcd) {
7385 /* if this fails, presume the device is a ghost */
7386 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7387 goto out_vdd_off;
7388 }
7389
7390 mutex_lock(&dev->mode_config.mutex);
7391 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7392 if (edid) {
7393 if (drm_add_edid_modes(connector, edid)) {
7394 drm_connector_update_edid_property(connector,
7395 edid);
7396 } else {
7397 kfree(edid);
7398 edid = ERR_PTR(-EINVAL);
7399 }
7400 } else {
7401 edid = ERR_PTR(-ENOENT);
7402 }
7403 intel_connector->edid = edid;
7404
7405 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7406 if (fixed_mode)
7407 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7408
7409 /* fallback to VBT if available for eDP */
7410 if (!fixed_mode)
7411 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7412 mutex_unlock(&dev->mode_config.mutex);
7413
7414 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7415 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7416 register_reboot_notifier(&intel_dp->edp_notifier);
7417
7418 /*
7419 * Figure out the current pipe for the initial backlight setup.
7420 * If the current pipe isn't valid, try the PPS pipe, and if that
7421 * fails just assume pipe A.
7422 */
7423 pipe = vlv_active_pipe(intel_dp);
7424
7425 if (pipe != PIPE_A && pipe != PIPE_B)
7426 pipe = intel_dp->pps_pipe;
7427
7428 if (pipe != PIPE_A && pipe != PIPE_B)
7429 pipe = PIPE_A;
7430
7431 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7432 pipe_name(pipe));
7433 }
7434
7435 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7436 intel_connector->panel.backlight.power = intel_edp_backlight_power;
7437 intel_panel_setup_backlight(connector, pipe);
7438
7439 if (fixed_mode)
7440 drm_connector_init_panel_orientation_property(
7441 connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7442
7443 return true;
7444
7445 out_vdd_off:
7446 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7447 /*
7448 * vdd might still be enabled do to the delayed vdd off.
7449 * Make sure vdd is actually turned off here.
7450 */
7451 with_pps_lock(intel_dp, wakeref)
7452 edp_panel_vdd_off_sync(intel_dp);
7453
7454 return false;
7455 }
7456
intel_dp_modeset_retry_work_fn(struct work_struct * work)7457 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7458 {
7459 struct intel_connector *intel_connector;
7460 struct drm_connector *connector;
7461
7462 intel_connector = container_of(work, typeof(*intel_connector),
7463 modeset_retry_work);
7464 connector = &intel_connector->base;
7465 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7466 connector->name);
7467
7468 /* Grab the locks before changing connector property*/
7469 mutex_lock(&connector->dev->mode_config.mutex);
7470 /* Set connector link status to BAD and send a Uevent to notify
7471 * userspace to do a modeset.
7472 */
7473 drm_connector_set_link_status_property(connector,
7474 DRM_MODE_LINK_STATUS_BAD);
7475 mutex_unlock(&connector->dev->mode_config.mutex);
7476 /* Send Hotplug uevent so userspace can reprobe */
7477 drm_kms_helper_hotplug_event(connector->dev);
7478 }
7479
7480 bool
intel_dp_init_connector(struct intel_digital_port * intel_dig_port,struct intel_connector * intel_connector)7481 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7482 struct intel_connector *intel_connector)
7483 {
7484 struct drm_connector *connector = &intel_connector->base;
7485 struct intel_dp *intel_dp = &intel_dig_port->dp;
7486 struct intel_encoder *intel_encoder = &intel_dig_port->base;
7487 struct drm_device *dev = intel_encoder->base.dev;
7488 struct drm_i915_private *dev_priv = to_i915(dev);
7489 enum port port = intel_encoder->port;
7490 enum phy phy = intel_port_to_phy(dev_priv, port);
7491 int type;
7492
7493 /* Initialize the work for modeset in case of link train failure */
7494 INIT_WORK(&intel_connector->modeset_retry_work,
7495 intel_dp_modeset_retry_work_fn);
7496
7497 if (WARN(intel_dig_port->max_lanes < 1,
7498 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
7499 intel_dig_port->max_lanes, intel_encoder->base.base.id,
7500 intel_encoder->base.name))
7501 return false;
7502
7503 intel_dp_set_source_rates(intel_dp);
7504
7505 intel_dp->reset_link_params = true;
7506 intel_dp->pps_pipe = INVALID_PIPE;
7507 intel_dp->active_pipe = INVALID_PIPE;
7508
7509 /* Preserve the current hw state. */
7510 intel_dp->DP = I915_READ(intel_dp->output_reg);
7511 intel_dp->attached_connector = intel_connector;
7512
7513 if (intel_dp_is_port_edp(dev_priv, port)) {
7514 /*
7515 * Currently we don't support eDP on TypeC ports, although in
7516 * theory it could work on TypeC legacy ports.
7517 */
7518 WARN_ON(intel_phy_is_tc(dev_priv, phy));
7519 type = DRM_MODE_CONNECTOR_eDP;
7520 } else {
7521 type = DRM_MODE_CONNECTOR_DisplayPort;
7522 }
7523
7524 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7525 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7526
7527 /*
7528 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7529 * for DP the encoder type can be set by the caller to
7530 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7531 */
7532 if (type == DRM_MODE_CONNECTOR_eDP)
7533 intel_encoder->type = INTEL_OUTPUT_EDP;
7534
7535 /* eDP only on port B and/or C on vlv/chv */
7536 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7537 intel_dp_is_edp(intel_dp) &&
7538 port != PORT_B && port != PORT_C))
7539 return false;
7540
7541 DRM_DEBUG_KMS("Adding %s connector on [ENCODER:%d:%s]\n",
7542 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7543 intel_encoder->base.base.id, intel_encoder->base.name);
7544
7545 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7546 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7547
7548 if (!HAS_GMCH(dev_priv))
7549 connector->interlace_allowed = true;
7550 connector->doublescan_allowed = 0;
7551
7552 if (INTEL_GEN(dev_priv) >= 11)
7553 connector->ycbcr_420_allowed = true;
7554
7555 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7556
7557 intel_dp_aux_init(intel_dp);
7558
7559 intel_connector_attach_encoder(intel_connector, intel_encoder);
7560
7561 if (HAS_DDI(dev_priv))
7562 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7563 else
7564 intel_connector->get_hw_state = intel_connector_get_hw_state;
7565
7566 /* init MST on ports that can support it */
7567 intel_dp_mst_encoder_init(intel_dig_port,
7568 intel_connector->base.base.id);
7569
7570 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7571 intel_dp_aux_fini(intel_dp);
7572 intel_dp_mst_encoder_cleanup(intel_dig_port);
7573 goto fail;
7574 }
7575
7576 intel_dp_add_properties(intel_dp, connector);
7577
7578 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7579 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7580 if (ret)
7581 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7582 }
7583
7584 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7585 * 0xd. Failure to do so will result in spurious interrupts being
7586 * generated on the port when a cable is not attached.
7587 */
7588 if (IS_G45(dev_priv)) {
7589 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
7590 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
7591 }
7592
7593 return true;
7594
7595 fail:
7596 drm_connector_cleanup(connector);
7597
7598 return false;
7599 }
7600
intel_dp_init(struct drm_i915_private * dev_priv,i915_reg_t output_reg,enum port port)7601 bool intel_dp_init(struct drm_i915_private *dev_priv,
7602 i915_reg_t output_reg,
7603 enum port port)
7604 {
7605 struct intel_digital_port *intel_dig_port;
7606 struct intel_encoder *intel_encoder;
7607 struct drm_encoder *encoder;
7608 struct intel_connector *intel_connector;
7609
7610 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7611 if (!intel_dig_port)
7612 return false;
7613
7614 intel_connector = intel_connector_alloc();
7615 if (!intel_connector)
7616 goto err_connector_alloc;
7617
7618 intel_encoder = &intel_dig_port->base;
7619 encoder = &intel_encoder->base;
7620
7621 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7622 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7623 "DP %c", port_name(port)))
7624 goto err_encoder_init;
7625
7626 intel_encoder->hotplug = intel_dp_hotplug;
7627 intel_encoder->compute_config = intel_dp_compute_config;
7628 intel_encoder->get_hw_state = intel_dp_get_hw_state;
7629 intel_encoder->get_config = intel_dp_get_config;
7630 intel_encoder->update_pipe = intel_panel_update_backlight;
7631 intel_encoder->suspend = intel_dp_encoder_suspend;
7632 if (IS_CHERRYVIEW(dev_priv)) {
7633 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7634 intel_encoder->pre_enable = chv_pre_enable_dp;
7635 intel_encoder->enable = vlv_enable_dp;
7636 intel_encoder->disable = vlv_disable_dp;
7637 intel_encoder->post_disable = chv_post_disable_dp;
7638 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7639 } else if (IS_VALLEYVIEW(dev_priv)) {
7640 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7641 intel_encoder->pre_enable = vlv_pre_enable_dp;
7642 intel_encoder->enable = vlv_enable_dp;
7643 intel_encoder->disable = vlv_disable_dp;
7644 intel_encoder->post_disable = vlv_post_disable_dp;
7645 } else {
7646 intel_encoder->pre_enable = g4x_pre_enable_dp;
7647 intel_encoder->enable = g4x_enable_dp;
7648 intel_encoder->disable = g4x_disable_dp;
7649 intel_encoder->post_disable = g4x_post_disable_dp;
7650 }
7651
7652 intel_dig_port->dp.output_reg = output_reg;
7653 intel_dig_port->max_lanes = 4;
7654
7655 intel_encoder->type = INTEL_OUTPUT_DP;
7656 intel_encoder->power_domain = intel_port_to_power_domain(port);
7657 if (IS_CHERRYVIEW(dev_priv)) {
7658 if (port == PORT_D)
7659 intel_encoder->pipe_mask = BIT(PIPE_C);
7660 else
7661 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
7662 } else {
7663 intel_encoder->pipe_mask = ~0;
7664 }
7665 intel_encoder->cloneable = 0;
7666 intel_encoder->port = port;
7667
7668 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7669
7670 if (port != PORT_A)
7671 intel_infoframe_init(intel_dig_port);
7672
7673 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7674 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7675 goto err_init_connector;
7676
7677 return true;
7678
7679 err_init_connector:
7680 drm_encoder_cleanup(encoder);
7681 err_encoder_init:
7682 kfree(intel_connector);
7683 err_connector_alloc:
7684 kfree(intel_dig_port);
7685 return false;
7686 }
7687
intel_dp_mst_suspend(struct drm_i915_private * dev_priv)7688 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7689 {
7690 struct intel_encoder *encoder;
7691
7692 for_each_intel_encoder(&dev_priv->drm, encoder) {
7693 struct intel_dp *intel_dp;
7694
7695 if (encoder->type != INTEL_OUTPUT_DDI)
7696 continue;
7697
7698 intel_dp = enc_to_intel_dp(encoder);
7699
7700 if (!intel_dp->can_mst)
7701 continue;
7702
7703 if (intel_dp->is_mst)
7704 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7705 }
7706 }
7707
intel_dp_mst_resume(struct drm_i915_private * dev_priv)7708 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7709 {
7710 struct intel_encoder *encoder;
7711
7712 for_each_intel_encoder(&dev_priv->drm, encoder) {
7713 struct intel_dp *intel_dp;
7714 int ret;
7715
7716 if (encoder->type != INTEL_OUTPUT_DDI)
7717 continue;
7718
7719 intel_dp = enc_to_intel_dp(encoder);
7720
7721 if (!intel_dp->can_mst)
7722 continue;
7723
7724 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
7725 true);
7726 if (ret) {
7727 intel_dp->is_mst = false;
7728 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7729 false);
7730 }
7731 }
7732 }
7733