xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/intel_audio.c (revision dfa0e026b754eb1035e5de7f65af7fb7cbdae3b8)
1 /*	$NetBSD: intel_audio.c,v 1.3 2021/12/19 11:38:03 riastradh Exp $	*/
2 
3 /*
4  * Copyright © 2014 Intel Corporation
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  */
25 
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: intel_audio.c,v 1.3 2021/12/19 11:38:03 riastradh Exp $");
28 
29 #include <linux/component.h>
30 #include <linux/kernel.h>
31 
32 #include <drm/drm_edid.h>
33 #include <drm/i915_component.h>
34 
35 #include "i915_drv.h"
36 #include "intel_atomic.h"
37 #include "intel_audio.h"
38 #include "intel_display_types.h"
39 #include "intel_lpe_audio.h"
40 
41 /**
42  * DOC: High Definition Audio over HDMI and Display Port
43  *
44  * The graphics and audio drivers together support High Definition Audio over
45  * HDMI and Display Port. The audio programming sequences are divided into audio
46  * codec and controller enable and disable sequences. The graphics driver
47  * handles the audio codec sequences, while the audio driver handles the audio
48  * controller sequences.
49  *
50  * The disable sequences must be performed before disabling the transcoder or
51  * port. The enable sequences may only be performed after enabling the
52  * transcoder and port, and after completed link training. Therefore the audio
53  * enable/disable sequences are part of the modeset sequence.
54  *
55  * The codec and controller sequences could be done either parallel or serial,
56  * but generally the ELDV/PD change in the codec sequence indicates to the audio
57  * driver that the controller sequence should start. Indeed, most of the
58  * co-operation between the graphics and audio drivers is handled via audio
59  * related registers. (The notable exception is the power management, not
60  * covered here.)
61  *
62  * The struct &i915_audio_component is used to interact between the graphics
63  * and audio drivers. The struct &i915_audio_component_ops @ops in it is
64  * defined in graphics driver and called in audio driver. The
65  * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
66  */
67 
68 /* DP N/M table */
69 #define LC_810M	810000
70 #define LC_540M	540000
71 #define LC_270M	270000
72 #define LC_162M	162000
73 
74 struct dp_aud_n_m {
75 	int sample_rate;
76 	int clock;
77 	u16 m;
78 	u16 n;
79 };
80 
81 struct hdmi_aud_ncts {
82 	int sample_rate;
83 	int clock;
84 	int n;
85 	int cts;
86 };
87 
88 /* Values according to DP 1.4 Table 2-104 */
89 static const struct dp_aud_n_m dp_aud_n_m[] = {
90 	{ 32000, LC_162M, 1024, 10125 },
91 	{ 44100, LC_162M, 784, 5625 },
92 	{ 48000, LC_162M, 512, 3375 },
93 	{ 64000, LC_162M, 2048, 10125 },
94 	{ 88200, LC_162M, 1568, 5625 },
95 	{ 96000, LC_162M, 1024, 3375 },
96 	{ 128000, LC_162M, 4096, 10125 },
97 	{ 176400, LC_162M, 3136, 5625 },
98 	{ 192000, LC_162M, 2048, 3375 },
99 	{ 32000, LC_270M, 1024, 16875 },
100 	{ 44100, LC_270M, 784, 9375 },
101 	{ 48000, LC_270M, 512, 5625 },
102 	{ 64000, LC_270M, 2048, 16875 },
103 	{ 88200, LC_270M, 1568, 9375 },
104 	{ 96000, LC_270M, 1024, 5625 },
105 	{ 128000, LC_270M, 4096, 16875 },
106 	{ 176400, LC_270M, 3136, 9375 },
107 	{ 192000, LC_270M, 2048, 5625 },
108 	{ 32000, LC_540M, 1024, 33750 },
109 	{ 44100, LC_540M, 784, 18750 },
110 	{ 48000, LC_540M, 512, 11250 },
111 	{ 64000, LC_540M, 2048, 33750 },
112 	{ 88200, LC_540M, 1568, 18750 },
113 	{ 96000, LC_540M, 1024, 11250 },
114 	{ 128000, LC_540M, 4096, 33750 },
115 	{ 176400, LC_540M, 3136, 18750 },
116 	{ 192000, LC_540M, 2048, 11250 },
117 	{ 32000, LC_810M, 1024, 50625 },
118 	{ 44100, LC_810M, 784, 28125 },
119 	{ 48000, LC_810M, 512, 16875 },
120 	{ 64000, LC_810M, 2048, 50625 },
121 	{ 88200, LC_810M, 1568, 28125 },
122 	{ 96000, LC_810M, 1024, 16875 },
123 	{ 128000, LC_810M, 4096, 50625 },
124 	{ 176400, LC_810M, 3136, 28125 },
125 	{ 192000, LC_810M, 2048, 16875 },
126 };
127 
128 static const struct dp_aud_n_m *
audio_config_dp_get_n_m(const struct intel_crtc_state * crtc_state,int rate)129 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
130 {
131 	int i;
132 
133 	for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
134 		if (rate == dp_aud_n_m[i].sample_rate &&
135 		    crtc_state->port_clock == dp_aud_n_m[i].clock)
136 			return &dp_aud_n_m[i];
137 	}
138 
139 	return NULL;
140 }
141 
142 static const struct {
143 	int clock;
144 	u32 config;
145 } hdmi_audio_clock[] = {
146 	{ 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
147 	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
148 	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
149 	{ 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
150 	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
151 	{ 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
152 	{ 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
153 	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
154 	{ 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
155 	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
156 };
157 
158 /* HDMI N/CTS table */
159 #define TMDS_297M 297000
160 #define TMDS_296M 296703
161 #define TMDS_594M 594000
162 #define TMDS_593M 593407
163 
164 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
165 	{ 32000, TMDS_296M, 5824, 421875 },
166 	{ 32000, TMDS_297M, 3072, 222750 },
167 	{ 32000, TMDS_593M, 5824, 843750 },
168 	{ 32000, TMDS_594M, 3072, 445500 },
169 	{ 44100, TMDS_296M, 4459, 234375 },
170 	{ 44100, TMDS_297M, 4704, 247500 },
171 	{ 44100, TMDS_593M, 8918, 937500 },
172 	{ 44100, TMDS_594M, 9408, 990000 },
173 	{ 88200, TMDS_296M, 8918, 234375 },
174 	{ 88200, TMDS_297M, 9408, 247500 },
175 	{ 88200, TMDS_593M, 17836, 937500 },
176 	{ 88200, TMDS_594M, 18816, 990000 },
177 	{ 176400, TMDS_296M, 17836, 234375 },
178 	{ 176400, TMDS_297M, 18816, 247500 },
179 	{ 176400, TMDS_593M, 35672, 937500 },
180 	{ 176400, TMDS_594M, 37632, 990000 },
181 	{ 48000, TMDS_296M, 5824, 281250 },
182 	{ 48000, TMDS_297M, 5120, 247500 },
183 	{ 48000, TMDS_593M, 5824, 562500 },
184 	{ 48000, TMDS_594M, 6144, 594000 },
185 	{ 96000, TMDS_296M, 11648, 281250 },
186 	{ 96000, TMDS_297M, 10240, 247500 },
187 	{ 96000, TMDS_593M, 11648, 562500 },
188 	{ 96000, TMDS_594M, 12288, 594000 },
189 	{ 192000, TMDS_296M, 23296, 281250 },
190 	{ 192000, TMDS_297M, 20480, 247500 },
191 	{ 192000, TMDS_593M, 23296, 562500 },
192 	{ 192000, TMDS_594M, 24576, 594000 },
193 };
194 
195 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
196 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
197 #define TMDS_371M 371250
198 #define TMDS_370M 370878
199 
200 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
201 	{ 32000, TMDS_370M, 5824, 527344 },
202 	{ 32000, TMDS_371M, 6144, 556875 },
203 	{ 44100, TMDS_370M, 8918, 585938 },
204 	{ 44100, TMDS_371M, 4704, 309375 },
205 	{ 88200, TMDS_370M, 17836, 585938 },
206 	{ 88200, TMDS_371M, 9408, 309375 },
207 	{ 176400, TMDS_370M, 35672, 585938 },
208 	{ 176400, TMDS_371M, 18816, 309375 },
209 	{ 48000, TMDS_370M, 11648, 703125 },
210 	{ 48000, TMDS_371M, 5120, 309375 },
211 	{ 96000, TMDS_370M, 23296, 703125 },
212 	{ 96000, TMDS_371M, 10240, 309375 },
213 	{ 192000, TMDS_370M, 46592, 703125 },
214 	{ 192000, TMDS_371M, 20480, 309375 },
215 };
216 
217 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
218 #define TMDS_445_5M 445500
219 #define TMDS_445M 445054
220 
221 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
222 	{ 32000, TMDS_445M, 5824, 632813 },
223 	{ 32000, TMDS_445_5M, 4096, 445500 },
224 	{ 44100, TMDS_445M, 8918, 703125 },
225 	{ 44100, TMDS_445_5M, 4704, 371250 },
226 	{ 88200, TMDS_445M, 17836, 703125 },
227 	{ 88200, TMDS_445_5M, 9408, 371250 },
228 	{ 176400, TMDS_445M, 35672, 703125 },
229 	{ 176400, TMDS_445_5M, 18816, 371250 },
230 	{ 48000, TMDS_445M, 5824, 421875 },
231 	{ 48000, TMDS_445_5M, 5120, 371250 },
232 	{ 96000, TMDS_445M, 11648, 421875 },
233 	{ 96000, TMDS_445_5M, 10240, 371250 },
234 	{ 192000, TMDS_445M, 23296, 421875 },
235 	{ 192000, TMDS_445_5M, 20480, 371250 },
236 };
237 
238 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
audio_config_hdmi_pixel_clock(const struct intel_crtc_state * crtc_state)239 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
240 {
241 	const struct drm_display_mode *adjusted_mode =
242 		&crtc_state->hw.adjusted_mode;
243 	int i;
244 
245 	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
246 		if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
247 			break;
248 	}
249 
250 	if (i == ARRAY_SIZE(hdmi_audio_clock)) {
251 		DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
252 			      adjusted_mode->crtc_clock);
253 		i = 1;
254 	}
255 
256 	DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
257 		      hdmi_audio_clock[i].clock,
258 		      hdmi_audio_clock[i].config);
259 
260 	return hdmi_audio_clock[i].config;
261 }
262 
audio_config_hdmi_get_n(const struct intel_crtc_state * crtc_state,int rate)263 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
264 				   int rate)
265 {
266 	const struct hdmi_aud_ncts *hdmi_ncts_table;
267 	int i, size;
268 
269 	if (crtc_state->pipe_bpp == 36) {
270 		hdmi_ncts_table = hdmi_aud_ncts_36bpp;
271 		size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
272 	} else if (crtc_state->pipe_bpp == 30) {
273 		hdmi_ncts_table = hdmi_aud_ncts_30bpp;
274 		size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
275 	} else {
276 		hdmi_ncts_table = hdmi_aud_ncts_24bpp;
277 		size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
278 	}
279 
280 	for (i = 0; i < size; i++) {
281 		if (rate == hdmi_ncts_table[i].sample_rate &&
282 		    crtc_state->port_clock == hdmi_ncts_table[i].clock) {
283 			return hdmi_ncts_table[i].n;
284 		}
285 	}
286 	return 0;
287 }
288 
intel_eld_uptodate(struct drm_connector * connector,i915_reg_t reg_eldv,u32 bits_eldv,i915_reg_t reg_elda,u32 bits_elda,i915_reg_t reg_edid)289 static bool intel_eld_uptodate(struct drm_connector *connector,
290 			       i915_reg_t reg_eldv, u32 bits_eldv,
291 			       i915_reg_t reg_elda, u32 bits_elda,
292 			       i915_reg_t reg_edid)
293 {
294 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
295 	const u8 *eld = connector->eld;
296 	u32 tmp;
297 	int i;
298 
299 	tmp = I915_READ(reg_eldv);
300 	tmp &= bits_eldv;
301 
302 	if (!tmp)
303 		return false;
304 
305 	tmp = I915_READ(reg_elda);
306 	tmp &= ~bits_elda;
307 	I915_WRITE(reg_elda, tmp);
308 
309 	for (i = 0; i < drm_eld_size(eld) / 4; i++)
310 		if (I915_READ(reg_edid) != *((const u32 *)eld + i))
311 			return false;
312 
313 	return true;
314 }
315 
g4x_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)316 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
317 				    const struct intel_crtc_state *old_crtc_state,
318 				    const struct drm_connector_state *old_conn_state)
319 {
320 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
321 	u32 eldv, tmp;
322 
323 	DRM_DEBUG_KMS("Disable audio codec\n");
324 
325 	tmp = I915_READ(G4X_AUD_VID_DID);
326 	if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
327 		eldv = G4X_ELDV_DEVCL_DEVBLC;
328 	else
329 		eldv = G4X_ELDV_DEVCTG;
330 
331 	/* Invalidate ELD */
332 	tmp = I915_READ(G4X_AUD_CNTL_ST);
333 	tmp &= ~eldv;
334 	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
335 }
336 
g4x_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)337 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
338 				   const struct intel_crtc_state *crtc_state,
339 				   const struct drm_connector_state *conn_state)
340 {
341 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
342 	struct drm_connector *connector = conn_state->connector;
343 	const u8 *eld = connector->eld;
344 	u32 eldv;
345 	u32 tmp;
346 	int len, i;
347 
348 	DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld));
349 
350 	tmp = I915_READ(G4X_AUD_VID_DID);
351 	if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
352 		eldv = G4X_ELDV_DEVCL_DEVBLC;
353 	else
354 		eldv = G4X_ELDV_DEVCTG;
355 
356 	if (intel_eld_uptodate(connector,
357 			       G4X_AUD_CNTL_ST, eldv,
358 			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
359 			       G4X_HDMIW_HDMIEDID))
360 		return;
361 
362 	tmp = I915_READ(G4X_AUD_CNTL_ST);
363 	tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
364 	len = (tmp >> 9) & 0x1f;		/* ELD buffer size */
365 	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
366 
367 	len = min(drm_eld_size(eld) / 4, len);
368 	DRM_DEBUG_DRIVER("ELD size %d\n", len);
369 	for (i = 0; i < len; i++)
370 		I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i));
371 
372 	tmp = I915_READ(G4X_AUD_CNTL_ST);
373 	tmp |= eldv;
374 	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
375 }
376 
377 static void
hsw_dp_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)378 hsw_dp_audio_config_update(struct intel_encoder *encoder,
379 			   const struct intel_crtc_state *crtc_state)
380 {
381 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
382 	struct i915_audio_component *acomp = dev_priv->audio_component;
383 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
384 	enum port port = encoder->port;
385 	const struct dp_aud_n_m *nm;
386 	int rate;
387 	u32 tmp;
388 
389 	rate = acomp ? acomp->aud_sample_rate[port] : 0;
390 	nm = audio_config_dp_get_n_m(crtc_state, rate);
391 	if (nm)
392 		DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
393 	else
394 		DRM_DEBUG_KMS("using automatic Maud, Naud\n");
395 
396 	tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
397 	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
398 	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
399 	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
400 	tmp |= AUD_CONFIG_N_VALUE_INDEX;
401 
402 	if (nm) {
403 		tmp &= ~AUD_CONFIG_N_MASK;
404 		tmp |= AUD_CONFIG_N(nm->n);
405 		tmp |= AUD_CONFIG_N_PROG_ENABLE;
406 	}
407 
408 	I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
409 
410 	tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
411 	tmp &= ~AUD_CONFIG_M_MASK;
412 	tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
413 	tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
414 
415 	if (nm) {
416 		tmp |= nm->m;
417 		tmp |= AUD_M_CTS_M_VALUE_INDEX;
418 		tmp |= AUD_M_CTS_M_PROG_ENABLE;
419 	}
420 
421 	I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
422 }
423 
424 static void
hsw_hdmi_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)425 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
426 			     const struct intel_crtc_state *crtc_state)
427 {
428 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
429 	struct i915_audio_component *acomp = dev_priv->audio_component;
430 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
431 	enum port port = encoder->port;
432 	int n, rate;
433 	u32 tmp;
434 
435 	rate = acomp ? acomp->aud_sample_rate[port] : 0;
436 
437 	tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
438 	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
439 	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
440 	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
441 	tmp |= audio_config_hdmi_pixel_clock(crtc_state);
442 
443 	n = audio_config_hdmi_get_n(crtc_state, rate);
444 	if (n != 0) {
445 		DRM_DEBUG_KMS("using N %d\n", n);
446 
447 		tmp &= ~AUD_CONFIG_N_MASK;
448 		tmp |= AUD_CONFIG_N(n);
449 		tmp |= AUD_CONFIG_N_PROG_ENABLE;
450 	} else {
451 		DRM_DEBUG_KMS("using automatic N\n");
452 	}
453 
454 	I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
455 
456 	/*
457 	 * Let's disable "Enable CTS or M Prog bit"
458 	 * and let HW calculate the value
459 	 */
460 	tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
461 	tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
462 	tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
463 	I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
464 }
465 
466 static void
hsw_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)467 hsw_audio_config_update(struct intel_encoder *encoder,
468 			const struct intel_crtc_state *crtc_state)
469 {
470 	if (intel_crtc_has_dp_encoder(crtc_state))
471 		hsw_dp_audio_config_update(encoder, crtc_state);
472 	else
473 		hsw_hdmi_audio_config_update(encoder, crtc_state);
474 }
475 
hsw_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)476 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
477 				    const struct intel_crtc_state *old_crtc_state,
478 				    const struct drm_connector_state *old_conn_state)
479 {
480 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
481 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
482 	u32 tmp;
483 
484 	DRM_DEBUG_KMS("Disable audio codec on transcoder %s\n",
485 		      transcoder_name(cpu_transcoder));
486 
487 	mutex_lock(&dev_priv->av_mutex);
488 
489 	/* Disable timestamps */
490 	tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
491 	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
492 	tmp |= AUD_CONFIG_N_PROG_ENABLE;
493 	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
494 	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
495 	if (intel_crtc_has_dp_encoder(old_crtc_state))
496 		tmp |= AUD_CONFIG_N_VALUE_INDEX;
497 	I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
498 
499 	/* Invalidate ELD */
500 	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
501 	tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
502 	tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
503 	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
504 
505 	mutex_unlock(&dev_priv->av_mutex);
506 }
507 
hsw_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)508 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
509 				   const struct intel_crtc_state *crtc_state,
510 				   const struct drm_connector_state *conn_state)
511 {
512 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
513 	struct drm_connector *connector = conn_state->connector;
514 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
515 	const u8 *eld = connector->eld;
516 	u32 tmp;
517 	int len, i;
518 
519 	DRM_DEBUG_KMS("Enable audio codec on transcoder %s, %u bytes ELD\n",
520 		      transcoder_name(cpu_transcoder), drm_eld_size(eld));
521 
522 	mutex_lock(&dev_priv->av_mutex);
523 
524 	/* Enable audio presence detect, invalidate ELD */
525 	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
526 	tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
527 	tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
528 	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
529 
530 	/*
531 	 * FIXME: We're supposed to wait for vblank here, but we have vblanks
532 	 * disabled during the mode set. The proper fix would be to push the
533 	 * rest of the setup into a vblank work item, queued here, but the
534 	 * infrastructure is not there yet.
535 	 */
536 
537 	/* Reset ELD write address */
538 	tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder));
539 	tmp &= ~IBX_ELD_ADDRESS_MASK;
540 	I915_WRITE(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
541 
542 	/* Up to 84 bytes of hw ELD buffer */
543 	len = min(drm_eld_size(eld), 84);
544 	for (i = 0; i < len / 4; i++)
545 		I915_WRITE(HSW_AUD_EDID_DATA(cpu_transcoder), *((const u32 *)eld + i));
546 
547 	/* ELD valid */
548 	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
549 	tmp |= AUDIO_ELD_VALID(cpu_transcoder);
550 	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
551 
552 	/* Enable timestamps */
553 	hsw_audio_config_update(encoder, crtc_state);
554 
555 	mutex_unlock(&dev_priv->av_mutex);
556 }
557 
ilk_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)558 static void ilk_audio_codec_disable(struct intel_encoder *encoder,
559 				    const struct intel_crtc_state *old_crtc_state,
560 				    const struct drm_connector_state *old_conn_state)
561 {
562 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
563 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
564 	enum pipe pipe = crtc->pipe;
565 	enum port port = encoder->port;
566 	u32 tmp, eldv;
567 	i915_reg_t aud_config, aud_cntrl_st2;
568 
569 	DRM_DEBUG_KMS("Disable audio codec on [ENCODER:%d:%s], pipe %c\n",
570 		      encoder->base.base.id, encoder->base.name,
571 		      pipe_name(pipe));
572 
573 	if (WARN_ON(port == PORT_A))
574 		return;
575 
576 	if (HAS_PCH_IBX(dev_priv)) {
577 		aud_config = IBX_AUD_CFG(pipe);
578 		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
579 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
580 		aud_config = VLV_AUD_CFG(pipe);
581 		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
582 	} else {
583 		aud_config = CPT_AUD_CFG(pipe);
584 		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
585 	}
586 
587 	/* Disable timestamps */
588 	tmp = I915_READ(aud_config);
589 	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
590 	tmp |= AUD_CONFIG_N_PROG_ENABLE;
591 	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
592 	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
593 	if (intel_crtc_has_dp_encoder(old_crtc_state))
594 		tmp |= AUD_CONFIG_N_VALUE_INDEX;
595 	I915_WRITE(aud_config, tmp);
596 
597 	eldv = IBX_ELD_VALID(port);
598 
599 	/* Invalidate ELD */
600 	tmp = I915_READ(aud_cntrl_st2);
601 	tmp &= ~eldv;
602 	I915_WRITE(aud_cntrl_st2, tmp);
603 }
604 
ilk_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)605 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
606 				   const struct intel_crtc_state *crtc_state,
607 				   const struct drm_connector_state *conn_state)
608 {
609 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
610 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
611 	struct drm_connector *connector = conn_state->connector;
612 	enum pipe pipe = crtc->pipe;
613 	enum port port = encoder->port;
614 	const u8 *eld = connector->eld;
615 	u32 tmp, eldv;
616 	int len, i;
617 	i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
618 
619 	DRM_DEBUG_KMS("Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n",
620 		      encoder->base.base.id, encoder->base.name,
621 		      pipe_name(pipe), drm_eld_size(eld));
622 
623 	if (WARN_ON(port == PORT_A))
624 		return;
625 
626 	/*
627 	 * FIXME: We're supposed to wait for vblank here, but we have vblanks
628 	 * disabled during the mode set. The proper fix would be to push the
629 	 * rest of the setup into a vblank work item, queued here, but the
630 	 * infrastructure is not there yet.
631 	 */
632 
633 	if (HAS_PCH_IBX(dev_priv)) {
634 		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
635 		aud_config = IBX_AUD_CFG(pipe);
636 		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
637 		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
638 	} else if (IS_VALLEYVIEW(dev_priv) ||
639 		   IS_CHERRYVIEW(dev_priv)) {
640 		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
641 		aud_config = VLV_AUD_CFG(pipe);
642 		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
643 		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
644 	} else {
645 		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
646 		aud_config = CPT_AUD_CFG(pipe);
647 		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
648 		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
649 	}
650 
651 	eldv = IBX_ELD_VALID(port);
652 
653 	/* Invalidate ELD */
654 	tmp = I915_READ(aud_cntrl_st2);
655 	tmp &= ~eldv;
656 	I915_WRITE(aud_cntrl_st2, tmp);
657 
658 	/* Reset ELD write address */
659 	tmp = I915_READ(aud_cntl_st);
660 	tmp &= ~IBX_ELD_ADDRESS_MASK;
661 	I915_WRITE(aud_cntl_st, tmp);
662 
663 	/* Up to 84 bytes of hw ELD buffer */
664 	len = min(drm_eld_size(eld), 84);
665 	for (i = 0; i < len / 4; i++)
666 		I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i));
667 
668 	/* ELD valid */
669 	tmp = I915_READ(aud_cntrl_st2);
670 	tmp |= eldv;
671 	I915_WRITE(aud_cntrl_st2, tmp);
672 
673 	/* Enable timestamps */
674 	tmp = I915_READ(aud_config);
675 	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
676 	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
677 	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
678 	if (intel_crtc_has_dp_encoder(crtc_state))
679 		tmp |= AUD_CONFIG_N_VALUE_INDEX;
680 	else
681 		tmp |= audio_config_hdmi_pixel_clock(crtc_state);
682 	I915_WRITE(aud_config, tmp);
683 }
684 
685 /**
686  * intel_audio_codec_enable - Enable the audio codec for HD audio
687  * @encoder: encoder on which to enable audio
688  * @crtc_state: pointer to the current crtc state.
689  * @conn_state: pointer to the current connector state.
690  *
691  * The enable sequences may only be performed after enabling the transcoder and
692  * port, and after completed link training.
693  */
intel_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)694 void intel_audio_codec_enable(struct intel_encoder *encoder,
695 			      const struct intel_crtc_state *crtc_state,
696 			      const struct drm_connector_state *conn_state)
697 {
698 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
699 	struct i915_audio_component *acomp = dev_priv->audio_component;
700 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
701 	struct drm_connector *connector = conn_state->connector;
702 	const struct drm_display_mode *adjusted_mode =
703 		&crtc_state->hw.adjusted_mode;
704 	enum port port = encoder->port;
705 	enum pipe pipe = crtc->pipe;
706 
707 	/* FIXME precompute the ELD in .compute_config() */
708 	if (!connector->eld[0])
709 		DRM_DEBUG_KMS("Bogus ELD on [CONNECTOR:%d:%s]\n",
710 			      connector->base.id, connector->name);
711 
712 	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
713 			 connector->base.id,
714 			 connector->name,
715 			 encoder->base.base.id,
716 			 encoder->base.name);
717 
718 	connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
719 
720 	if (dev_priv->display.audio_codec_enable)
721 		dev_priv->display.audio_codec_enable(encoder,
722 						     crtc_state,
723 						     conn_state);
724 
725 	mutex_lock(&dev_priv->av_mutex);
726 	encoder->audio_connector = connector;
727 
728 	/* referred in audio callbacks */
729 	dev_priv->av_enc_map[pipe] = encoder;
730 	mutex_unlock(&dev_priv->av_mutex);
731 
732 	if (acomp && acomp->base.audio_ops &&
733 	    acomp->base.audio_ops->pin_eld_notify) {
734 		/* audio drivers expect pipe = -1 to indicate Non-MST cases */
735 		if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
736 			pipe = -1;
737 		acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
738 						 (int) port, (int) pipe);
739 	}
740 
741 	intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
742 			       crtc_state->port_clock,
743 			       intel_crtc_has_dp_encoder(crtc_state));
744 }
745 
746 /**
747  * intel_audio_codec_disable - Disable the audio codec for HD audio
748  * @encoder: encoder on which to disable audio
749  * @old_crtc_state: pointer to the old crtc state.
750  * @old_conn_state: pointer to the old connector state.
751  *
752  * The disable sequences must be performed before disabling the transcoder or
753  * port.
754  */
intel_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)755 void intel_audio_codec_disable(struct intel_encoder *encoder,
756 			       const struct intel_crtc_state *old_crtc_state,
757 			       const struct drm_connector_state *old_conn_state)
758 {
759 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
760 	struct i915_audio_component *acomp = dev_priv->audio_component;
761 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
762 	enum port port = encoder->port;
763 	enum pipe pipe = crtc->pipe;
764 
765 	if (dev_priv->display.audio_codec_disable)
766 		dev_priv->display.audio_codec_disable(encoder,
767 						      old_crtc_state,
768 						      old_conn_state);
769 
770 	mutex_lock(&dev_priv->av_mutex);
771 	encoder->audio_connector = NULL;
772 	dev_priv->av_enc_map[pipe] = NULL;
773 	mutex_unlock(&dev_priv->av_mutex);
774 
775 	if (acomp && acomp->base.audio_ops &&
776 	    acomp->base.audio_ops->pin_eld_notify) {
777 		/* audio drivers expect pipe = -1 to indicate Non-MST cases */
778 		if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
779 			pipe = -1;
780 		acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
781 						 (int) port, (int) pipe);
782 	}
783 
784 	intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
785 }
786 
787 /**
788  * intel_init_audio_hooks - Set up chip specific audio hooks
789  * @dev_priv: device private
790  */
intel_init_audio_hooks(struct drm_i915_private * dev_priv)791 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
792 {
793 	if (IS_G4X(dev_priv)) {
794 		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
795 		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
796 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
797 		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
798 		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
799 	} else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
800 		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
801 		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
802 	} else if (HAS_PCH_SPLIT(dev_priv)) {
803 		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
804 		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
805 	}
806 }
807 
808 #ifndef __NetBSD__		/* XXX intel audio */
809 
glk_force_audio_cdclk(struct drm_i915_private * dev_priv,bool enable)810 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
811 				  bool enable)
812 {
813 	struct drm_modeset_acquire_ctx ctx;
814 	struct drm_atomic_state *state;
815 	int ret;
816 
817 	drm_modeset_acquire_init(&ctx, 0);
818 	state = drm_atomic_state_alloc(&dev_priv->drm);
819 	if (WARN_ON(!state))
820 		return;
821 
822 	state->acquire_ctx = &ctx;
823 
824 retry:
825 	to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true;
826 	to_intel_atomic_state(state)->cdclk.force_min_cdclk =
827 		enable ? 2 * 96000 : 0;
828 
829 	/* Protects dev_priv->cdclk.force_min_cdclk */
830 	ret = intel_atomic_lock_global_state(to_intel_atomic_state(state));
831 	if (!ret)
832 		ret = drm_atomic_commit(state);
833 
834 	if (ret == -EDEADLK) {
835 		drm_atomic_state_clear(state);
836 		drm_modeset_backoff(&ctx);
837 		goto retry;
838 	}
839 
840 	WARN_ON(ret);
841 
842 	drm_atomic_state_put(state);
843 
844 	drm_modeset_drop_locks(&ctx);
845 	drm_modeset_acquire_fini(&ctx);
846 }
847 
i915_audio_component_get_power(struct device * kdev)848 static unsigned long i915_audio_component_get_power(struct device *kdev)
849 {
850 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
851 	intel_wakeref_t ret;
852 
853 	/* Catch potential impedance mismatches before they occur! */
854 	BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
855 
856 	ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
857 
858 	if (dev_priv->audio_power_refcount++ == 0) {
859 		if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
860 			I915_WRITE(AUD_FREQ_CNTRL, dev_priv->audio_freq_cntrl);
861 			DRM_DEBUG_KMS("restored AUD_FREQ_CNTRL to 0x%x\n",
862 				      dev_priv->audio_freq_cntrl);
863 		}
864 
865 		/* Force CDCLK to 2*BCLK as long as we need audio powered. */
866 		if (IS_GEMINILAKE(dev_priv))
867 			glk_force_audio_cdclk(dev_priv, true);
868 
869 		if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
870 			I915_WRITE(AUD_PIN_BUF_CTL,
871 				   (I915_READ(AUD_PIN_BUF_CTL) |
872 				    AUD_PIN_BUF_ENABLE));
873 	}
874 
875 	return ret;
876 }
877 
i915_audio_component_put_power(struct device * kdev,unsigned long cookie)878 static void i915_audio_component_put_power(struct device *kdev,
879 					   unsigned long cookie)
880 {
881 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
882 
883 	/* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
884 	if (--dev_priv->audio_power_refcount == 0)
885 		if (IS_GEMINILAKE(dev_priv))
886 			glk_force_audio_cdclk(dev_priv, false);
887 
888 	intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
889 }
890 
i915_audio_component_codec_wake_override(struct device * kdev,bool enable)891 static void i915_audio_component_codec_wake_override(struct device *kdev,
892 						     bool enable)
893 {
894 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
895 	unsigned long cookie;
896 	u32 tmp;
897 
898 	if (!IS_GEN(dev_priv, 9))
899 		return;
900 
901 	cookie = i915_audio_component_get_power(kdev);
902 
903 	/*
904 	 * Enable/disable generating the codec wake signal, overriding the
905 	 * internal logic to generate the codec wake to controller.
906 	 */
907 	tmp = I915_READ(HSW_AUD_CHICKENBIT);
908 	tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
909 	I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
910 	usleep_range(1000, 1500);
911 
912 	if (enable) {
913 		tmp = I915_READ(HSW_AUD_CHICKENBIT);
914 		tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
915 		I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
916 		usleep_range(1000, 1500);
917 	}
918 
919 	i915_audio_component_put_power(kdev, cookie);
920 }
921 
922 /* Get CDCLK in kHz  */
i915_audio_component_get_cdclk_freq(struct device * kdev)923 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
924 {
925 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
926 
927 	if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
928 		return -ENODEV;
929 
930 	return dev_priv->cdclk.hw.cdclk;
931 }
932 
933 /*
934  * get the intel_encoder according to the parameter port and pipe
935  * intel_encoder is saved by the index of pipe
936  * MST & (pipe >= 0): return the av_enc_map[pipe],
937  *   when port is matched
938  * MST & (pipe < 0): this is invalid
939  * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
940  *   will get the right intel_encoder with port matched
941  * Non-MST & (pipe < 0): get the right intel_encoder with port matched
942  */
get_saved_enc(struct drm_i915_private * dev_priv,int port,int pipe)943 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
944 					       int port, int pipe)
945 {
946 	struct intel_encoder *encoder;
947 
948 	/* MST */
949 	if (pipe >= 0) {
950 		if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
951 			return NULL;
952 
953 		encoder = dev_priv->av_enc_map[pipe];
954 		/*
955 		 * when bootup, audio driver may not know it is
956 		 * MST or not. So it will poll all the port & pipe
957 		 * combinations
958 		 */
959 		if (encoder != NULL && encoder->port == port &&
960 		    encoder->type == INTEL_OUTPUT_DP_MST)
961 			return encoder;
962 	}
963 
964 	/* Non-MST */
965 	if (pipe > 0)
966 		return NULL;
967 
968 	for_each_pipe(dev_priv, pipe) {
969 		encoder = dev_priv->av_enc_map[pipe];
970 		if (encoder == NULL)
971 			continue;
972 
973 		if (encoder->type == INTEL_OUTPUT_DP_MST)
974 			continue;
975 
976 		if (port == encoder->port)
977 			return encoder;
978 	}
979 
980 	return NULL;
981 }
982 
i915_audio_component_sync_audio_rate(struct device * kdev,int port,int pipe,int rate)983 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
984 						int pipe, int rate)
985 {
986 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
987 	struct i915_audio_component *acomp = dev_priv->audio_component;
988 	struct intel_encoder *encoder;
989 	struct intel_crtc *crtc;
990 	unsigned long cookie;
991 	int err = 0;
992 
993 	if (!HAS_DDI(dev_priv))
994 		return 0;
995 
996 	cookie = i915_audio_component_get_power(kdev);
997 	mutex_lock(&dev_priv->av_mutex);
998 
999 	/* 1. get the pipe */
1000 	encoder = get_saved_enc(dev_priv, port, pipe);
1001 	if (!encoder || !encoder->base.crtc) {
1002 		DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
1003 		err = -ENODEV;
1004 		goto unlock;
1005 	}
1006 
1007 	crtc = to_intel_crtc(encoder->base.crtc);
1008 
1009 	/* port must be valid now, otherwise the pipe will be invalid */
1010 	acomp->aud_sample_rate[port] = rate;
1011 
1012 	hsw_audio_config_update(encoder, crtc->config);
1013 
1014  unlock:
1015 	mutex_unlock(&dev_priv->av_mutex);
1016 	i915_audio_component_put_power(kdev, cookie);
1017 	return err;
1018 }
1019 
i915_audio_component_get_eld(struct device * kdev,int port,int pipe,bool * enabled,unsigned char * buf,int max_bytes)1020 static int i915_audio_component_get_eld(struct device *kdev, int port,
1021 					int pipe, bool *enabled,
1022 					unsigned char *buf, int max_bytes)
1023 {
1024 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1025 	struct intel_encoder *intel_encoder;
1026 	const u8 *eld;
1027 	int ret = -EINVAL;
1028 
1029 	mutex_lock(&dev_priv->av_mutex);
1030 
1031 	intel_encoder = get_saved_enc(dev_priv, port, pipe);
1032 	if (!intel_encoder) {
1033 		DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
1034 		mutex_unlock(&dev_priv->av_mutex);
1035 		return ret;
1036 	}
1037 
1038 	ret = 0;
1039 	*enabled = intel_encoder->audio_connector != NULL;
1040 	if (*enabled) {
1041 		eld = intel_encoder->audio_connector->eld;
1042 		ret = drm_eld_size(eld);
1043 		memcpy(buf, eld, min(max_bytes, ret));
1044 	}
1045 
1046 	mutex_unlock(&dev_priv->av_mutex);
1047 	return ret;
1048 }
1049 
1050 static const struct drm_audio_component_ops i915_audio_component_ops = {
1051 	.owner		= THIS_MODULE,
1052 	.get_power	= i915_audio_component_get_power,
1053 	.put_power	= i915_audio_component_put_power,
1054 	.codec_wake_override = i915_audio_component_codec_wake_override,
1055 	.get_cdclk_freq	= i915_audio_component_get_cdclk_freq,
1056 	.sync_audio_rate = i915_audio_component_sync_audio_rate,
1057 	.get_eld	= i915_audio_component_get_eld,
1058 };
1059 
i915_audio_component_bind(struct device * i915_kdev,struct device * hda_kdev,void * data)1060 static int i915_audio_component_bind(struct device *i915_kdev,
1061 				     struct device *hda_kdev, void *data)
1062 {
1063 	struct i915_audio_component *acomp = data;
1064 	struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1065 	int i;
1066 
1067 	if (WARN_ON(acomp->base.ops || acomp->base.dev))
1068 		return -EEXIST;
1069 
1070 	if (WARN_ON(!device_link_add(hda_kdev, i915_kdev, DL_FLAG_STATELESS)))
1071 		return -ENOMEM;
1072 
1073 	drm_modeset_lock_all(&dev_priv->drm);
1074 	acomp->base.ops = &i915_audio_component_ops;
1075 	acomp->base.dev = i915_kdev;
1076 	BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1077 	for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1078 		acomp->aud_sample_rate[i] = 0;
1079 	dev_priv->audio_component = acomp;
1080 	drm_modeset_unlock_all(&dev_priv->drm);
1081 
1082 	return 0;
1083 }
1084 
i915_audio_component_unbind(struct device * i915_kdev,struct device * hda_kdev,void * data)1085 static void i915_audio_component_unbind(struct device *i915_kdev,
1086 					struct device *hda_kdev, void *data)
1087 {
1088 	struct i915_audio_component *acomp = data;
1089 	struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1090 
1091 	drm_modeset_lock_all(&dev_priv->drm);
1092 	acomp->base.ops = NULL;
1093 	acomp->base.dev = NULL;
1094 	dev_priv->audio_component = NULL;
1095 	drm_modeset_unlock_all(&dev_priv->drm);
1096 
1097 	device_link_remove(hda_kdev, i915_kdev);
1098 }
1099 
1100 static const struct component_ops i915_audio_component_bind_ops = {
1101 	.bind	= i915_audio_component_bind,
1102 	.unbind	= i915_audio_component_unbind,
1103 };
1104 
1105 #endif	/* __NetBSD__ */
1106 
1107 /**
1108  * i915_audio_component_init - initialize and register the audio component
1109  * @dev_priv: i915 device instance
1110  *
1111  * This will register with the component framework a child component which
1112  * will bind dynamically to the snd_hda_intel driver's corresponding master
1113  * component when the latter is registered. During binding the child
1114  * initializes an instance of struct i915_audio_component which it receives
1115  * from the master. The master can then start to use the interface defined by
1116  * this struct. Each side can break the binding at any point by deregistering
1117  * its own component after which each side's component unbind callback is
1118  * called.
1119  *
1120  * We ignore any error during registration and continue with reduced
1121  * functionality (i.e. without HDMI audio).
1122  */
i915_audio_component_init(struct drm_i915_private * dev_priv)1123 static void i915_audio_component_init(struct drm_i915_private *dev_priv)
1124 {
1125 #ifndef __NetBSD__		/* XXX intel audio */
1126 	int ret;
1127 
1128 	ret = component_add_typed(dev_priv->drm.dev,
1129 				  &i915_audio_component_bind_ops,
1130 				  I915_COMPONENT_AUDIO);
1131 	if (ret < 0) {
1132 		DRM_ERROR("failed to add audio component (%d)\n", ret);
1133 		/* continue with reduced functionality */
1134 		return;
1135 	}
1136 #endif
1137 
1138 	if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
1139 		dev_priv->audio_freq_cntrl = I915_READ(AUD_FREQ_CNTRL);
1140 		DRM_DEBUG_KMS("init value of AUD_FREQ_CNTRL of 0x%x\n",
1141 			      dev_priv->audio_freq_cntrl);
1142 	}
1143 
1144 	dev_priv->audio_component_registered = true;
1145 }
1146 
1147 /**
1148  * i915_audio_component_cleanup - deregister the audio component
1149  * @dev_priv: i915 device instance
1150  *
1151  * Deregisters the audio component, breaking any existing binding to the
1152  * corresponding snd_hda_intel driver's master component.
1153  */
i915_audio_component_cleanup(struct drm_i915_private * dev_priv)1154 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
1155 {
1156 	if (!dev_priv->audio_component_registered)
1157 		return;
1158 
1159 #ifndef __NetBSD__		/* XXX intel audio */
1160 	component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
1161 #endif
1162 	dev_priv->audio_component_registered = false;
1163 }
1164 
1165 /**
1166  * intel_audio_init() - Initialize the audio driver either using
1167  * component framework or using lpe audio bridge
1168  * @dev_priv: the i915 drm device private data
1169  *
1170  */
intel_audio_init(struct drm_i915_private * dev_priv)1171 void intel_audio_init(struct drm_i915_private *dev_priv)
1172 {
1173 	if (intel_lpe_audio_init(dev_priv) < 0)
1174 		i915_audio_component_init(dev_priv);
1175 }
1176 
1177 /**
1178  * intel_audio_deinit() - deinitialize the audio driver
1179  * @dev_priv: the i915 drm device private data
1180  *
1181  */
intel_audio_deinit(struct drm_i915_private * dev_priv)1182 void intel_audio_deinit(struct drm_i915_private *dev_priv)
1183 {
1184 	if ((dev_priv)->lpe_audio.platdev != NULL)
1185 		intel_lpe_audio_teardown(dev_priv);
1186 	else
1187 		i915_audio_component_cleanup(dev_priv);
1188 }
1189