1 /* $NetBSD: intel_guc_ads.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */
2
3 // SPDX-License-Identifier: MIT
4 /*
5 * Copyright © 2014-2019 Intel Corporation
6 */
7
8 #include <sys/cdefs.h>
9 __KERNEL_RCSID(0, "$NetBSD: intel_guc_ads.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $");
10
11 #include "gt/intel_gt.h"
12 #include "intel_guc_ads.h"
13 #include "intel_uc.h"
14 #include "i915_drv.h"
15
16 /*
17 * The Additional Data Struct (ADS) has pointers for different buffers used by
18 * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
19 * scheduling policies (guc_policies), a structure describing a collection of
20 * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
21 * its internal state for sleep.
22 */
23
guc_policy_init(struct guc_policy * policy)24 static void guc_policy_init(struct guc_policy *policy)
25 {
26 policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
27 policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;
28 policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;
29 policy->policy_flags = 0;
30 }
31
guc_policies_init(struct guc_policies * policies)32 static void guc_policies_init(struct guc_policies *policies)
33 {
34 struct guc_policy *policy;
35 u32 p, i;
36
37 policies->dpc_promote_time = POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
38 policies->max_num_work_items = POLICY_MAX_NUM_WI;
39
40 for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
41 for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++) {
42 policy = &policies->policy[p][i];
43
44 guc_policy_init(policy);
45 }
46 }
47
48 policies->is_valid = 1;
49 }
50
guc_ct_pool_entries_init(struct guc_ct_pool_entry * pool,u32 num)51 static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
52 {
53 memset(pool, 0, num * sizeof(*pool));
54 }
55
56 /*
57 * The first 80 dwords of the register state context, containing the
58 * execlists and ppgtt registers.
59 */
60 #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
61
62 /* The ads obj includes the struct itself and buffers passed to GuC */
63 struct __guc_ads_blob {
64 struct guc_ads ads;
65 struct guc_policies policies;
66 struct guc_mmio_reg_state reg_state;
67 struct guc_gt_system_info system_info;
68 struct guc_clients_info clients_info;
69 struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
70 u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
71 } __packed;
72
__guc_ads_init(struct intel_guc * guc)73 static void __guc_ads_init(struct intel_guc *guc)
74 {
75 struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
76 struct __guc_ads_blob *blob = guc->ads_blob;
77 const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
78 u32 base;
79 u8 engine_class;
80
81 /* GuC scheduling policies */
82 guc_policies_init(&blob->policies);
83
84 /*
85 * GuC expects a per-engine-class context image and size
86 * (minus hwsp and ring context). The context image will be
87 * used to reinitialize engines after a reset. It must exist
88 * and be pinned in the GGTT, so that the address won't change after
89 * we have told GuC where to find it. The context size will be used
90 * to validate that the LRC base + size fall within allowed GGTT.
91 */
92 for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
93 if (engine_class == OTHER_CLASS)
94 continue;
95 /*
96 * TODO: Set context pointer to default state to allow
97 * GuC to re-init guilty contexts after internal reset.
98 */
99 blob->ads.golden_context_lrca[engine_class] = 0;
100 blob->ads.eng_state_size[engine_class] =
101 intel_engine_context_size(guc_to_gt(guc),
102 engine_class) -
103 skipped_size;
104 }
105
106 /* System info */
107 blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
108 blob->system_info.rcs_enabled = 1;
109 blob->system_info.bcs_enabled = 1;
110
111 blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv);
112 blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
113 blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
114
115 base = intel_guc_ggtt_offset(guc, guc->ads_vma);
116
117 /* Clients info */
118 guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
119
120 blob->clients_info.clients_num = 1;
121 blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);
122 blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);
123
124 /* ADS */
125 blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
126 blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
127 blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
128 blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
129 blob->ads.clients_info = base + ptr_offset(blob, clients_info);
130
131 i915_gem_object_flush_map(guc->ads_vma->obj);
132 }
133
134 /**
135 * intel_guc_ads_create() - allocates and initializes GuC ADS.
136 * @guc: intel_guc struct
137 *
138 * GuC needs memory block (Additional Data Struct), where it will store
139 * some data. Allocate and initialize such memory block for GuC use.
140 */
intel_guc_ads_create(struct intel_guc * guc)141 int intel_guc_ads_create(struct intel_guc *guc)
142 {
143 const u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob));
144 int ret;
145
146 GEM_BUG_ON(guc->ads_vma);
147
148 ret = intel_guc_allocate_and_map_vma(guc, size, &guc->ads_vma,
149 (void **)&guc->ads_blob);
150
151 if (ret)
152 return ret;
153
154 __guc_ads_init(guc);
155
156 return 0;
157 }
158
intel_guc_ads_destroy(struct intel_guc * guc)159 void intel_guc_ads_destroy(struct intel_guc *guc)
160 {
161 i915_vma_unpin_and_release(&guc->ads_vma, I915_VMA_RELEASE_MAP);
162 }
163
164 /**
165 * intel_guc_ads_reset() - prepares GuC Additional Data Struct for reuse
166 * @guc: intel_guc struct
167 *
168 * GuC stores some data in ADS, which might be stale after a reset.
169 * Reinitialize whole ADS in case any part of it was corrupted during
170 * previous GuC run.
171 */
intel_guc_ads_reset(struct intel_guc * guc)172 void intel_guc_ads_reset(struct intel_guc *guc)
173 {
174 if (!guc->ads_vma)
175 return;
176 __guc_ads_init(guc);
177 }
178