1 /* $NetBSD: intel_lvds.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */
2
3 /*
4 * Copyright © 2006-2007 Intel Corporation
5 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Eric Anholt <eric@anholt.net>
28 * Dave Airlie <airlied@linux.ie>
29 * Jesse Barnes <jesse.barnes@intel.com>
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: intel_lvds.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $");
34
35 #include <acpi/button.h>
36 #include <linux/acpi.h>
37 #include <linux/dmi.h>
38 #include <linux/i2c.h>
39 #include <linux/slab.h>
40 #include <linux/vga_switcheroo.h>
41
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_crtc.h>
44 #include <drm/drm_edid.h>
45 #include <drm/i915_drm.h>
46
47 #include "i915_drv.h"
48 #include "intel_atomic.h"
49 #include "intel_connector.h"
50 #include "intel_display_types.h"
51 #include "intel_gmbus.h"
52 #include "intel_lvds.h"
53 #include "intel_panel.h"
54
55 /* Private structure for the integrated LVDS support */
56 struct intel_lvds_pps {
57 /* 100us units */
58 int t1_t2;
59 int t3;
60 int t4;
61 int t5;
62 int tx;
63
64 int divider;
65
66 int port;
67 bool powerdown_on_reset;
68 };
69
70 struct intel_lvds_encoder {
71 struct intel_encoder base;
72
73 bool is_dual_link;
74 i915_reg_t reg;
75 u32 a3_power;
76
77 struct intel_lvds_pps init_pps;
78 u32 init_lvds_val;
79
80 struct intel_connector *attached_connector;
81 };
82
to_lvds_encoder(struct drm_encoder * encoder)83 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
84 {
85 return container_of(encoder, struct intel_lvds_encoder, base.base);
86 }
87
intel_lvds_port_enabled(struct drm_i915_private * dev_priv,i915_reg_t lvds_reg,enum pipe * pipe)88 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
89 i915_reg_t lvds_reg, enum pipe *pipe)
90 {
91 u32 val;
92
93 val = I915_READ(lvds_reg);
94
95 /* asserts want to know the pipe even if the port is disabled */
96 if (HAS_PCH_CPT(dev_priv))
97 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
98 else
99 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
100
101 return val & LVDS_PORT_EN;
102 }
103
intel_lvds_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)104 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
105 enum pipe *pipe)
106 {
107 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
108 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
109 intel_wakeref_t wakeref;
110 bool ret;
111
112 wakeref = intel_display_power_get_if_enabled(dev_priv,
113 encoder->power_domain);
114 if (!wakeref)
115 return false;
116
117 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
118
119 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
120
121 return ret;
122 }
123
intel_lvds_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)124 static void intel_lvds_get_config(struct intel_encoder *encoder,
125 struct intel_crtc_state *pipe_config)
126 {
127 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
128 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
129 u32 tmp, flags = 0;
130
131 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
132
133 tmp = I915_READ(lvds_encoder->reg);
134 if (tmp & LVDS_HSYNC_POLARITY)
135 flags |= DRM_MODE_FLAG_NHSYNC;
136 else
137 flags |= DRM_MODE_FLAG_PHSYNC;
138 if (tmp & LVDS_VSYNC_POLARITY)
139 flags |= DRM_MODE_FLAG_NVSYNC;
140 else
141 flags |= DRM_MODE_FLAG_PVSYNC;
142
143 pipe_config->hw.adjusted_mode.flags |= flags;
144
145 if (INTEL_GEN(dev_priv) < 5)
146 pipe_config->gmch_pfit.lvds_border_bits =
147 tmp & LVDS_BORDER_ENABLE;
148
149 /* gen2/3 store dither state in pfit control, needs to match */
150 if (INTEL_GEN(dev_priv) < 4) {
151 tmp = I915_READ(PFIT_CONTROL);
152
153 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
154 }
155
156 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
157 }
158
intel_lvds_pps_get_hw_state(struct drm_i915_private * dev_priv,struct intel_lvds_pps * pps)159 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
160 struct intel_lvds_pps *pps)
161 {
162 u32 val;
163
164 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
165
166 val = I915_READ(PP_ON_DELAYS(0));
167 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
168 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
169 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
170
171 val = I915_READ(PP_OFF_DELAYS(0));
172 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
173 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
174
175 val = I915_READ(PP_DIVISOR(0));
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
177 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
178 /*
179 * Remove the BSpec specified +1 (100ms) offset that accounts for a
180 * too short power-cycle delay due to the asynchronous programming of
181 * the register.
182 */
183 if (val)
184 val--;
185 /* Convert from 100ms to 100us units */
186 pps->t4 = val * 1000;
187
188 if (INTEL_GEN(dev_priv) <= 4 &&
189 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
190 DRM_DEBUG_KMS("Panel power timings uninitialized, "
191 "setting defaults\n");
192 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
193 pps->t1_t2 = 40 * 10;
194 pps->t5 = 200 * 10;
195 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
196 pps->t3 = 35 * 10;
197 pps->tx = 200 * 10;
198 }
199
200 DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
201 "divider %d port %d powerdown_on_reset %d\n",
202 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
203 pps->divider, pps->port, pps->powerdown_on_reset);
204 }
205
intel_lvds_pps_init_hw(struct drm_i915_private * dev_priv,struct intel_lvds_pps * pps)206 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
207 struct intel_lvds_pps *pps)
208 {
209 u32 val;
210
211 val = I915_READ(PP_CONTROL(0));
212 WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
213 if (pps->powerdown_on_reset)
214 val |= PANEL_POWER_RESET;
215 I915_WRITE(PP_CONTROL(0), val);
216
217 I915_WRITE(PP_ON_DELAYS(0),
218 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
219 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) |
220 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
221
222 I915_WRITE(PP_OFF_DELAYS(0),
223 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) |
224 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
225
226 I915_WRITE(PP_DIVISOR(0),
227 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
228 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,
229 DIV_ROUND_UP(pps->t4, 1000) + 1));
230 }
231
intel_pre_enable_lvds(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)232 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
233 const struct intel_crtc_state *pipe_config,
234 const struct drm_connector_state *conn_state)
235 {
236 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
237 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
238 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
239 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
240 enum pipe pipe = crtc->pipe;
241 u32 temp;
242
243 if (HAS_PCH_SPLIT(dev_priv)) {
244 assert_fdi_rx_pll_disabled(dev_priv, pipe);
245 assert_shared_dpll_disabled(dev_priv,
246 pipe_config->shared_dpll);
247 } else {
248 assert_pll_disabled(dev_priv, pipe);
249 }
250
251 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
252
253 temp = lvds_encoder->init_lvds_val;
254 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
255
256 if (HAS_PCH_CPT(dev_priv)) {
257 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
258 temp |= LVDS_PIPE_SEL_CPT(pipe);
259 } else {
260 temp &= ~LVDS_PIPE_SEL_MASK;
261 temp |= LVDS_PIPE_SEL(pipe);
262 }
263
264 /* set the corresponsding LVDS_BORDER bit */
265 temp &= ~LVDS_BORDER_ENABLE;
266 temp |= pipe_config->gmch_pfit.lvds_border_bits;
267
268 /*
269 * Set the B0-B3 data pairs corresponding to whether we're going to
270 * set the DPLLs for dual-channel mode or not.
271 */
272 if (lvds_encoder->is_dual_link)
273 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
274 else
275 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
276
277 /*
278 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
279 * appropriately here, but we need to look more thoroughly into how
280 * panels behave in the two modes. For now, let's just maintain the
281 * value we got from the BIOS.
282 */
283 temp &= ~LVDS_A3_POWER_MASK;
284 temp |= lvds_encoder->a3_power;
285
286 /*
287 * Set the dithering flag on LVDS as needed, note that there is no
288 * special lvds dither control bit on pch-split platforms, dithering is
289 * only controlled through the PIPECONF reg.
290 */
291 if (IS_GEN(dev_priv, 4)) {
292 /*
293 * Bspec wording suggests that LVDS port dithering only exists
294 * for 18bpp panels.
295 */
296 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
297 temp |= LVDS_ENABLE_DITHER;
298 else
299 temp &= ~LVDS_ENABLE_DITHER;
300 }
301 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
302 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
303 temp |= LVDS_HSYNC_POLARITY;
304 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
305 temp |= LVDS_VSYNC_POLARITY;
306
307 I915_WRITE(lvds_encoder->reg, temp);
308 }
309
310 /*
311 * Sets the power state for the panel.
312 */
intel_enable_lvds(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)313 static void intel_enable_lvds(struct intel_encoder *encoder,
314 const struct intel_crtc_state *pipe_config,
315 const struct drm_connector_state *conn_state)
316 {
317 struct drm_device *dev = encoder->base.dev;
318 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
319 struct drm_i915_private *dev_priv = to_i915(dev);
320
321 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
322
323 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
324 POSTING_READ(lvds_encoder->reg);
325
326 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
327 DRM_ERROR("timed out waiting for panel to power on\n");
328
329 intel_panel_enable_backlight(pipe_config, conn_state);
330 }
331
intel_disable_lvds(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)332 static void intel_disable_lvds(struct intel_encoder *encoder,
333 const struct intel_crtc_state *old_crtc_state,
334 const struct drm_connector_state *old_conn_state)
335 {
336 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
337 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
338
339 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
340 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
341 DRM_ERROR("timed out waiting for panel to power off\n");
342
343 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
344 POSTING_READ(lvds_encoder->reg);
345 }
346
gmch_disable_lvds(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)347 static void gmch_disable_lvds(struct intel_encoder *encoder,
348 const struct intel_crtc_state *old_crtc_state,
349 const struct drm_connector_state *old_conn_state)
350
351 {
352 intel_panel_disable_backlight(old_conn_state);
353
354 intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
355 }
356
pch_disable_lvds(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)357 static void pch_disable_lvds(struct intel_encoder *encoder,
358 const struct intel_crtc_state *old_crtc_state,
359 const struct drm_connector_state *old_conn_state)
360 {
361 intel_panel_disable_backlight(old_conn_state);
362 }
363
pch_post_disable_lvds(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)364 static void pch_post_disable_lvds(struct intel_encoder *encoder,
365 const struct intel_crtc_state *old_crtc_state,
366 const struct drm_connector_state *old_conn_state)
367 {
368 intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
369 }
370
371 static enum drm_mode_status
intel_lvds_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)372 intel_lvds_mode_valid(struct drm_connector *connector,
373 struct drm_display_mode *mode)
374 {
375 struct intel_connector *intel_connector = to_intel_connector(connector);
376 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
377 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
378
379 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
380 return MODE_NO_DBLESCAN;
381 if (mode->hdisplay > fixed_mode->hdisplay)
382 return MODE_PANEL;
383 if (mode->vdisplay > fixed_mode->vdisplay)
384 return MODE_PANEL;
385 if (fixed_mode->clock > max_pixclk)
386 return MODE_CLOCK_HIGH;
387
388 return MODE_OK;
389 }
390
intel_lvds_compute_config(struct intel_encoder * intel_encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)391 static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
392 struct intel_crtc_state *pipe_config,
393 struct drm_connector_state *conn_state)
394 {
395 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
396 struct intel_lvds_encoder *lvds_encoder =
397 to_lvds_encoder(&intel_encoder->base);
398 struct intel_connector *intel_connector =
399 lvds_encoder->attached_connector;
400 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
401 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
402 unsigned int lvds_bpp;
403
404 /* Should never happen!! */
405 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
406 DRM_ERROR("Can't support LVDS on pipe A\n");
407 return -EINVAL;
408 }
409
410 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
411 lvds_bpp = 8*3;
412 else
413 lvds_bpp = 6*3;
414
415 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
416 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
417 pipe_config->pipe_bpp, lvds_bpp);
418 pipe_config->pipe_bpp = lvds_bpp;
419 }
420
421 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
422
423 /*
424 * We have timings from the BIOS for the panel, put them in
425 * to the adjusted mode. The CRTC will be set up for this mode,
426 * with the panel scaling set up to source from the H/VDisplay
427 * of the original mode.
428 */
429 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
430 adjusted_mode);
431
432 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
433 return -EINVAL;
434
435 if (HAS_PCH_SPLIT(dev_priv)) {
436 pipe_config->has_pch_encoder = true;
437
438 intel_pch_panel_fitting(intel_crtc, pipe_config,
439 conn_state->scaling_mode);
440 } else {
441 intel_gmch_panel_fitting(intel_crtc, pipe_config,
442 conn_state->scaling_mode);
443
444 }
445
446 /*
447 * XXX: It would be nice to support lower refresh rates on the
448 * panels to reduce power consumption, and perhaps match the
449 * user's requested refresh rate.
450 */
451
452 return 0;
453 }
454
455 static enum drm_connector_status
intel_lvds_detect(struct drm_connector * connector,bool force)456 intel_lvds_detect(struct drm_connector *connector, bool force)
457 {
458 return connector_status_connected;
459 }
460
461 /*
462 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
463 */
intel_lvds_get_modes(struct drm_connector * connector)464 static int intel_lvds_get_modes(struct drm_connector *connector)
465 {
466 struct intel_connector *intel_connector = to_intel_connector(connector);
467 struct drm_device *dev = connector->dev;
468 struct drm_display_mode *mode;
469
470 /* use cached edid if we have one */
471 if (!IS_ERR_OR_NULL(intel_connector->edid))
472 return drm_add_edid_modes(connector, intel_connector->edid);
473
474 mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode);
475 if (mode == NULL)
476 return 0;
477
478 drm_mode_probed_add(connector, mode);
479 return 1;
480 }
481
482 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
483 .get_modes = intel_lvds_get_modes,
484 .mode_valid = intel_lvds_mode_valid,
485 .atomic_check = intel_digital_connector_atomic_check,
486 };
487
488 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
489 .detect = intel_lvds_detect,
490 .fill_modes = drm_helper_probe_single_connector_modes,
491 .atomic_get_property = intel_digital_connector_atomic_get_property,
492 .atomic_set_property = intel_digital_connector_atomic_set_property,
493 .late_register = intel_connector_register,
494 .early_unregister = intel_connector_unregister,
495 .destroy = intel_connector_destroy,
496 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
497 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
498 };
499
500 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
501 .destroy = intel_encoder_destroy,
502 };
503
intel_no_lvds_dmi_callback(const struct dmi_system_id * id)504 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
505 {
506 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
507 return 1;
508 }
509
510 /* These systems claim to have LVDS, but really don't */
511 static const struct dmi_system_id intel_no_lvds[] = {
512 {
513 .callback = intel_no_lvds_dmi_callback,
514 .ident = "Apple Mac Mini (Core series)",
515 .matches = {
516 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
517 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
518 },
519 },
520 {
521 .callback = intel_no_lvds_dmi_callback,
522 .ident = "Apple Mac Mini (Core 2 series)",
523 .matches = {
524 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
525 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
526 },
527 },
528 {
529 .callback = intel_no_lvds_dmi_callback,
530 .ident = "MSI IM-945GSE-A",
531 .matches = {
532 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
533 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
534 },
535 },
536 {
537 .callback = intel_no_lvds_dmi_callback,
538 .ident = "Dell Studio Hybrid",
539 .matches = {
540 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
541 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
542 },
543 },
544 {
545 .callback = intel_no_lvds_dmi_callback,
546 .ident = "Dell OptiPlex FX170",
547 .matches = {
548 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
549 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
550 },
551 },
552 {
553 .callback = intel_no_lvds_dmi_callback,
554 .ident = "AOpen Mini PC",
555 .matches = {
556 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
557 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
558 },
559 },
560 {
561 .callback = intel_no_lvds_dmi_callback,
562 .ident = "AOpen Mini PC MP915",
563 .matches = {
564 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
565 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
566 },
567 },
568 {
569 .callback = intel_no_lvds_dmi_callback,
570 .ident = "AOpen i915GMm-HFS",
571 .matches = {
572 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
573 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
574 },
575 },
576 {
577 .callback = intel_no_lvds_dmi_callback,
578 .ident = "AOpen i45GMx-I",
579 .matches = {
580 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
581 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
582 },
583 },
584 {
585 .callback = intel_no_lvds_dmi_callback,
586 .ident = "Aopen i945GTt-VFA",
587 .matches = {
588 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
589 },
590 },
591 {
592 .callback = intel_no_lvds_dmi_callback,
593 .ident = "Clientron U800",
594 .matches = {
595 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
596 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
597 },
598 },
599 {
600 .callback = intel_no_lvds_dmi_callback,
601 .ident = "Clientron E830",
602 .matches = {
603 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
604 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
605 },
606 },
607 {
608 .callback = intel_no_lvds_dmi_callback,
609 .ident = "Asus EeeBox PC EB1007",
610 .matches = {
611 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
612 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
613 },
614 },
615 {
616 .callback = intel_no_lvds_dmi_callback,
617 .ident = "Asus AT5NM10T-I",
618 .matches = {
619 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
620 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
621 },
622 },
623 {
624 .callback = intel_no_lvds_dmi_callback,
625 .ident = "Hewlett-Packard HP t5740",
626 .matches = {
627 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
628 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
629 },
630 },
631 {
632 .callback = intel_no_lvds_dmi_callback,
633 .ident = "Hewlett-Packard t5745",
634 .matches = {
635 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
636 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
637 },
638 },
639 {
640 .callback = intel_no_lvds_dmi_callback,
641 .ident = "Hewlett-Packard st5747",
642 .matches = {
643 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
644 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
645 },
646 },
647 {
648 .callback = intel_no_lvds_dmi_callback,
649 .ident = "MSI Wind Box DC500",
650 .matches = {
651 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
652 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
653 },
654 },
655 {
656 .callback = intel_no_lvds_dmi_callback,
657 .ident = "Gigabyte GA-D525TUD",
658 .matches = {
659 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
660 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
661 },
662 },
663 {
664 .callback = intel_no_lvds_dmi_callback,
665 .ident = "Supermicro X7SPA-H",
666 .matches = {
667 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
668 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
669 },
670 },
671 {
672 .callback = intel_no_lvds_dmi_callback,
673 .ident = "Fujitsu Esprimo Q900",
674 .matches = {
675 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
676 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
677 },
678 },
679 {
680 .callback = intel_no_lvds_dmi_callback,
681 .ident = "Intel D410PT",
682 .matches = {
683 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
684 DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
685 },
686 },
687 {
688 .callback = intel_no_lvds_dmi_callback,
689 .ident = "Intel D425KT",
690 .matches = {
691 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
692 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
693 },
694 },
695 {
696 .callback = intel_no_lvds_dmi_callback,
697 .ident = "Intel D510MO",
698 .matches = {
699 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
700 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
701 },
702 },
703 {
704 .callback = intel_no_lvds_dmi_callback,
705 .ident = "Intel D525MW",
706 .matches = {
707 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
708 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
709 },
710 },
711 {
712 .callback = intel_no_lvds_dmi_callback,
713 .ident = "Radiant P845",
714 .matches = {
715 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
716 DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
717 },
718 },
719
720 { } /* terminating entry */
721 };
722
intel_dual_link_lvds_callback(const struct dmi_system_id * id)723 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
724 {
725 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
726 return 1;
727 }
728
729 static const struct dmi_system_id intel_dual_link_lvds[] = {
730 {
731 .callback = intel_dual_link_lvds_callback,
732 .ident = "Apple MacBook Pro 15\" (2010)",
733 .matches = {
734 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
735 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
736 },
737 },
738 {
739 .callback = intel_dual_link_lvds_callback,
740 .ident = "Apple MacBook Pro 15\" (2011)",
741 .matches = {
742 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
743 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
744 },
745 },
746 {
747 .callback = intel_dual_link_lvds_callback,
748 .ident = "Apple MacBook Pro 15\" (2012)",
749 .matches = {
750 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
751 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
752 },
753 },
754 { } /* terminating entry */
755 };
756
intel_get_lvds_encoder(struct drm_i915_private * dev_priv)757 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv)
758 {
759 struct intel_encoder *encoder;
760
761 for_each_intel_encoder(&dev_priv->drm, encoder) {
762 if (encoder->type == INTEL_OUTPUT_LVDS)
763 return encoder;
764 }
765
766 return NULL;
767 }
768
intel_is_dual_link_lvds(struct drm_i915_private * dev_priv)769 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv)
770 {
771 struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv);
772
773 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
774 }
775
compute_is_dual_link_lvds(struct intel_lvds_encoder * lvds_encoder)776 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
777 {
778 struct drm_device *dev = lvds_encoder->base.base.dev;
779 unsigned int val;
780 struct drm_i915_private *dev_priv = to_i915(dev);
781
782 /* use the module option value if specified */
783 if (i915_modparams.lvds_channel_mode > 0)
784 return i915_modparams.lvds_channel_mode == 2;
785
786 /* single channel LVDS is limited to 112 MHz */
787 if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999)
788 return true;
789
790 if (dmi_check_system(intel_dual_link_lvds))
791 return true;
792
793 /*
794 * BIOS should set the proper LVDS register value at boot, but
795 * in reality, it doesn't set the value when the lid is closed;
796 * we need to check "the value to be set" in VBT when LVDS
797 * register is uninitialized.
798 */
799 val = I915_READ(lvds_encoder->reg);
800 if (HAS_PCH_CPT(dev_priv))
801 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
802 else
803 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
804 if (val == 0)
805 val = dev_priv->vbt.bios_lvds_val;
806
807 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
808 }
809
810 /**
811 * intel_lvds_init - setup LVDS connectors on this device
812 * @dev_priv: i915 device
813 *
814 * Create the connector, register the LVDS DDC bus, and try to figure out what
815 * modes we can display on the LVDS panel (if present).
816 */
intel_lvds_init(struct drm_i915_private * dev_priv)817 void intel_lvds_init(struct drm_i915_private *dev_priv)
818 {
819 struct drm_device *dev = &dev_priv->drm;
820 struct intel_lvds_encoder *lvds_encoder;
821 struct intel_encoder *intel_encoder;
822 struct intel_connector *intel_connector;
823 struct drm_connector *connector;
824 struct drm_encoder *encoder;
825 struct drm_display_mode *fixed_mode = NULL;
826 struct drm_display_mode *downclock_mode = NULL;
827 struct edid *edid;
828 i915_reg_t lvds_reg;
829 u32 lvds;
830 u8 pin;
831 u32 allowed_scalers;
832
833 /* Skip init on machines we know falsely report LVDS */
834 if (dmi_check_system(intel_no_lvds)) {
835 WARN(!dev_priv->vbt.int_lvds_support,
836 "Useless DMI match. Internal LVDS support disabled by VBT\n");
837 return;
838 }
839
840 if (!dev_priv->vbt.int_lvds_support) {
841 DRM_DEBUG_KMS("Internal LVDS support disabled by VBT\n");
842 return;
843 }
844
845 if (HAS_PCH_SPLIT(dev_priv))
846 lvds_reg = PCH_LVDS;
847 else
848 lvds_reg = LVDS;
849
850 lvds = I915_READ(lvds_reg);
851
852 if (HAS_PCH_SPLIT(dev_priv)) {
853 if ((lvds & LVDS_DETECTED) == 0)
854 return;
855 }
856
857 pin = GMBUS_PIN_PANEL;
858 if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
859 if ((lvds & LVDS_PORT_EN) == 0) {
860 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
861 return;
862 }
863 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
864 }
865
866 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
867 if (!lvds_encoder)
868 return;
869
870 intel_connector = intel_connector_alloc();
871 if (!intel_connector) {
872 kfree(lvds_encoder);
873 return;
874 }
875
876 lvds_encoder->attached_connector = intel_connector;
877
878 intel_encoder = &lvds_encoder->base;
879 encoder = &intel_encoder->base;
880 connector = &intel_connector->base;
881 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
882 DRM_MODE_CONNECTOR_LVDS);
883
884 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
885 DRM_MODE_ENCODER_LVDS, "LVDS");
886
887 intel_encoder->enable = intel_enable_lvds;
888 intel_encoder->pre_enable = intel_pre_enable_lvds;
889 intel_encoder->compute_config = intel_lvds_compute_config;
890 if (HAS_PCH_SPLIT(dev_priv)) {
891 intel_encoder->disable = pch_disable_lvds;
892 intel_encoder->post_disable = pch_post_disable_lvds;
893 } else {
894 intel_encoder->disable = gmch_disable_lvds;
895 }
896 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
897 intel_encoder->get_config = intel_lvds_get_config;
898 intel_encoder->update_pipe = intel_panel_update_backlight;
899 intel_connector->get_hw_state = intel_connector_get_hw_state;
900
901 intel_connector_attach_encoder(intel_connector, intel_encoder);
902
903 intel_encoder->type = INTEL_OUTPUT_LVDS;
904 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
905 intel_encoder->port = PORT_NONE;
906 intel_encoder->cloneable = 0;
907 if (INTEL_GEN(dev_priv) < 4)
908 intel_encoder->pipe_mask = BIT(PIPE_B);
909 else
910 intel_encoder->pipe_mask = ~0;
911
912 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
913 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
914 connector->interlace_allowed = false;
915 connector->doublescan_allowed = false;
916
917 lvds_encoder->reg = lvds_reg;
918
919 /* create the scaling mode property */
920 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
921 allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
922 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
923 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
924 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
925
926 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
927 lvds_encoder->init_lvds_val = lvds;
928
929 /*
930 * LVDS discovery:
931 * 1) check for EDID on DDC
932 * 2) check for VBT data
933 * 3) check to see if LVDS is already on
934 * if none of the above, no panel
935 */
936
937 /*
938 * Attempt to get the fixed panel mode from DDC. Assume that the
939 * preferred mode is the right one.
940 */
941 mutex_lock(&dev->mode_config.mutex);
942 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
943 edid = drm_get_edid_switcheroo(connector,
944 intel_gmbus_get_adapter(dev_priv, pin));
945 else
946 edid = drm_get_edid(connector,
947 intel_gmbus_get_adapter(dev_priv, pin));
948 if (edid) {
949 if (drm_add_edid_modes(connector, edid)) {
950 drm_connector_update_edid_property(connector,
951 edid);
952 } else {
953 kfree(edid);
954 edid = ERR_PTR(-EINVAL);
955 }
956 } else {
957 edid = ERR_PTR(-ENOENT);
958 }
959 intel_connector->edid = edid;
960
961 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
962 if (fixed_mode)
963 goto out;
964
965 /* Failed to get EDID, what about VBT? */
966 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
967 if (fixed_mode)
968 goto out;
969
970 /*
971 * If we didn't get EDID, try checking if the panel is already turned
972 * on. If so, assume that whatever is currently programmed is the
973 * correct mode.
974 */
975 fixed_mode = intel_encoder_current_mode(intel_encoder);
976 if (fixed_mode) {
977 DRM_DEBUG_KMS("using current (BIOS) mode: ");
978 drm_mode_debug_printmodeline(fixed_mode);
979 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
980 }
981
982 /* If we still don't have a mode after all that, give up. */
983 if (!fixed_mode)
984 goto failed;
985
986 out:
987 mutex_unlock(&dev->mode_config.mutex);
988
989 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
990 intel_panel_setup_backlight(connector, INVALID_PIPE);
991
992 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
993 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
994 lvds_encoder->is_dual_link ? "dual" : "single");
995
996 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
997
998 return;
999
1000 failed:
1001 mutex_unlock(&dev->mode_config.mutex);
1002
1003 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1004 drm_connector_cleanup(connector);
1005 drm_encoder_cleanup(encoder);
1006 kfree(lvds_encoder);
1007 intel_connector_free(intel_connector);
1008 return;
1009 }
1010