1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 * 5 * High level display driver entry points. This is a layer between top level 6 * driver code and low level display functionality; no low level display code or 7 * details here. 8 */ 9 10 #include <linux/vga_switcheroo.h> 11 #include <acpi/video.h> 12 #include <drm/display/drm_dp_mst_helper.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_mode_config.h> 15 #include <drm/drm_privacy_screen_consumer.h> 16 #include <drm/drm_probe_helper.h> 17 #include <drm/drm_vblank.h> 18 19 #include "i915_drv.h" 20 #include "i9xx_wm.h" 21 #include "intel_acpi.h" 22 #include "intel_atomic.h" 23 #include "intel_audio.h" 24 #include "intel_bios.h" 25 #include "intel_bw.h" 26 #include "intel_cdclk.h" 27 #include "intel_color.h" 28 #include "intel_crtc.h" 29 #include "intel_display_debugfs.h" 30 #include "intel_display_driver.h" 31 #include "intel_display_irq.h" 32 #include "intel_display_power.h" 33 #include "intel_display_types.h" 34 #include "intel_dkl_phy.h" 35 #include "intel_dmc.h" 36 #include "intel_dp.h" 37 #include "intel_dpll.h" 38 #include "intel_dpll_mgr.h" 39 #include "intel_fb.h" 40 #include "intel_fbc.h" 41 #include "intel_fbdev.h" 42 #include "intel_fdi.h" 43 #include "intel_gmbus.h" 44 #include "intel_hdcp.h" 45 #include "intel_hotplug.h" 46 #include "intel_hti.h" 47 #include "intel_modeset_setup.h" 48 #include "intel_opregion.h" 49 #include "intel_overlay.h" 50 #include "intel_plane_initial.h" 51 #include "intel_pmdemand.h" 52 #include "intel_pps.h" 53 #include "intel_quirks.h" 54 #include "intel_vga.h" 55 #include "intel_wm.h" 56 #include "skl_watermark.h" 57 58 bool intel_display_driver_probe_defer(struct pci_dev *pdev) 59 { 60 struct drm_privacy_screen *privacy_screen; 61 62 /* 63 * apple-gmux is needed on dual GPU MacBook Pro 64 * to probe the panel if we're the inactive GPU. 65 */ 66 if (vga_switcheroo_client_probe_defer(pdev)) 67 return true; 68 69 /* If the LCD panel has a privacy-screen, wait for it */ 70 #ifdef notyet 71 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 72 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 73 return true; 74 75 drm_privacy_screen_put(privacy_screen); 76 #endif 77 78 return false; 79 } 80 81 void intel_display_driver_init_hw(struct drm_i915_private *i915) 82 { 83 struct intel_cdclk_state *cdclk_state; 84 85 if (!HAS_DISPLAY(i915)) 86 return; 87 88 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); 89 90 intel_update_cdclk(i915); 91 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); 92 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; 93 } 94 95 static const struct drm_mode_config_funcs intel_mode_funcs = { 96 .fb_create = intel_user_framebuffer_create, 97 .get_format_info = intel_fb_get_format_info, 98 .output_poll_changed = intel_fbdev_output_poll_changed, 99 .mode_valid = intel_mode_valid, 100 .atomic_check = intel_atomic_check, 101 .atomic_commit = intel_atomic_commit, 102 .atomic_state_alloc = intel_atomic_state_alloc, 103 .atomic_state_clear = intel_atomic_state_clear, 104 .atomic_state_free = intel_atomic_state_free, 105 }; 106 107 static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = { 108 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 109 }; 110 111 static void intel_mode_config_init(struct drm_i915_private *i915) 112 { 113 struct drm_mode_config *mode_config = &i915->drm.mode_config; 114 115 drm_mode_config_init(&i915->drm); 116 INIT_LIST_HEAD(&i915->display.global.obj_list); 117 118 mode_config->min_width = 0; 119 mode_config->min_height = 0; 120 121 mode_config->preferred_depth = 24; 122 mode_config->prefer_shadow = 1; 123 124 mode_config->funcs = &intel_mode_funcs; 125 mode_config->helper_private = &intel_mode_config_funcs; 126 127 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 128 129 /* 130 * Maximum framebuffer dimensions, chosen to match 131 * the maximum render engine surface size on gen4+. 132 */ 133 if (DISPLAY_VER(i915) >= 7) { 134 mode_config->max_width = 16384; 135 mode_config->max_height = 16384; 136 } else if (DISPLAY_VER(i915) >= 4) { 137 mode_config->max_width = 8192; 138 mode_config->max_height = 8192; 139 } else if (DISPLAY_VER(i915) == 3) { 140 mode_config->max_width = 4096; 141 mode_config->max_height = 4096; 142 } else { 143 mode_config->max_width = 2048; 144 mode_config->max_height = 2048; 145 } 146 147 if (IS_I845G(i915) || IS_I865G(i915)) { 148 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 149 mode_config->cursor_height = 1023; 150 } else if (IS_I830(i915) || IS_I85X(i915) || 151 IS_I915G(i915) || IS_I915GM(i915)) { 152 mode_config->cursor_width = 64; 153 mode_config->cursor_height = 64; 154 } else { 155 mode_config->cursor_width = 256; 156 mode_config->cursor_height = 256; 157 } 158 } 159 160 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 161 { 162 intel_atomic_global_obj_cleanup(i915); 163 drm_mode_config_cleanup(&i915->drm); 164 } 165 166 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 167 { 168 struct intel_plane *plane; 169 170 for_each_intel_plane(&dev_priv->drm, plane) { 171 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 172 plane->pipe); 173 174 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 175 } 176 } 177 178 void intel_display_driver_early_probe(struct drm_i915_private *i915) 179 { 180 if (!HAS_DISPLAY(i915)) 181 return; 182 183 intel_display_irq_init(i915); 184 intel_dkl_phy_init(i915); 185 intel_color_init_hooks(i915); 186 intel_init_cdclk_hooks(i915); 187 intel_audio_hooks_init(i915); 188 intel_dpll_init_clock_hook(i915); 189 intel_init_display_hooks(i915); 190 intel_fdi_init_hook(i915); 191 } 192 193 /* part #1: call before irq install */ 194 int intel_display_driver_probe_noirq(struct drm_i915_private *i915) 195 { 196 int ret; 197 198 if (i915_inject_probe_failure(i915)) 199 return -ENODEV; 200 201 if (HAS_DISPLAY(i915)) { 202 ret = drm_vblank_init(&i915->drm, 203 INTEL_NUM_PIPES(i915)); 204 if (ret) 205 return ret; 206 } 207 208 intel_bios_init(i915); 209 210 ret = intel_vga_register(i915); 211 if (ret) 212 goto cleanup_bios; 213 214 /* FIXME: completely on the wrong abstraction layer */ 215 ret = intel_power_domains_init(i915); 216 if (ret < 0) 217 goto cleanup_vga; 218 219 intel_pmdemand_init_early(i915); 220 221 intel_power_domains_init_hw(i915, false); 222 223 if (!HAS_DISPLAY(i915)) 224 return 0; 225 226 intel_dmc_init(i915); 227 228 i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); 229 i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | 230 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 231 232 intel_mode_config_init(i915); 233 234 ret = intel_cdclk_init(i915); 235 if (ret) 236 goto cleanup_vga_client_pw_domain_dmc; 237 238 ret = intel_color_init(i915); 239 if (ret) 240 goto cleanup_vga_client_pw_domain_dmc; 241 242 ret = intel_dbuf_init(i915); 243 if (ret) 244 goto cleanup_vga_client_pw_domain_dmc; 245 246 ret = intel_bw_init(i915); 247 if (ret) 248 goto cleanup_vga_client_pw_domain_dmc; 249 250 ret = intel_pmdemand_init(i915); 251 if (ret) 252 goto cleanup_vga_client_pw_domain_dmc; 253 254 init_llist_head(&i915->display.atomic_helper.free_list); 255 INIT_WORK(&i915->display.atomic_helper.free_work, 256 intel_atomic_helper_free_state_worker); 257 258 intel_init_quirks(i915); 259 260 intel_fbc_init(i915); 261 262 return 0; 263 264 cleanup_vga_client_pw_domain_dmc: 265 intel_dmc_fini(i915); 266 intel_power_domains_driver_remove(i915); 267 cleanup_vga: 268 intel_vga_unregister(i915); 269 cleanup_bios: 270 intel_bios_driver_remove(i915); 271 272 return ret; 273 } 274 275 /* part #2: call after irq install, but before gem init */ 276 int intel_display_driver_probe_nogem(struct drm_i915_private *i915) 277 { 278 struct drm_device *dev = &i915->drm; 279 enum pipe pipe; 280 int ret; 281 282 if (!HAS_DISPLAY(i915)) 283 return 0; 284 285 intel_wm_init(i915); 286 287 intel_panel_sanitize_ssc(i915); 288 289 intel_pps_setup(i915); 290 291 intel_gmbus_setup(i915); 292 293 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 294 INTEL_NUM_PIPES(i915), 295 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 296 297 for_each_pipe(i915, pipe) { 298 ret = intel_crtc_init(i915, pipe); 299 if (ret) { 300 intel_mode_config_cleanup(i915); 301 return ret; 302 } 303 } 304 305 intel_plane_possible_crtcs_init(i915); 306 intel_shared_dpll_init(i915); 307 intel_fdi_pll_freq_update(i915); 308 309 intel_update_czclk(i915); 310 intel_display_driver_init_hw(i915); 311 intel_dpll_update_ref_clks(i915); 312 313 intel_hdcp_component_init(i915); 314 315 if (i915->display.cdclk.max_cdclk_freq == 0) 316 intel_update_max_cdclk(i915); 317 318 intel_hti_init(i915); 319 320 /* Just disable it once at startup */ 321 intel_vga_disable(i915); 322 intel_setup_outputs(i915); 323 324 drm_modeset_lock_all(dev); 325 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx); 326 intel_acpi_assign_connector_fwnodes(i915); 327 drm_modeset_unlock_all(dev); 328 329 intel_initial_plane_config(i915); 330 331 /* 332 * Make sure hardware watermarks really match the state we read out. 333 * Note that we need to do this after reconstructing the BIOS fb's 334 * since the watermark calculation done here will use pstate->fb. 335 */ 336 if (!HAS_GMCH(i915)) 337 ilk_wm_sanitize(i915); 338 339 return 0; 340 } 341 342 /* part #3: call after gem init */ 343 int intel_display_driver_probe(struct drm_i915_private *i915) 344 { 345 int ret; 346 347 if (!HAS_DISPLAY(i915)) 348 return 0; 349 350 /* 351 * Force all active planes to recompute their states. So that on 352 * mode_setcrtc after probe, all the intel_plane_state variables 353 * are already calculated and there is no assert_plane warnings 354 * during bootup. 355 */ 356 ret = intel_initial_commit(&i915->drm); 357 if (ret) 358 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 359 360 intel_overlay_setup(i915); 361 362 ret = intel_fbdev_init(&i915->drm); 363 if (ret) 364 return ret; 365 366 /* Only enable hotplug handling once the fbdev is fully set up. */ 367 intel_hpd_init(i915); 368 intel_hpd_poll_disable(i915); 369 370 skl_watermark_ipc_init(i915); 371 372 return 0; 373 } 374 375 void intel_display_driver_register(struct drm_i915_private *i915) 376 { 377 if (!HAS_DISPLAY(i915)) 378 return; 379 380 /* Must be done after probing outputs */ 381 intel_opregion_register(i915); 382 intel_acpi_video_register(i915); 383 384 intel_audio_init(i915); 385 386 intel_audio_register(i915); 387 388 intel_display_debugfs_register(i915); 389 390 /* 391 * Some ports require correctly set-up hpd registers for 392 * detection to work properly (leading to ghost connected 393 * connector status), e.g. VGA on gm45. Hence we can only set 394 * up the initial fbdev config after hpd irqs are fully 395 * enabled. We do it last so that the async config cannot run 396 * before the connectors are registered. 397 */ 398 intel_fbdev_initial_config_async(i915); 399 400 /* 401 * We need to coordinate the hotplugs with the asynchronous 402 * fbdev configuration, for which we use the 403 * fbdev->async_cookie. 404 */ 405 drm_kms_helper_poll_init(&i915->drm); 406 } 407 408 /* part #1: call before irq uninstall */ 409 void intel_display_driver_remove(struct drm_i915_private *i915) 410 { 411 if (!HAS_DISPLAY(i915)) 412 return; 413 414 flush_workqueue(i915->display.wq.flip); 415 flush_workqueue(i915->display.wq.modeset); 416 417 flush_work(&i915->display.atomic_helper.free_work); 418 drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list)); 419 420 /* 421 * MST topology needs to be suspended so we don't have any calls to 422 * fbdev after it's finalized. MST will be destroyed later as part of 423 * drm_mode_config_cleanup() 424 */ 425 intel_dp_mst_suspend(i915); 426 } 427 428 /* part #2: call after irq uninstall */ 429 void intel_display_driver_remove_noirq(struct drm_i915_private *i915) 430 { 431 if (!HAS_DISPLAY(i915)) 432 return; 433 434 /* 435 * Due to the hpd irq storm handling the hotplug work can re-arm the 436 * poll handlers. Hence disable polling after hpd handling is shut down. 437 */ 438 intel_hpd_poll_fini(i915); 439 440 /* poll work can call into fbdev, hence clean that up afterwards */ 441 intel_fbdev_fini(i915); 442 443 intel_unregister_dsm_handler(); 444 445 /* flush any delayed tasks or pending work */ 446 flush_workqueue(i915->unordered_wq); 447 448 intel_hdcp_component_fini(i915); 449 450 intel_mode_config_cleanup(i915); 451 452 intel_overlay_cleanup(i915); 453 454 intel_gmbus_teardown(i915); 455 456 destroy_workqueue(i915->display.wq.flip); 457 destroy_workqueue(i915->display.wq.modeset); 458 459 intel_fbc_cleanup(i915); 460 } 461 462 /* part #3: call after gem init */ 463 void intel_display_driver_remove_nogem(struct drm_i915_private *i915) 464 { 465 intel_dmc_fini(i915); 466 467 intel_power_domains_driver_remove(i915); 468 469 intel_vga_unregister(i915); 470 471 intel_bios_driver_remove(i915); 472 } 473 474 void intel_display_driver_unregister(struct drm_i915_private *i915) 475 { 476 if (!HAS_DISPLAY(i915)) 477 return; 478 479 intel_fbdev_unregister(i915); 480 intel_audio_deinit(i915); 481 482 /* 483 * After flushing the fbdev (incl. a late async config which 484 * will have delayed queuing of a hotplug event), then flush 485 * the hotplug events. 486 */ 487 drm_kms_helper_poll_fini(&i915->drm); 488 drm_atomic_helper_shutdown(&i915->drm); 489 490 acpi_video_unregister(); 491 intel_opregion_unregister(i915); 492 } 493 494 /* 495 * turn all crtc's off, but do not adjust state 496 * This has to be paired with a call to intel_modeset_setup_hw_state. 497 */ 498 int intel_display_driver_suspend(struct drm_i915_private *i915) 499 { 500 struct drm_atomic_state *state; 501 int ret; 502 503 if (!HAS_DISPLAY(i915)) 504 return 0; 505 506 state = drm_atomic_helper_suspend(&i915->drm); 507 ret = PTR_ERR_OR_ZERO(state); 508 if (ret) 509 drm_err(&i915->drm, "Suspending crtc's failed with %i\n", 510 ret); 511 else 512 i915->display.restore.modeset_state = state; 513 return ret; 514 } 515 516 int 517 __intel_display_driver_resume(struct drm_i915_private *i915, 518 struct drm_atomic_state *state, 519 struct drm_modeset_acquire_ctx *ctx) 520 { 521 struct drm_crtc_state *crtc_state; 522 struct drm_crtc *crtc; 523 int ret, i; 524 525 intel_modeset_setup_hw_state(i915, ctx); 526 intel_vga_redisable(i915); 527 528 if (!state) 529 return 0; 530 531 /* 532 * We've duplicated the state, pointers to the old state are invalid. 533 * 534 * Don't attempt to use the old state until we commit the duplicated state. 535 */ 536 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 537 /* 538 * Force recalculation even if we restore 539 * current state. With fast modeset this may not result 540 * in a modeset when the state is compatible. 541 */ 542 crtc_state->mode_changed = true; 543 } 544 545 /* ignore any reset values/BIOS leftovers in the WM registers */ 546 if (!HAS_GMCH(i915)) 547 to_intel_atomic_state(state)->skip_intermediate_wm = true; 548 549 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 550 551 drm_WARN_ON(&i915->drm, ret == -EDEADLK); 552 553 return ret; 554 } 555 556 void intel_display_driver_resume(struct drm_i915_private *i915) 557 { 558 struct drm_atomic_state *state = i915->display.restore.modeset_state; 559 struct drm_modeset_acquire_ctx ctx; 560 int ret; 561 562 if (!HAS_DISPLAY(i915)) 563 return; 564 565 i915->display.restore.modeset_state = NULL; 566 if (state) 567 state->acquire_ctx = &ctx; 568 569 drm_modeset_acquire_init(&ctx, 0); 570 571 while (1) { 572 ret = drm_modeset_lock_all_ctx(&i915->drm, &ctx); 573 if (ret != -EDEADLK) 574 break; 575 576 drm_modeset_backoff(&ctx); 577 } 578 579 if (!ret) 580 ret = __intel_display_driver_resume(i915, state, &ctx); 581 582 skl_watermark_ipc_update(i915); 583 drm_modeset_drop_locks(&ctx); 584 drm_modeset_acquire_fini(&ctx); 585 586 if (ret) 587 drm_err(&i915->drm, 588 "Restoring old state failed with %i\n", ret); 589 if (state) 590 drm_atomic_state_put(state); 591 } 592