xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/intel_csr.c (revision 1b83323c0bdad9c107ce4d58bfa3a1d22f04422f)
1 /*	$NetBSD: intel_csr.c,v 1.9 2021/12/27 11:06:49 riastradh Exp $	*/
2 
3 /*
4  * Copyright © 2014 Intel Corporation
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23  * IN THE SOFTWARE.
24  *
25  */
26 
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: intel_csr.c,v 1.9 2021/12/27 11:06:49 riastradh Exp $");
29 
30 #include <linux/firmware.h>
31 
32 #include "i915_drv.h"
33 #include "i915_reg.h"
34 #include "intel_csr.h"
35 
36 /**
37  * DOC: csr support for dmc
38  *
39  * Display Context Save and Restore (CSR) firmware support added from gen9
40  * onwards to drive newly added DMC (Display microcontroller) in display
41  * engine to save and restore the state of display engine when it enter into
42  * low-power state and comes back to normal.
43  */
44 
45 #define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
46 
47 #define TGL_CSR_PATH			"i915/tgl_dmc_ver2_04.bin"
48 #define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 4)
49 #define TGL_CSR_MAX_FW_SIZE		0x6000
50 MODULE_FIRMWARE(TGL_CSR_PATH);
51 
52 #define ICL_CSR_PATH			"i915/icl_dmc_ver1_09.bin"
53 #define ICL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 9)
54 #define ICL_CSR_MAX_FW_SIZE		0x6000
55 MODULE_FIRMWARE(ICL_CSR_PATH);
56 
57 #define CNL_CSR_PATH			"i915/cnl_dmc_ver1_07.bin"
58 #define CNL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 7)
59 #define CNL_CSR_MAX_FW_SIZE		GLK_CSR_MAX_FW_SIZE
60 MODULE_FIRMWARE(CNL_CSR_PATH);
61 
62 #define GLK_CSR_PATH			"i915/glk_dmc_ver1_04.bin"
63 #define GLK_CSR_VERSION_REQUIRED	CSR_VERSION(1, 4)
64 #define GLK_CSR_MAX_FW_SIZE		0x4000
65 MODULE_FIRMWARE(GLK_CSR_PATH);
66 
67 #define KBL_CSR_PATH			"i915/kbl_dmc_ver1_04.bin"
68 #define KBL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 4)
69 #define KBL_CSR_MAX_FW_SIZE		BXT_CSR_MAX_FW_SIZE
70 MODULE_FIRMWARE(KBL_CSR_PATH);
71 
72 #define SKL_CSR_PATH			"i915/skl_dmc_ver1_27.bin"
73 #define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 27)
74 #define SKL_CSR_MAX_FW_SIZE		BXT_CSR_MAX_FW_SIZE
75 MODULE_FIRMWARE(SKL_CSR_PATH);
76 
77 #define BXT_CSR_PATH			"i915/bxt_dmc_ver1_07.bin"
78 #define BXT_CSR_VERSION_REQUIRED	CSR_VERSION(1, 7)
79 #define BXT_CSR_MAX_FW_SIZE		0x3000
80 MODULE_FIRMWARE(BXT_CSR_PATH);
81 
82 #define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
83 #define PACKAGE_MAX_FW_INFO_ENTRIES	20
84 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES	32
85 #define DMC_V1_MAX_MMIO_COUNT		8
86 #define DMC_V3_MAX_MMIO_COUNT		20
87 
88 struct intel_css_header {
89 	/* 0x09 for DMC */
90 	u32 module_type;
91 
92 	/* Includes the DMC specific header in dwords */
93 	u32 header_len;
94 
95 	/* always value would be 0x10000 */
96 	u32 header_ver;
97 
98 	/* Not used */
99 	u32 module_id;
100 
101 	/* Not used */
102 	u32 module_vendor;
103 
104 	/* in YYYYMMDD format */
105 	u32 date;
106 
107 	/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
108 	u32 size;
109 
110 	/* Not used */
111 	u32 key_size;
112 
113 	/* Not used */
114 	u32 modulus_size;
115 
116 	/* Not used */
117 	u32 exponent_size;
118 
119 	/* Not used */
120 	u32 reserved1[12];
121 
122 	/* Major Minor */
123 	u32 version;
124 
125 	/* Not used */
126 	u32 reserved2[8];
127 
128 	/* Not used */
129 	u32 kernel_header_info;
130 } __packed;
131 
132 struct intel_fw_info {
133 	u8 reserved1;
134 
135 	/* reserved on package_header version 1, must be 0 on version 2 */
136 	u8 dmc_id;
137 
138 	/* Stepping (A, B, C, ..., *). * is a wildcard */
139 	char stepping;
140 
141 	/* Sub-stepping (0, 1, ..., *). * is a wildcard */
142 	char substepping;
143 
144 	u32 offset;
145 	u32 reserved2;
146 } __packed;
147 
148 struct intel_package_header {
149 	/* DMC container header length in dwords */
150 	u8 header_len;
151 
152 	/* 0x01, 0x02 */
153 	u8 header_ver;
154 
155 	u8 reserved[10];
156 
157 	/* Number of valid entries in the FWInfo array below */
158 	u32 num_entries;
159 } __packed;
160 
161 struct intel_dmc_header_base {
162 	/* always value would be 0x40403E3E */
163 	u32 signature;
164 
165 	/* DMC binary header length */
166 	u8 header_len;
167 
168 	/* 0x01 */
169 	u8 header_ver;
170 
171 	/* Reserved */
172 	u16 dmcc_ver;
173 
174 	/* Major, Minor */
175 	u32 project;
176 
177 	/* Firmware program size (excluding header) in dwords */
178 	u32 fw_size;
179 
180 	/* Major Minor version */
181 	u32 fw_version;
182 } __packed;
183 
184 struct intel_dmc_header_v1 {
185 	struct intel_dmc_header_base base;
186 
187 	/* Number of valid MMIO cycles present. */
188 	u32 mmio_count;
189 
190 	/* MMIO address */
191 	u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
192 
193 	/* MMIO data */
194 	u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
195 
196 	/* FW filename  */
197 	char dfile[32];
198 
199 	u32 reserved1[2];
200 } __packed;
201 
202 struct intel_dmc_header_v3 {
203 	struct intel_dmc_header_base base;
204 
205 	/* DMC RAM start MMIO address */
206 	u32 start_mmioaddr;
207 
208 	u32 reserved[9];
209 
210 	/* FW filename */
211 	char dfile[32];
212 
213 	/* Number of valid MMIO cycles present. */
214 	u32 mmio_count;
215 
216 	/* MMIO address */
217 	u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
218 
219 	/* MMIO data */
220 	u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
221 } __packed;
222 
223 struct stepping_info {
224 	char stepping;
225 	char substepping;
226 };
227 
228 /*
229  * Kabylake derivated from Skylake H0, so SKL H0
230  * is the right firmware for KBL A0 (revid 0).
231  */
232 static const struct stepping_info kbl_stepping_info[] __unused = {
233 	{'H', '0'}, {'I', '0'}
234 };
235 
236 static const struct stepping_info skl_stepping_info[] = {
237 	{'A', '0'}, {'B', '0'}, {'C', '0'},
238 	{'D', '0'}, {'E', '0'}, {'F', '0'},
239 	{'G', '0'}, {'H', '0'}, {'I', '0'},
240 	{'J', '0'}, {'K', '0'}
241 };
242 
243 static const struct stepping_info bxt_stepping_info[] = {
244 	{'A', '0'}, {'A', '1'}, {'A', '2'},
245 	{'B', '0'}, {'B', '1'}, {'B', '2'}
246 };
247 
248 static const struct stepping_info icl_stepping_info[] = {
249 	{'A', '0'}, {'A', '1'}, {'A', '2'},
250 	{'B', '0'}, {'B', '2'},
251 	{'C', '0'}
252 };
253 
254 static const struct stepping_info no_stepping_info = { '*', '*' };
255 
256 static const struct stepping_info *
intel_get_stepping_info(struct drm_i915_private * dev_priv)257 intel_get_stepping_info(struct drm_i915_private *dev_priv)
258 {
259 	const struct stepping_info *si;
260 	unsigned int size;
261 
262 	if (IS_ICELAKE(dev_priv)) {
263 		size = ARRAY_SIZE(icl_stepping_info);
264 		si = icl_stepping_info;
265 	} else if (IS_SKYLAKE(dev_priv)) {
266 		size = ARRAY_SIZE(skl_stepping_info);
267 		si = skl_stepping_info;
268 	} else if (IS_BROXTON(dev_priv)) {
269 		size = ARRAY_SIZE(bxt_stepping_info);
270 		si = bxt_stepping_info;
271 	} else {
272 		size = 0;
273 		si = NULL;
274 	}
275 
276 	if (INTEL_REVID(dev_priv) < size)
277 		return si + INTEL_REVID(dev_priv);
278 
279 	return &no_stepping_info;
280 }
281 
gen9_set_dc_state_debugmask(struct drm_i915_private * dev_priv)282 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
283 {
284 	u32 val, mask;
285 
286 	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
287 
288 	if (IS_GEN9_LP(dev_priv))
289 		mask |= DC_STATE_DEBUG_MASK_CORES;
290 
291 	/* The below bit doesn't need to be cleared ever afterwards */
292 	val = I915_READ(DC_STATE_DEBUG);
293 	if ((val & mask) != mask) {
294 		val |= mask;
295 		I915_WRITE(DC_STATE_DEBUG, val);
296 		POSTING_READ(DC_STATE_DEBUG);
297 	}
298 }
299 
300 /**
301  * intel_csr_load_program() - write the firmware from memory to register.
302  * @dev_priv: i915 drm device.
303  *
304  * CSR firmware is read from a .bin file and kept in internal memory one time.
305  * Everytime display comes back from low power state this function is called to
306  * copy the firmware from internal memory to registers.
307  */
intel_csr_load_program(struct drm_i915_private * dev_priv)308 void intel_csr_load_program(struct drm_i915_private *dev_priv)
309 {
310 	u32 *payload = dev_priv->csr.dmc_payload;
311 	u32 i, fw_size;
312 
313 	if (!HAS_CSR(dev_priv)) {
314 		DRM_ERROR("No CSR support available for this platform\n");
315 		return;
316 	}
317 
318 	if (!dev_priv->csr.dmc_payload) {
319 		DRM_ERROR("Tried to program CSR with empty payload\n");
320 		return;
321 	}
322 
323 	fw_size = dev_priv->csr.dmc_fw_size;
324 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
325 
326 	preempt_disable();
327 
328 	for (i = 0; i < fw_size; i++)
329 		I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
330 
331 	preempt_enable();
332 
333 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
334 		I915_WRITE(dev_priv->csr.mmioaddr[i],
335 			   dev_priv->csr.mmiodata[i]);
336 	}
337 
338 	dev_priv->csr.dc_state = 0;
339 
340 	gen9_set_dc_state_debugmask(dev_priv);
341 }
342 
343 /*
344  * Search fw_info table for dmc_offset to find firmware binary: num_entries is
345  * already sanitized.
346  */
find_dmc_fw_offset(const struct intel_fw_info * fw_info,unsigned int num_entries,const struct stepping_info * si,u8 package_ver)347 static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
348 			      unsigned int num_entries,
349 			      const struct stepping_info *si,
350 			      u8 package_ver)
351 {
352 	u32 dmc_offset = CSR_DEFAULT_FW_OFFSET;
353 	unsigned int i;
354 
355 	for (i = 0; i < num_entries; i++) {
356 		if (package_ver > 1 && fw_info[i].dmc_id != 0)
357 			continue;
358 
359 		if (fw_info[i].substepping == '*' &&
360 		    si->stepping == fw_info[i].stepping) {
361 			dmc_offset = fw_info[i].offset;
362 			break;
363 		}
364 
365 		if (si->stepping == fw_info[i].stepping &&
366 		    si->substepping == fw_info[i].substepping) {
367 			dmc_offset = fw_info[i].offset;
368 			break;
369 		}
370 
371 		if (fw_info[i].stepping == '*' &&
372 		    fw_info[i].substepping == '*') {
373 			/*
374 			 * In theory we should stop the search as generic
375 			 * entries should always come after the more specific
376 			 * ones, but let's continue to make sure to work even
377 			 * with "broken" firmwares. If we don't find a more
378 			 * specific one, then we use this entry
379 			 */
380 			dmc_offset = fw_info[i].offset;
381 		}
382 	}
383 
384 	return dmc_offset;
385 }
386 
parse_csr_fw_dmc(struct intel_csr * csr,const struct intel_dmc_header_base * dmc_header,size_t rem_size)387 static u32 parse_csr_fw_dmc(struct intel_csr *csr,
388 			    const struct intel_dmc_header_base *dmc_header,
389 			    size_t rem_size)
390 {
391 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
392 	const u32 *mmioaddr, *mmiodata;
393 	u32 mmio_count, mmio_count_max;
394 	const u8 *payload;
395 
396 	BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
397 		     ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
398 
399 	/*
400 	 * Check if we can access common fields, we will checkc again below
401 	 * after we have read the version
402 	 */
403 	if (rem_size < sizeof(struct intel_dmc_header_base))
404 		goto error_truncated;
405 
406 	/* Cope with small differences between v1 and v3 */
407 	if (dmc_header->header_ver == 3) {
408 		const struct intel_dmc_header_v3 *v3 =
409 			(const struct intel_dmc_header_v3 *)dmc_header;
410 
411 		if (rem_size < sizeof(struct intel_dmc_header_v3))
412 			goto error_truncated;
413 
414 		mmioaddr = v3->mmioaddr;
415 		mmiodata = v3->mmiodata;
416 		mmio_count = v3->mmio_count;
417 		mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
418 		/* header_len is in dwords */
419 		header_len_bytes = dmc_header->header_len * 4;
420 		dmc_header_size = sizeof(*v3);
421 	} else if (dmc_header->header_ver == 1) {
422 		const struct intel_dmc_header_v1 *v1 =
423 			(const struct intel_dmc_header_v1 *)dmc_header;
424 
425 		if (rem_size < sizeof(struct intel_dmc_header_v1))
426 			goto error_truncated;
427 
428 		mmioaddr = v1->mmioaddr;
429 		mmiodata = v1->mmiodata;
430 		mmio_count = v1->mmio_count;
431 		mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
432 		header_len_bytes = dmc_header->header_len;
433 		dmc_header_size = sizeof(*v1);
434 	} else {
435 		DRM_ERROR("Unknown DMC fw header version: %u\n",
436 			  dmc_header->header_ver);
437 		return 0;
438 	}
439 
440 	if (header_len_bytes != dmc_header_size) {
441 		DRM_ERROR("DMC firmware has wrong dmc header length "
442 			  "(%u bytes)\n", header_len_bytes);
443 		return 0;
444 	}
445 
446 	/* Cache the dmc header info. */
447 	if (mmio_count > mmio_count_max) {
448 		DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
449 		return 0;
450 	}
451 
452 	for (i = 0; i < mmio_count; i++) {
453 		if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
454 		    mmioaddr[i] > CSR_MMIO_END_RANGE) {
455 			DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
456 				  mmioaddr[i]);
457 			return 0;
458 		}
459 		csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
460 		csr->mmiodata[i] = mmiodata[i];
461 	}
462 	csr->mmio_count = mmio_count;
463 
464 	rem_size -= header_len_bytes;
465 
466 	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
467 	payload_size = dmc_header->fw_size * 4;
468 	if (rem_size < payload_size)
469 		goto error_truncated;
470 
471 	if (payload_size > csr->max_fw_size) {
472 		DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
473 		return 0;
474 	}
475 	csr->dmc_fw_size = dmc_header->fw_size;
476 
477 	csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
478 	if (!csr->dmc_payload) {
479 		DRM_ERROR("Memory allocation failed for dmc payload\n");
480 		return 0;
481 	}
482 
483 	payload = (const u8 *)(dmc_header) + header_len_bytes;
484 	memcpy(csr->dmc_payload, payload, payload_size);
485 
486 	return header_len_bytes + payload_size;
487 
488 error_truncated:
489 	DRM_ERROR("Truncated DMC firmware, refusing.\n");
490 	return 0;
491 }
492 
493 static u32
parse_csr_fw_package(struct intel_csr * csr,const struct intel_package_header * package_header,const struct stepping_info * si,size_t rem_size)494 parse_csr_fw_package(struct intel_csr *csr,
495 		     const struct intel_package_header *package_header,
496 		     const struct stepping_info *si,
497 		     size_t rem_size)
498 {
499 	u32 package_size = sizeof(struct intel_package_header);
500 	u32 num_entries, max_entries, dmc_offset;
501 	const struct intel_fw_info *fw_info;
502 
503 	if (rem_size < package_size)
504 		goto error_truncated;
505 
506 	if (package_header->header_ver == 1) {
507 		max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
508 	} else if (package_header->header_ver == 2) {
509 		max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
510 	} else {
511 		DRM_ERROR("DMC firmware has unknown header version %u\n",
512 			  package_header->header_ver);
513 		return 0;
514 	}
515 
516 	/*
517 	 * We should always have space for max_entries,
518 	 * even if not all are used
519 	 */
520 	package_size += max_entries * sizeof(struct intel_fw_info);
521 	if (rem_size < package_size)
522 		goto error_truncated;
523 
524 	if (package_header->header_len * 4 != package_size) {
525 		DRM_ERROR("DMC firmware has wrong package header length "
526 			  "(%u bytes)\n", package_size);
527 		return 0;
528 	}
529 
530 	num_entries = package_header->num_entries;
531 	if (WARN_ON(package_header->num_entries > max_entries))
532 		num_entries = max_entries;
533 
534 	fw_info = (const struct intel_fw_info *)
535 		((const u8 *)package_header + sizeof(*package_header));
536 	dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
537 					package_header->header_ver);
538 	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
539 		DRM_ERROR("DMC firmware not supported for %c stepping\n",
540 			  si->stepping);
541 		return 0;
542 	}
543 
544 	/* dmc_offset is in dwords */
545 	return package_size + dmc_offset * 4;
546 
547 error_truncated:
548 	DRM_ERROR("Truncated DMC firmware, refusing.\n");
549 	return 0;
550 }
551 
552 /* Return number of bytes parsed or 0 on error */
parse_csr_fw_css(struct intel_csr * csr,struct intel_css_header * css_header,size_t rem_size)553 static u32 parse_csr_fw_css(struct intel_csr *csr,
554 			    struct intel_css_header *css_header,
555 			    size_t rem_size)
556 {
557 	if (rem_size < sizeof(struct intel_css_header)) {
558 		DRM_ERROR("Truncated DMC firmware, refusing.\n");
559 		return 0;
560 	}
561 
562 	if (sizeof(struct intel_css_header) !=
563 	    (css_header->header_len * 4)) {
564 		DRM_ERROR("DMC firmware has wrong CSS header length "
565 			  "(%u bytes)\n",
566 			  (css_header->header_len * 4));
567 		return 0;
568 	}
569 
570 	if (csr->required_version &&
571 	    css_header->version != csr->required_version) {
572 		DRM_INFO("Refusing to load DMC firmware v%u.%u,"
573 			 " please use v%u.%u\n",
574 			 CSR_VERSION_MAJOR(css_header->version),
575 			 CSR_VERSION_MINOR(css_header->version),
576 			 CSR_VERSION_MAJOR(csr->required_version),
577 			 CSR_VERSION_MINOR(csr->required_version));
578 		return 0;
579 	}
580 
581 	csr->version = css_header->version;
582 
583 	return sizeof(struct intel_css_header);
584 }
585 
parse_csr_fw(struct drm_i915_private * dev_priv,const struct firmware * fw)586 static void parse_csr_fw(struct drm_i915_private *dev_priv,
587 			 const struct firmware *fw)
588 {
589 	struct intel_css_header *css_header;
590 	struct intel_package_header *package_header;
591 	struct intel_dmc_header_base *dmc_header;
592 	struct intel_csr *csr = &dev_priv->csr;
593 	const struct stepping_info *si = intel_get_stepping_info(dev_priv);
594 	u32 readcount = 0;
595 	u32 r;
596 
597 	if (!fw)
598 		return;
599 
600 	/* Extract CSS Header information */
601 	css_header = (struct intel_css_header *)fw->data;
602 	r = parse_csr_fw_css(csr, css_header, fw->size);
603 	if (!r)
604 		return;
605 
606 	readcount += r;
607 
608 	/* Extract Package Header information */
609 	package_header = (struct intel_package_header *)&fw->data[readcount];
610 	r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
611 	if (!r)
612 		return;
613 
614 	readcount += r;
615 
616 	/* Extract dmc_header information */
617 	dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
618 	parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
619 }
620 
intel_csr_runtime_pm_get(struct drm_i915_private * dev_priv)621 static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
622 {
623 	WARN_ON(dev_priv->csr.wakeref);
624 	dev_priv->csr.wakeref =
625 		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
626 }
627 
intel_csr_runtime_pm_put(struct drm_i915_private * dev_priv)628 static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
629 {
630 	intel_wakeref_t wakeref __maybe_unused =
631 		fetch_and_zero(&dev_priv->csr.wakeref);
632 
633 	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
634 }
635 
csr_load_work_fn(struct work_struct * work)636 static void csr_load_work_fn(struct work_struct *work)
637 {
638 	struct drm_i915_private *dev_priv;
639 	struct intel_csr *csr;
640 	const struct firmware *fw = NULL;
641 
642 	dev_priv = container_of(work, typeof(*dev_priv), csr.work);
643 	csr = &dev_priv->csr;
644 
645 	request_firmware(&fw, dev_priv->csr.fw_path,
646 	    pci_dev_dev(dev_priv->drm.pdev));
647 	parse_csr_fw(dev_priv, fw);
648 
649 	if (dev_priv->csr.dmc_payload) {
650 		intel_csr_load_program(dev_priv);
651 		intel_csr_runtime_pm_put(dev_priv);
652 
653 		DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
654 			 dev_priv->csr.fw_path,
655 			 CSR_VERSION_MAJOR(csr->version),
656 			 CSR_VERSION_MINOR(csr->version));
657 	} else {
658 		dev_notice(dev_priv->drm.dev,
659 			   "Failed to load DMC firmware %s."
660 			   " Disabling runtime power management.\n",
661 			   csr->fw_path);
662 #ifndef __NetBSD__
663 		dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
664 			   INTEL_UC_FIRMWARE_URL);
665 #endif
666 	}
667 
668 	release_firmware(fw);
669 }
670 
671 /**
672  * intel_csr_ucode_init() - initialize the firmware loading.
673  * @dev_priv: i915 drm device.
674  *
675  * This function is called at the time of loading the display driver to read
676  * firmware from a .bin file and copied into a internal memory.
677  */
intel_csr_ucode_init(struct drm_i915_private * dev_priv)678 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
679 {
680 	struct intel_csr *csr = &dev_priv->csr;
681 
682 	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
683 
684 	if (!HAS_CSR(dev_priv))
685 		return;
686 
687 	/*
688 	 * Obtain a runtime pm reference, until CSR is loaded, to avoid entering
689 	 * runtime-suspend.
690 	 *
691 	 * On error, we return with the rpm wakeref held to prevent runtime
692 	 * suspend as runtime suspend *requires* a working CSR for whatever
693 	 * reason.
694 	 */
695 	intel_csr_runtime_pm_get(dev_priv);
696 
697 	if (INTEL_GEN(dev_priv) >= 12) {
698 		csr->fw_path = TGL_CSR_PATH;
699 		csr->required_version = TGL_CSR_VERSION_REQUIRED;
700 		/* Allow to load fw via parameter using the last known size */
701 		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
702 	} else if (IS_GEN(dev_priv, 11)) {
703 		csr->fw_path = ICL_CSR_PATH;
704 		csr->required_version = ICL_CSR_VERSION_REQUIRED;
705 		csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
706 	} else if (IS_CANNONLAKE(dev_priv)) {
707 		csr->fw_path = CNL_CSR_PATH;
708 		csr->required_version = CNL_CSR_VERSION_REQUIRED;
709 		csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;
710 	} else if (IS_GEMINILAKE(dev_priv)) {
711 		csr->fw_path = GLK_CSR_PATH;
712 		csr->required_version = GLK_CSR_VERSION_REQUIRED;
713 		csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
714 	} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
715 		csr->fw_path = KBL_CSR_PATH;
716 		csr->required_version = KBL_CSR_VERSION_REQUIRED;
717 		csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;
718 	} else if (IS_SKYLAKE(dev_priv)) {
719 		csr->fw_path = SKL_CSR_PATH;
720 		csr->required_version = SKL_CSR_VERSION_REQUIRED;
721 		csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;
722 	} else if (IS_BROXTON(dev_priv)) {
723 		csr->fw_path = BXT_CSR_PATH;
724 		csr->required_version = BXT_CSR_VERSION_REQUIRED;
725 		csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
726 	}
727 
728 	if (i915_modparams.dmc_firmware_path) {
729 		if (strlen(i915_modparams.dmc_firmware_path) == 0) {
730 			csr->fw_path = NULL;
731 			DRM_INFO("Disabling CSR firmware and runtime PM\n");
732 			return;
733 		}
734 
735 		csr->fw_path = i915_modparams.dmc_firmware_path;
736 		/* Bypass version check for firmware override. */
737 		csr->required_version = 0;
738 	}
739 
740 	if (csr->fw_path == NULL) {
741 		DRM_DEBUG_KMS("No known CSR firmware for platform, disabling runtime PM\n");
742 		return;
743 	}
744 
745 	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
746 	schedule_work(&dev_priv->csr.work);
747 }
748 
749 /**
750  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
751  * @dev_priv: i915 drm device
752  *
753  * Prepare the DMC firmware before entering system suspend. This includes
754  * flushing pending work items and releasing any resources acquired during
755  * init.
756  */
intel_csr_ucode_suspend(struct drm_i915_private * dev_priv)757 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
758 {
759 	if (!HAS_CSR(dev_priv))
760 		return;
761 
762 	flush_work(&dev_priv->csr.work);
763 
764 	/* Drop the reference held in case DMC isn't loaded. */
765 	if (!dev_priv->csr.dmc_payload)
766 		intel_csr_runtime_pm_put(dev_priv);
767 }
768 
769 /**
770  * intel_csr_ucode_resume() - init CSR firmware during system resume
771  * @dev_priv: i915 drm device
772  *
773  * Reinitialize the DMC firmware during system resume, reacquiring any
774  * resources released in intel_csr_ucode_suspend().
775  */
intel_csr_ucode_resume(struct drm_i915_private * dev_priv)776 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
777 {
778 	if (!HAS_CSR(dev_priv))
779 		return;
780 
781 	/*
782 	 * Reacquire the reference to keep RPM disabled in case DMC isn't
783 	 * loaded.
784 	 */
785 	if (!dev_priv->csr.dmc_payload)
786 		intel_csr_runtime_pm_get(dev_priv);
787 }
788 
789 /**
790  * intel_csr_ucode_fini() - unload the CSR firmware.
791  * @dev_priv: i915 drm device.
792  *
793  * Firmmware unloading includes freeing the internal memory and reset the
794  * firmware loading status.
795  */
intel_csr_ucode_fini(struct drm_i915_private * dev_priv)796 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
797 {
798 	if (!HAS_CSR(dev_priv))
799 		return;
800 
801 	intel_csr_ucode_suspend(dev_priv);
802 	WARN_ON(dev_priv->csr.wakeref);
803 
804 	kfree(dev_priv->csr.dmc_payload);
805 }
806