1 /* $NetBSD: kfd_pm4_headers_diq.h,v 1.3 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef KFD_PM4_HEADERS_DIQ_H_ 27 #define KFD_PM4_HEADERS_DIQ_H_ 28 29 /*--------------------_INDIRECT_BUFFER-------------------- */ 30 31 #ifndef _PM4__INDIRECT_BUFFER_DEFINED 32 #define _PM4__INDIRECT_BUFFER_DEFINED 33 enum _INDIRECT_BUFFER_cache_policy_enum { 34 cache_policy___indirect_buffer__lru = 0, 35 cache_policy___indirect_buffer__stream = 1, 36 cache_policy___indirect_buffer__bypass = 2 37 }; 38 39 enum { 40 IT_INDIRECT_BUFFER_PASID = 0x5C 41 }; 42 43 struct pm4__indirect_buffer_pasid { 44 union { 45 union PM4_MES_TYPE_3_HEADER header; /* header */ 46 unsigned int ordinal1; 47 }; 48 49 union { 50 struct { 51 unsigned int reserved1:2; 52 unsigned int ib_base_lo:30; 53 } bitfields2; 54 unsigned int ordinal2; 55 }; 56 57 union { 58 struct { 59 unsigned int ib_base_hi:16; 60 unsigned int reserved2:16; 61 } bitfields3; 62 unsigned int ordinal3; 63 }; 64 65 union { 66 unsigned int control; 67 unsigned int ordinal4; 68 }; 69 70 union { 71 struct { 72 unsigned int pasid:10; 73 unsigned int reserved4:22; 74 } bitfields5; 75 unsigned int ordinal5; 76 }; 77 78 }; 79 80 #endif 81 82 /*--------------------_RELEASE_MEM-------------------- */ 83 84 #ifndef _PM4__RELEASE_MEM_DEFINED 85 #define _PM4__RELEASE_MEM_DEFINED 86 enum _RELEASE_MEM_event_index_enum { 87 event_index___release_mem__end_of_pipe = 5, 88 event_index___release_mem__shader_done = 6 89 }; 90 91 enum _RELEASE_MEM_cache_policy_enum { 92 cache_policy___release_mem__lru = 0, 93 cache_policy___release_mem__stream = 1, 94 cache_policy___release_mem__bypass = 2 95 }; 96 97 enum _RELEASE_MEM_dst_sel_enum { 98 dst_sel___release_mem__memory_controller = 0, 99 dst_sel___release_mem__tc_l2 = 1, 100 dst_sel___release_mem__queue_write_pointer_register = 2, 101 dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3 102 }; 103 104 enum _RELEASE_MEM_int_sel_enum { 105 int_sel___release_mem__none = 0, 106 int_sel___release_mem__send_interrupt_only = 1, 107 int_sel___release_mem__send_interrupt_after_write_confirm = 2, 108 int_sel___release_mem__send_data_after_write_confirm = 3 109 }; 110 111 enum _RELEASE_MEM_data_sel_enum { 112 data_sel___release_mem__none = 0, 113 data_sel___release_mem__send_32_bit_low = 1, 114 data_sel___release_mem__send_64_bit_data = 2, 115 data_sel___release_mem__send_gpu_clock_counter = 3, 116 data_sel___release_mem__send_cp_perfcounter_hi_lo = 4, 117 data_sel___release_mem__store_gds_data_to_memory = 5 118 }; 119 120 struct pm4__release_mem { 121 union { 122 union PM4_MES_TYPE_3_HEADER header; /*header */ 123 unsigned int ordinal1; 124 }; 125 126 union { 127 struct { 128 unsigned int event_type:6; 129 unsigned int reserved1:2; 130 enum _RELEASE_MEM_event_index_enum event_index:4; 131 unsigned int tcl1_vol_action_ena:1; 132 unsigned int tc_vol_action_ena:1; 133 unsigned int reserved2:1; 134 unsigned int tc_wb_action_ena:1; 135 unsigned int tcl1_action_ena:1; 136 unsigned int tc_action_ena:1; 137 unsigned int reserved3:6; 138 unsigned int atc:1; 139 enum _RELEASE_MEM_cache_policy_enum cache_policy:2; 140 unsigned int reserved4:5; 141 } bitfields2; 142 unsigned int ordinal2; 143 }; 144 145 union { 146 struct { 147 unsigned int reserved5:16; 148 enum _RELEASE_MEM_dst_sel_enum dst_sel:2; 149 unsigned int reserved6:6; 150 enum _RELEASE_MEM_int_sel_enum int_sel:3; 151 unsigned int reserved7:2; 152 enum _RELEASE_MEM_data_sel_enum data_sel:3; 153 } bitfields3; 154 unsigned int ordinal3; 155 }; 156 157 union { 158 struct { 159 unsigned int reserved8:2; 160 unsigned int address_lo_32b:30; 161 } bitfields4; 162 struct { 163 unsigned int reserved9:3; 164 unsigned int address_lo_64b:29; 165 } bitfields5; 166 unsigned int ordinal4; 167 }; 168 169 unsigned int address_hi; 170 171 unsigned int data_lo; 172 173 unsigned int data_hi; 174 175 }; 176 #endif 177 178 179 /*--------------------_SET_CONFIG_REG-------------------- */ 180 181 #ifndef _PM4__SET_CONFIG_REG_DEFINED 182 #define _PM4__SET_CONFIG_REG_DEFINED 183 184 struct pm4__set_config_reg { 185 union { 186 union PM4_MES_TYPE_3_HEADER header; /*header */ 187 unsigned int ordinal1; 188 }; 189 190 union { 191 struct { 192 unsigned int reg_offset:16; 193 unsigned int reserved1:7; 194 unsigned int vmid_shift:5; 195 unsigned int insert_vmid:1; 196 unsigned int reserved2:3; 197 } bitfields2; 198 unsigned int ordinal2; 199 }; 200 201 unsigned int reg_data[1]; /*1..N of these fields */ 202 203 }; 204 #endif 205 206 /*--------------------_WAIT_REG_MEM-------------------- */ 207 208 #ifndef _PM4__WAIT_REG_MEM_DEFINED 209 #define _PM4__WAIT_REG_MEM_DEFINED 210 enum _WAIT_REG_MEM_function_enum { 211 function___wait_reg_mem__always_pass = 0, 212 function___wait_reg_mem__less_than_ref_value = 1, 213 function___wait_reg_mem__less_than_equal_to_the_ref_value = 2, 214 function___wait_reg_mem__equal_to_the_reference_value = 3, 215 function___wait_reg_mem__not_equal_reference_value = 4, 216 function___wait_reg_mem__greater_than_or_equal_reference_value = 5, 217 function___wait_reg_mem__greater_than_reference_value = 6, 218 function___wait_reg_mem__reserved = 7 219 }; 220 221 enum _WAIT_REG_MEM_mem_space_enum { 222 mem_space___wait_reg_mem__register_space = 0, 223 mem_space___wait_reg_mem__memory_space = 1 224 }; 225 226 enum _WAIT_REG_MEM_operation_enum { 227 operation___wait_reg_mem__wait_reg_mem = 0, 228 operation___wait_reg_mem__wr_wait_wr_reg = 1 229 }; 230 231 struct pm4__wait_reg_mem { 232 union { 233 union PM4_MES_TYPE_3_HEADER header; /*header */ 234 unsigned int ordinal1; 235 }; 236 237 union { 238 struct { 239 enum _WAIT_REG_MEM_function_enum function:3; 240 unsigned int reserved1:1; 241 enum _WAIT_REG_MEM_mem_space_enum mem_space:2; 242 enum _WAIT_REG_MEM_operation_enum operation:2; 243 unsigned int reserved2:24; 244 } bitfields2; 245 unsigned int ordinal2; 246 }; 247 248 union { 249 struct { 250 unsigned int reserved3:2; 251 unsigned int memory_poll_addr_lo:30; 252 } bitfields3; 253 struct { 254 unsigned int register_poll_addr:16; 255 unsigned int reserved4:16; 256 } bitfields4; 257 struct { 258 unsigned int register_write_addr:16; 259 unsigned int reserved5:16; 260 } bitfields5; 261 unsigned int ordinal3; 262 }; 263 264 union { 265 struct { 266 unsigned int poll_address_hi:16; 267 unsigned int reserved6:16; 268 } bitfields6; 269 struct { 270 unsigned int register_write_addr:16; 271 unsigned int reserved7:16; 272 } bitfields7; 273 unsigned int ordinal4; 274 }; 275 276 unsigned int reference; 277 278 unsigned int mask; 279 280 union { 281 struct { 282 unsigned int poll_interval:16; 283 unsigned int reserved8:16; 284 } bitfields8; 285 unsigned int ordinal7; 286 }; 287 288 }; 289 #endif 290 291 292 #endif /* KFD_PM4_HEADERS_DIQ_H_ */ 293