1 /* $OpenBSD: machdep.c,v 1.674 2024/07/29 18:43:11 kettenis Exp $ */ 2 /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 1993, 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 36 * Copyright (c) 1992 Terrence R. Lambert. 37 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 38 * All rights reserved. 39 * 40 * This code is derived from software contributed to Berkeley by 41 * William Jolitz. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 68 */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/signalvar.h> 73 #include <sys/proc.h> 74 #include <sys/user.h> 75 #include <sys/exec.h> 76 #include <sys/buf.h> 77 #include <sys/reboot.h> 78 #include <sys/conf.h> 79 #include <sys/malloc.h> 80 #include <sys/msgbuf.h> 81 #include <sys/mount.h> 82 #include <sys/device.h> 83 #include <sys/extent.h> 84 #include <sys/sysctl.h> 85 #include <sys/syscallargs.h> 86 #include <sys/core.h> 87 #include <sys/kcore.h> 88 #include <sys/sensors.h> 89 90 #include <dev/cons.h> 91 #include <stand/boot/bootarg.h> 92 93 #include <net/if.h> 94 #include <uvm/uvm_extern.h> 95 96 #include <machine/bus.h> 97 98 #include <machine/cpu.h> 99 #include <machine/cpu_full.h> 100 #include <machine/cpufunc.h> 101 #include <machine/cpuvar.h> 102 #include <machine/kcore.h> 103 #include <machine/pio.h> 104 #include <machine/psl.h> 105 #include <machine/specialreg.h> 106 #include <machine/biosvar.h> 107 #include <machine/pte.h> 108 #ifdef MULTIPROCESSOR 109 #include <machine/mpbiosvar.h> 110 #endif /* MULTIPROCESSOR */ 111 112 #include <dev/isa/isareg.h> 113 #include <dev/ic/i8042reg.h> 114 #include <i386/isa/isa_machdep.h> 115 116 #include "acpi.h" 117 #if NACPI > 0 118 #include <dev/acpi/acpireg.h> 119 #include <dev/acpi/acpivar.h> 120 #endif 121 122 #include "apm.h" 123 #if NAPM > 0 124 #include <machine/apmvar.h> 125 #endif 126 127 #ifdef DDB 128 #include <machine/db_machdep.h> 129 #include <ddb/db_extern.h> 130 #endif 131 132 #include "isa.h" 133 #include "isadma.h" 134 #include "npx.h" 135 #if NNPX > 0 136 extern struct proc *npxproc; 137 #endif 138 139 #include "bios.h" 140 141 #ifdef HIBERNATE 142 #include <machine/hibernate_var.h> 143 #endif /* HIBERNATE */ 144 145 #include "ukbd.h" 146 #include "pckbc.h" 147 #if NPCKBC > 0 && NUKBD > 0 148 #include <dev/ic/pckbcvar.h> 149 #endif 150 151 /* #define MACHDEP_DEBUG */ 152 153 #ifdef MACHDEP_DEBUG 154 #define DPRINTF(x...) do { printf(x); } while (0) 155 #else 156 #define DPRINTF(x...) 157 #endif /* MACHDEP_DEBUG */ 158 159 void replacesmap(void); 160 int intr_handler(struct intrframe *, struct intrhand *); 161 162 /* the following is used externally (sysctl_hw) */ 163 char machine[] = MACHINE; 164 165 /* 166 * switchto vectors 167 */ 168 void (*cpu_idle_leave_fcn)(void) = NULL; 169 void (*cpu_idle_cycle_fcn)(void) = NULL; 170 void (*cpu_idle_enter_fcn)(void) = NULL; 171 void (*cpu_suspend_cycle_fcn)(void); 172 173 174 struct uvm_constraint_range isa_constraint = { 0x0, 0x00ffffffUL }; 175 struct uvm_constraint_range dma_constraint = { 0x0, 0xffffffffUL }; 176 struct uvm_constraint_range *uvm_md_constraints[] = { 177 &isa_constraint, 178 &dma_constraint, 179 NULL 180 }; 181 182 extern int boothowto; 183 int physmem; 184 185 struct dumpmem dumpmem[VM_PHYSSEG_MAX]; 186 u_int ndumpmem; 187 188 /* 189 * These variables are needed by /sbin/savecore 190 */ 191 u_long dumpmag = 0x8fca0101; /* magic number */ 192 int dumpsize = 0; /* pages */ 193 long dumplo = 0; /* blocks */ 194 195 int cpu_class; 196 197 int i386_use_fxsave; 198 int i386_has_sse; 199 int i386_has_sse2; 200 int i386_has_xcrypt; 201 202 bootarg_t *bootargp; 203 paddr_t avail_end; 204 205 struct vm_map *exec_map = NULL; 206 struct vm_map *phys_map = NULL; 207 208 #if !defined(SMALL_KERNEL) 209 int p3_early; 210 void (*update_cpuspeed)(void) = NULL; 211 void via_update_sensor(void *args); 212 #endif 213 int kbd_reset; 214 int lid_action = 1; 215 int pwr_action = 1; 216 int forceukbd; 217 218 /* 219 * safepri is a safe priority for sleep to set for a spin-wait 220 * during autoconfiguration or after a panic. 221 */ 222 int safepri = 0; 223 224 #if !defined(SMALL_KERNEL) 225 int bus_clock; 226 #endif 227 void (*setperf_setup)(struct cpu_info *); 228 int setperf_prio = 0; /* for concurrent handlers */ 229 230 void (*cpusensors_setup)(struct cpu_info *); 231 232 void (*delay_func)(int) = i8254_delay; 233 void (*initclock_func)(void) = i8254_initclocks; 234 void (*startclock_func)(void) = i8254_start_both_clocks; 235 236 /* 237 * Extent maps to manage I/O and ISA memory hole space. Allocate 238 * storage for 16 regions in each, initially. Later, ioport_malloc_safe 239 * will indicate that it's safe to use malloc() to dynamically allocate 240 * region descriptors. 241 * 242 * N.B. At least two regions are _always_ allocated from the iomem 243 * extent map; (0 -> ISA hole) and (end of ISA hole -> end of RAM). 244 * 245 * The extent maps are not static! Machine-dependent ISA and EISA 246 * routines need access to them for bus address space allocation. 247 */ 248 static long ioport_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 249 static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 250 struct extent *ioport_ex; 251 struct extent *iomem_ex; 252 static int ioport_malloc_safe; 253 254 void dumpsys(void); 255 int cpu_dump(void); 256 void init386(paddr_t); 257 void consinit(void); 258 void (*cpuresetfn)(void); 259 260 int bus_mem_add_mapping(bus_addr_t, bus_size_t, 261 int, bus_space_handle_t *); 262 263 #ifdef APERTURE 264 int allowaperture = 0; 265 #endif 266 267 int has_rdrand; 268 int has_rdseed; 269 270 void winchip_cpu_setup(struct cpu_info *); 271 void amd_family5_setperf_setup(struct cpu_info *); 272 void amd_family5_setup(struct cpu_info *); 273 void amd_family6_setperf_setup(struct cpu_info *); 274 void amd_family6_setup(struct cpu_info *); 275 void cyrix3_setperf_setup(struct cpu_info *); 276 void cyrix3_cpu_setup(struct cpu_info *); 277 void cyrix6x86_cpu_setup(struct cpu_info *); 278 void natsem6x86_cpu_setup(struct cpu_info *); 279 void intel586_cpu_setup(struct cpu_info *); 280 void intel686_cpusensors_setup(struct cpu_info *); 281 void intel686_setperf_setup(struct cpu_info *); 282 void intel686_common_cpu_setup(struct cpu_info *); 283 void intel686_cpu_setup(struct cpu_info *); 284 void intel686_p4_cpu_setup(struct cpu_info *); 285 void intelcore_update_sensor(void *); 286 void tm86_cpu_setup(struct cpu_info *); 287 char * intel686_cpu_name(int); 288 char * cyrix3_cpu_name(int, int); 289 char * tm86_cpu_name(int); 290 void cyrix3_get_bus_clock(struct cpu_info *); 291 void p4_get_bus_clock(struct cpu_info *); 292 void p3_get_bus_clock(struct cpu_info *); 293 void p4_update_cpuspeed(void); 294 void p3_update_cpuspeed(void); 295 int pentium_cpuspeed(int *); 296 void enter_shared_special_pages(void); 297 298 static __inline u_char 299 cyrix_read_reg(u_char reg) 300 { 301 outb(0x22, reg); 302 return inb(0x23); 303 } 304 305 static __inline void 306 cyrix_write_reg(u_char reg, u_char data) 307 { 308 outb(0x22, reg); 309 outb(0x23, data); 310 } 311 312 /* 313 * cpuid instruction. request in eax, result in eax, ebx, ecx, edx. 314 * requires caller to provide u_int32_t regs[4] array. 315 */ 316 void 317 cpuid(u_int32_t ax, u_int32_t *regs) 318 { 319 __asm volatile( 320 "cpuid\n\t" 321 "movl %%eax, 0(%2)\n\t" 322 "movl %%ebx, 4(%2)\n\t" 323 "movl %%ecx, 8(%2)\n\t" 324 "movl %%edx, 12(%2)\n\t" 325 :"=a" (ax) 326 :"0" (ax), "S" (regs) 327 :"bx", "cx", "dx"); 328 } 329 330 /* 331 * Machine-dependent startup code 332 */ 333 void 334 cpu_startup(void) 335 { 336 unsigned i; 337 vaddr_t minaddr, maxaddr, va; 338 paddr_t pa; 339 340 /* 341 * Initialize error message buffer (at end of core). 342 * (space reserved in pmap_bootstrap) 343 */ 344 pa = avail_end; 345 va = (vaddr_t)msgbufp; 346 for (i = 0; i < atop(MSGBUFSIZE); i++) { 347 pmap_kenter_pa(va, pa, PROT_READ | PROT_WRITE); 348 va += PAGE_SIZE; 349 pa += PAGE_SIZE; 350 } 351 pmap_update(pmap_kernel()); 352 initmsgbuf((caddr_t)msgbufp, round_page(MSGBUFSIZE)); 353 354 printf("%s", version); 355 startclocks(); 356 rtcinit(); 357 358 printf("real mem = %llu (%lluMB)\n", 359 (unsigned long long)ptoa((psize_t)physmem), 360 (unsigned long long)ptoa((psize_t)physmem)/1024U/1024U); 361 362 /* 363 * Allocate a submap for exec arguments. This map effectively 364 * limits the number of processes exec'ing at any time. 365 */ 366 minaddr = vm_map_min(kernel_map); 367 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 368 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL); 369 370 /* 371 * Allocate a submap for physio 372 */ 373 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 374 VM_PHYS_SIZE, 0, FALSE, NULL); 375 376 printf("avail mem = %llu (%lluMB)\n", 377 (unsigned long long)ptoa((psize_t)uvmexp.free), 378 (unsigned long long)ptoa((psize_t)uvmexp.free)/1024U/1024U); 379 380 /* 381 * Set up buffers, so they can be used to read disk labels. 382 */ 383 bufinit(); 384 385 /* 386 * Configure the system. 387 */ 388 if (boothowto & RB_CONFIG) { 389 #ifdef BOOT_CONFIG 390 user_config(); 391 #else 392 printf("kernel does not support -c; continuing..\n"); 393 #endif 394 } 395 ioport_malloc_safe = 1; 396 397 #ifndef SMALL_KERNEL 398 cpu_ucode_setup(); 399 #endif 400 401 /* enter the IDT and trampoline code in the u-k maps */ 402 enter_shared_special_pages(); 403 404 /* initialize CPU0's TSS and GDT and put them in the u-k maps */ 405 cpu_enter_pages(&cpu_info_full_primary); 406 } 407 408 void 409 enter_shared_special_pages(void) 410 { 411 extern char __kutext_start[], __kutext_end[], __kernel_kutext_phys[]; 412 extern char __kudata_start[], __kudata_end[], __kernel_kudata_phys[]; 413 vaddr_t va; 414 paddr_t pa; 415 416 /* idt */ 417 pmap_extract(pmap_kernel(), (vaddr_t)idt, &pa); 418 pmap_enter_special((vaddr_t)idt, pa, PROT_READ, 0); 419 420 /* .kutext section */ 421 va = (vaddr_t)__kutext_start; 422 pa = (paddr_t)__kernel_kutext_phys; 423 while (va < (vaddr_t)__kutext_end) { 424 pmap_enter_special(va, pa, PROT_READ | PROT_EXEC, 0); 425 DPRINTF("%s: entered kutext page va 0x%08lx pa 0x%08lx\n", 426 __func__, (unsigned long)va, (unsigned long)pa); 427 va += PAGE_SIZE; 428 pa += PAGE_SIZE; 429 } 430 431 /* .kudata section */ 432 va = (vaddr_t)__kudata_start; 433 pa = (paddr_t)__kernel_kudata_phys; 434 while (va < (vaddr_t)__kudata_end) { 435 pmap_enter_special(va, pa, PROT_READ | PROT_WRITE, 0); 436 DPRINTF("%s: entered kudata page va 0x%08lx pa 0x%08lx\n", 437 __func__, (unsigned long)va, (unsigned long)pa); 438 va += PAGE_SIZE; 439 pa += PAGE_SIZE; 440 } 441 } 442 443 /* 444 * Set up proc0's TSS 445 */ 446 void 447 i386_proc0_tss_init(void) 448 { 449 struct pcb *pcb; 450 451 curpcb = pcb = &proc0.p_addr->u_pcb; 452 pcb->pcb_cr0 = rcr0(); 453 pcb->pcb_kstack = (int)proc0.p_addr + USPACE - 16; 454 proc0.p_md.md_regs = (struct trapframe *)pcb->pcb_kstack - 1; 455 } 456 457 #ifdef MULTIPROCESSOR 458 void 459 i386_init_pcb_tss(struct cpu_info *ci) 460 { 461 struct pcb *pcb = ci->ci_idle_pcb; 462 463 pcb->pcb_cr0 = rcr0(); 464 } 465 #endif /* MULTIPROCESSOR */ 466 467 /* 468 * Info for CTL_HW 469 */ 470 char cpu_model[120]; 471 472 const char *classnames[] = { 473 "", 474 "486", 475 "586", 476 "686" 477 }; 478 479 const char *modifiers[] = { 480 "", 481 "OverDrive ", 482 "Dual ", 483 "" 484 }; 485 486 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 487 { 488 "GenuineIntel", 489 CPUVENDOR_INTEL, 490 "Intel", 491 /* Family 4 */ 492 { { 493 CPUCLASS_486, 494 { 495 "486DX", "486DX", "486SX", "486DX2", "486SL", 496 "486SX2", 0, "486DX2 W/B", 497 "486DX4", 0, 0, 0, 0, 0, 0, 0, 498 "486" /* Default */ 499 }, 500 NULL 501 }, 502 /* Family 5 */ 503 { 504 CPUCLASS_586, 505 { 506 "Pentium (A-step)", "Pentium (P5)", 507 "Pentium (P54C)", "Pentium (P24T)", 508 "Pentium/MMX", "Pentium", 0, 509 "Pentium (P54C)", "Pentium/MMX", 510 0, 0, 0, 0, 0, 0, 0, 511 "Pentium" /* Default */ 512 }, 513 intel586_cpu_setup 514 }, 515 /* Family 6 */ 516 { 517 CPUCLASS_686, 518 { 519 "Pentium Pro", "Pentium Pro", 0, 520 "Pentium II", "Pentium Pro", 521 "Pentium II/Celeron", 522 "Celeron", 523 "Pentium III", 524 "Pentium III", 525 "Pentium M", 526 "Pentium III Xeon", 527 "Pentium III", 0, 528 "Pentium M", 529 "Core Duo/Solo", 0, 530 "Pentium Pro, II or III" /* Default */ 531 }, 532 intel686_cpu_setup 533 }, 534 /* Family 7 */ 535 { 536 CPUCLASS_686, 537 } , 538 /* Family 8 */ 539 { 540 CPUCLASS_686, 541 } , 542 /* Family 9 */ 543 { 544 CPUCLASS_686, 545 } , 546 /* Family A */ 547 { 548 CPUCLASS_686, 549 } , 550 /* Family B */ 551 { 552 CPUCLASS_686, 553 } , 554 /* Family C */ 555 { 556 CPUCLASS_686, 557 } , 558 /* Family D */ 559 { 560 CPUCLASS_686, 561 } , 562 /* Family E */ 563 { 564 CPUCLASS_686, 565 } , 566 /* Family F */ 567 { 568 CPUCLASS_686, 569 { 570 "Pentium 4", 0, 0, 0, 571 0, 0, 0, 0, 572 0, 0, 0, 0, 573 0, 0, 0, 0, 574 "Pentium 4" /* Default */ 575 }, 576 intel686_p4_cpu_setup 577 } } 578 }, 579 { 580 "AuthenticAMD", 581 CPUVENDOR_AMD, 582 "AMD", 583 /* Family 4 */ 584 { { 585 CPUCLASS_486, 586 { 587 0, 0, 0, "Am486DX2 W/T", 588 0, 0, 0, "Am486DX2 W/B", 589 "Am486DX4 W/T or Am5x86 W/T 150", 590 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 591 0, 0, "Am5x86 W/T 133/160", 592 "Am5x86 W/B 133/160", 593 "Am486 or Am5x86" /* Default */ 594 }, 595 NULL 596 }, 597 /* Family 5 */ 598 { 599 CPUCLASS_586, 600 { 601 "K5", "K5", "K5", "K5", 0, 0, "K6", 602 "K6", "K6-2", "K6-III", 0, 0, 0, 603 "K6-2+/III+", 0, 0, 604 "K5 or K6" /* Default */ 605 }, 606 amd_family5_setup 607 }, 608 /* Family 6 */ 609 { 610 CPUCLASS_686, 611 { 612 0, "Athlon Model 1", "Athlon Model 2", 613 "Duron Model 3", 614 "Athlon Model 4", 615 0, "Athlon XP Model 6", 616 "Duron Model 7", 617 "Athlon XP Model 8", 618 0, "Athlon XP Model 10", 619 0, 0, 0, 0, 0, 620 "K7" /* Default */ 621 }, 622 amd_family6_setup 623 }, 624 /* Family 7 */ 625 { 626 CPUCLASS_686, 627 } , 628 /* Family 8 */ 629 { 630 CPUCLASS_686, 631 } , 632 /* Family 9 */ 633 { 634 CPUCLASS_686, 635 } , 636 /* Family A */ 637 { 638 CPUCLASS_686, 639 } , 640 /* Family B */ 641 { 642 CPUCLASS_686, 643 } , 644 /* Family C */ 645 { 646 CPUCLASS_686, 647 } , 648 /* Family D */ 649 { 650 CPUCLASS_686, 651 } , 652 /* Family E */ 653 { 654 CPUCLASS_686, 655 } , 656 /* Family F */ 657 { 658 CPUCLASS_686, 659 { 660 0, 0, 0, 0, "Athlon64", 661 "Opteron or Athlon64FX", 0, 0, 662 0, 0, 0, 0, 0, 0, 0, 0, 663 "AMD64" /* DEFAULT */ 664 }, 665 amd_family6_setup 666 } } 667 }, 668 { 669 "CyrixInstead", 670 CPUVENDOR_CYRIX, 671 "Cyrix", 672 /* Family 4 */ 673 { { 674 CPUCLASS_486, 675 { 676 0, 0, 0, "MediaGX", 0, 0, 0, 0, "5x86", 0, 0, 677 0, 0, 0, 0, 678 "486 class" /* Default */ 679 }, 680 NULL 681 }, 682 /* Family 5 */ 683 { 684 CPUCLASS_586, 685 { 686 0, 0, "6x86", 0, "GXm", 0, 0, 0, 0, 0, 687 0, 0, 0, 0, 0, 0, 688 "586 class" /* Default */ 689 }, 690 cyrix6x86_cpu_setup 691 }, 692 /* Family 6 */ 693 { 694 CPUCLASS_686, 695 { 696 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 697 0, 0, 0, 0, 698 "686 class" /* Default */ 699 }, 700 NULL 701 } } 702 }, 703 { 704 "CentaurHauls", 705 CPUVENDOR_IDT, 706 "IDT", 707 /* Family 4, not available from IDT */ 708 { { 709 CPUCLASS_486, 710 { 711 0, 0, 0, 0, 0, 0, 0, 0, 712 0, 0, 0, 0, 0, 0, 0, 0, 713 "486 class" /* Default */ 714 }, 715 NULL 716 }, 717 /* Family 5 */ 718 { 719 CPUCLASS_586, 720 { 721 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 722 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 723 "WinChip" /* Default */ 724 }, 725 winchip_cpu_setup 726 }, 727 /* Family 6 */ 728 { 729 CPUCLASS_686, 730 { 731 0, 0, 0, 0, 0, 0, 732 "C3 Samuel", 733 "C3 Samuel 2/Ezra", 734 "C3 Ezra-T", 735 "C3 Nehemiah", "C3 Esther", 0, 0, 0, 0, 0, 736 "C3" /* Default */ 737 }, 738 cyrix3_cpu_setup 739 } } 740 }, 741 { 742 "GenuineTMx86", 743 CPUVENDOR_TRANSMETA, 744 "Transmeta", 745 /* Family 4, not available from Transmeta */ 746 { { 747 CPUCLASS_486, 748 { 749 0, 0, 0, 0, 0, 0, 0, 0, 750 0, 0, 0, 0, 0, 0, 0, 0, 751 "486 class" /* Default */ 752 }, 753 NULL 754 }, 755 /* Family 5 */ 756 { 757 CPUCLASS_586, 758 { 759 0, 0, 0, 0, "TMS5x00", 0, 0, 760 0, 0, 0, 0, 0, 0, 0, 0, 0, 761 "TMS5x00" /* Default */ 762 }, 763 tm86_cpu_setup 764 }, 765 /* Family 6, not yet available from Transmeta */ 766 { 767 CPUCLASS_686, 768 { 769 0, 0, 0, 0, 0, 0, 0, 0, 770 0, 0, 0, 0, 0, 0, 0, 0, 771 "686 class" /* Default */ 772 }, 773 NULL 774 }, 775 /* Family 7 */ 776 { 777 CPUCLASS_686, 778 } , 779 /* Family 8 */ 780 { 781 CPUCLASS_686, 782 } , 783 /* Family 9 */ 784 { 785 CPUCLASS_686, 786 } , 787 /* Family A */ 788 { 789 CPUCLASS_686, 790 } , 791 /* Family B */ 792 { 793 CPUCLASS_686, 794 } , 795 /* Family C */ 796 { 797 CPUCLASS_686, 798 } , 799 /* Family D */ 800 { 801 CPUCLASS_686, 802 } , 803 /* Family E */ 804 { 805 CPUCLASS_686, 806 } , 807 /* Family F */ 808 { 809 /* Extended processor family - Transmeta Efficeon */ 810 CPUCLASS_686, 811 { 812 0, 0, "TM8000", "TM8000", 813 0, 0, 0, 0, 814 0, 0, 0, 0, 815 0, 0, 0, 0, 816 "TM8000" /* Default */ 817 }, 818 tm86_cpu_setup 819 } } 820 }, 821 { 822 "Geode by NSC", 823 CPUVENDOR_NS, 824 "National Semiconductor", 825 /* Family 4, not available from National Semiconductor */ 826 { { 827 CPUCLASS_486, 828 { 829 0, 0, 0, 0, 0, 0, 0, 0, 830 0, 0, 0, 0, 0, 0, 0, 0, 831 "486 class" /* Default */ 832 }, 833 NULL 834 }, 835 /* Family 5 */ 836 { 837 CPUCLASS_586, 838 { 839 0, 0, 0, 0, "Geode GX1", 0, 0, 0, 0, 0, 840 0, 0, 0, 0, 0, 0, 841 "586 class" /* Default */ 842 }, 843 natsem6x86_cpu_setup 844 } } 845 }, 846 { 847 "SiS SiS SiS ", 848 CPUVENDOR_SIS, 849 "SiS", 850 /* Family 4, not available from SiS */ 851 { { 852 CPUCLASS_486, 853 { 854 0, 0, 0, 0, 0, 0, 0, 0, 855 0, 0, 0, 0, 0, 0, 0, 0, 856 "486 class" /* Default */ 857 }, 858 NULL 859 }, 860 /* Family 5 */ 861 { 862 CPUCLASS_586, 863 { 864 "SiS55x", 0, 0, 0, 0, 0, 0, 0, 0, 0, 865 0, 0, 0, 0, 0, 0, 866 "586 class" /* Default */ 867 }, 868 NULL 869 } } 870 } 871 }; 872 873 const struct cpu_cpuid_feature i386_cpuid_features[] = { 874 { CPUID_FPU, "FPU" }, 875 { CPUID_VME, "V86" }, 876 { CPUID_DE, "DE" }, 877 { CPUID_PSE, "PSE" }, 878 { CPUID_TSC, "TSC" }, 879 { CPUID_MSR, "MSR" }, 880 { CPUID_PAE, "PAE" }, 881 { CPUID_MCE, "MCE" }, 882 { CPUID_CX8, "CX8" }, 883 { CPUID_APIC, "APIC" }, 884 { CPUID_SYS1, "SYS" }, 885 { CPUID_SEP, "SEP" }, 886 { CPUID_MTRR, "MTRR" }, 887 { CPUID_PGE, "PGE" }, 888 { CPUID_MCA, "MCA" }, 889 { CPUID_CMOV, "CMOV" }, 890 { CPUID_PAT, "PAT" }, 891 { CPUID_PSE36, "PSE36" }, 892 { CPUID_PSN, "PSN" }, 893 { CPUID_CFLUSH, "CFLUSH" }, 894 { CPUID_DS, "DS" }, 895 { CPUID_ACPI, "ACPI" }, 896 { CPUID_MMX, "MMX" }, 897 { CPUID_FXSR, "FXSR" }, 898 { CPUID_SSE, "SSE" }, 899 { CPUID_SSE2, "SSE2" }, 900 { CPUID_SS, "SS" }, 901 { CPUID_HTT, "HTT" }, 902 { CPUID_TM, "TM" }, 903 { CPUID_PBE, "PBE" } 904 }; 905 906 const struct cpu_cpuid_feature i386_ecpuid_features[] = { 907 { CPUID_MPC, "MPC" }, 908 { CPUID_NXE, "NXE" }, 909 { CPUID_MMXX, "MMXX" }, 910 { CPUID_FFXSR, "FFXSR" }, 911 { CPUID_PAGE1GB, "PAGE1GB" }, 912 { CPUID_RDTSCP, "RDTSCP" }, 913 { CPUID_LONG, "LONG" }, 914 { CPUID_3DNOW2, "3DNOW2" }, 915 { CPUID_3DNOW, "3DNOW" } 916 }; 917 918 const struct cpu_cpuid_feature i386_cpuid_ecxfeatures[] = { 919 { CPUIDECX_SSE3, "SSE3" }, 920 { CPUIDECX_PCLMUL, "PCLMUL" }, 921 { CPUIDECX_DTES64, "DTES64" }, 922 { CPUIDECX_MWAIT, "MWAIT" }, 923 { CPUIDECX_DSCPL, "DS-CPL" }, 924 { CPUIDECX_VMX, "VMX" }, 925 { CPUIDECX_SMX, "SMX" }, 926 { CPUIDECX_EST, "EST" }, 927 { CPUIDECX_TM2, "TM2" }, 928 { CPUIDECX_SSSE3, "SSSE3" }, 929 { CPUIDECX_CNXTID, "CNXT-ID" }, 930 { CPUIDECX_SDBG, "SDBG" }, 931 { CPUIDECX_FMA3, "FMA3" }, 932 { CPUIDECX_CX16, "CX16" }, 933 { CPUIDECX_XTPR, "xTPR" }, 934 { CPUIDECX_PDCM, "PDCM" }, 935 { CPUIDECX_PCID, "PCID" }, 936 { CPUIDECX_DCA, "DCA" }, 937 { CPUIDECX_SSE41, "SSE4.1" }, 938 { CPUIDECX_SSE42, "SSE4.2" }, 939 { CPUIDECX_X2APIC, "x2APIC" }, 940 { CPUIDECX_MOVBE, "MOVBE" }, 941 { CPUIDECX_POPCNT, "POPCNT" }, 942 { CPUIDECX_DEADLINE, "DEADLINE" }, 943 { CPUIDECX_AES, "AES" }, 944 { CPUIDECX_XSAVE, "XSAVE" }, 945 { CPUIDECX_OSXSAVE, "OSXSAVE" }, 946 { CPUIDECX_AVX, "AVX" }, 947 { CPUIDECX_F16C, "F16C" }, 948 { CPUIDECX_RDRAND, "RDRAND" }, 949 { CPUIDECX_HV, "HV" }, 950 }; 951 952 const struct cpu_cpuid_feature i386_ecpuid_ecxfeatures[] = { 953 { CPUIDECX_LAHF, "LAHF" }, 954 { CPUIDECX_CMPLEG, "CMPLEG" }, 955 { CPUIDECX_SVM, "SVM" }, 956 { CPUIDECX_EAPICSP, "EAPICSP" }, 957 { CPUIDECX_AMCR8, "AMCR8" }, 958 { CPUIDECX_ABM, "ABM" }, 959 { CPUIDECX_SSE4A, "SSE4A" }, 960 { CPUIDECX_MASSE, "MASSE" }, 961 { CPUIDECX_3DNOWP, "3DNOWP" }, 962 { CPUIDECX_OSVW, "OSVW" }, 963 { CPUIDECX_IBS, "IBS" }, 964 { CPUIDECX_XOP, "XOP" }, 965 { CPUIDECX_SKINIT, "SKINIT" }, 966 { CPUIDECX_WDT, "WDT" }, 967 { CPUIDECX_LWP, "LWP" }, 968 { CPUIDECX_FMA4, "FMA4" }, 969 { CPUIDECX_TCE, "TCE" }, 970 { CPUIDECX_NODEID, "NODEID" }, 971 { CPUIDECX_TBM, "TBM" }, 972 { CPUIDECX_TOPEXT, "TOPEXT" }, 973 { CPUIDECX_CPCTR, "CPCTR" }, 974 { CPUIDECX_DBKP, "DBKP" }, 975 { CPUIDECX_PERFTSC, "PERFTSC" }, 976 { CPUIDECX_PCTRL3, "PCTRL3" }, 977 { CPUIDECX_MWAITX, "MWAITX" }, 978 }; 979 980 const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = { 981 { SEFF0EBX_FSGSBASE, "FSGSBASE" }, 982 { SEFF0EBX_TSC_ADJUST, "TSC_ADJUST" }, 983 { SEFF0EBX_SGX, "SGX" }, 984 { SEFF0EBX_BMI1, "BMI1" }, 985 { SEFF0EBX_HLE, "HLE" }, 986 { SEFF0EBX_AVX2, "AVX2" }, 987 { SEFF0EBX_SMEP, "SMEP" }, 988 { SEFF0EBX_BMI2, "BMI2" }, 989 { SEFF0EBX_ERMS, "ERMS" }, 990 { SEFF0EBX_INVPCID, "INVPCID" }, 991 { SEFF0EBX_RTM, "RTM" }, 992 { SEFF0EBX_PQM, "PQM" }, 993 { SEFF0EBX_MPX, "MPX" }, 994 { SEFF0EBX_AVX512F, "AVX512F" }, 995 { SEFF0EBX_AVX512DQ, "AVX512DQ" }, 996 { SEFF0EBX_RDSEED, "RDSEED" }, 997 { SEFF0EBX_ADX, "ADX" }, 998 { SEFF0EBX_SMAP, "SMAP" }, 999 { SEFF0EBX_AVX512IFMA, "AVX512IFMA" }, 1000 { SEFF0EBX_PCOMMIT, "PCOMMIT" }, 1001 { SEFF0EBX_CLFLUSHOPT, "CLFLUSHOPT" }, 1002 { SEFF0EBX_CLWB, "CLWB" }, 1003 { SEFF0EBX_PT, "PT" }, 1004 { SEFF0EBX_AVX512PF, "AVX512PF" }, 1005 { SEFF0EBX_AVX512ER, "AVX512ER" }, 1006 { SEFF0EBX_AVX512CD, "AVX512CD" }, 1007 { SEFF0EBX_SHA, "SHA" }, 1008 { SEFF0EBX_AVX512BW, "AVX512BW" }, 1009 { SEFF0EBX_AVX512VL, "AVX512VL" }, 1010 }; 1011 1012 const struct cpu_cpuid_feature cpu_seff0_ecxfeatures[] = { 1013 { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" }, 1014 { SEFF0ECX_UMIP, "UMIP" }, 1015 { SEFF0ECX_AVX512VBMI, "AVX512VBMI" }, 1016 { SEFF0ECX_PKU, "PKU" }, 1017 { SEFF0ECX_WAITPKG, "WAITPKG" }, 1018 }; 1019 1020 const struct cpu_cpuid_feature cpu_seff0_edxfeatures[] = { 1021 { SEFF0EDX_AVX512_4FNNIW, "AVX512FNNIW" }, 1022 { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" }, 1023 { SEFF0EDX_SRBDS_CTRL, "SRBDS_CTRL" }, 1024 { SEFF0EDX_MD_CLEAR, "MD_CLEAR" }, 1025 { SEFF0EDX_TSXFA, "TSXFA" }, 1026 { SEFF0EDX_IBRS, "IBRS,IBPB" }, 1027 { SEFF0EDX_STIBP, "STIBP" }, 1028 { SEFF0EDX_L1DF, "L1DF" }, 1029 /* SEFF0EDX_ARCH_CAP (not printed) */ 1030 { SEFF0EDX_SSBD, "SSBD" }, 1031 }; 1032 1033 const struct cpu_cpuid_feature cpu_tpm_eaxfeatures[] = { 1034 { TPM_SENSOR, "SENSOR" }, 1035 { TPM_ARAT, "ARAT" }, 1036 }; 1037 1038 const struct cpu_cpuid_feature i386_cpuid_eaxperf[] = { 1039 { CPUIDEAX_VERID, "PERF" }, 1040 }; 1041 1042 const struct cpu_cpuid_feature i386_cpuid_edxapmi[] = { 1043 { CPUIDEDX_ITSC, "ITSC" }, 1044 }; 1045 1046 const struct cpu_cpuid_feature cpu_xsave_extfeatures[] = { 1047 { XSAVE_XSAVEOPT, "XSAVEOPT" }, 1048 { XSAVE_XSAVEC, "XSAVEC" }, 1049 { XSAVE_XGETBV1, "XGETBV1" }, 1050 { XSAVE_XSAVES, "XSAVES" }, 1051 }; 1052 1053 void 1054 winchip_cpu_setup(struct cpu_info *ci) 1055 { 1056 1057 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1058 case 4: /* WinChip C6 */ 1059 ci->ci_feature_flags &= ~CPUID_TSC; 1060 /* Disable RDTSC instruction from user-level. */ 1061 lcr4(rcr4() | CR4_TSD); 1062 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1063 break; 1064 } 1065 } 1066 1067 #if !defined(SMALL_KERNEL) 1068 void 1069 cyrix3_setperf_setup(struct cpu_info *ci) 1070 { 1071 if (cpu_ecxfeature & CPUIDECX_EST) { 1072 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1073 est_init(ci, CPUVENDOR_VIA); 1074 else 1075 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1076 ci->ci_dev->dv_xname); 1077 } 1078 } 1079 #endif 1080 1081 void 1082 cyrix3_cpu_setup(struct cpu_info *ci) 1083 { 1084 int model = (ci->ci_signature >> 4) & 15; 1085 int step = ci->ci_signature & 15; 1086 1087 u_int64_t msreg; 1088 u_int32_t regs[4]; 1089 unsigned int val; 1090 #if !defined(SMALL_KERNEL) 1091 extern void (*pagezero)(void *, size_t); 1092 extern void i686_pagezero(void *, size_t); 1093 1094 pagezero = i686_pagezero; 1095 1096 setperf_setup = cyrix3_setperf_setup; 1097 #endif 1098 1099 switch (model) { 1100 /* Possible earlier models */ 1101 case 0: case 1: case 2: 1102 case 3: case 4: case 5: 1103 break; 1104 1105 case 6: /* C3 Samuel 1 */ 1106 case 7: /* C3 Samuel 2 or C3 Ezra */ 1107 case 8: /* C3 Ezra-T */ 1108 cpuid(0x80000001, regs); 1109 val = regs[3]; 1110 if (val & (1U << 31)) { 1111 cpu_feature |= CPUID_3DNOW; 1112 } else { 1113 cpu_feature &= ~CPUID_3DNOW; 1114 } 1115 break; 1116 1117 case 9: 1118 if (step < 3) 1119 break; 1120 /* 1121 * C3 Nehemiah & later: fall through. 1122 */ 1123 1124 case 10: /* C7-M Type A */ 1125 case 13: /* C7-M Type D */ 1126 case 15: /* Nano */ 1127 #if !defined(SMALL_KERNEL) 1128 if (CPU_IS_PRIMARY(ci) && 1129 (model == 10 || model == 13 || model == 15)) { 1130 /* Setup the sensors structures */ 1131 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 1132 sizeof(ci->ci_sensordev.xname)); 1133 ci->ci_sensor.type = SENSOR_TEMP; 1134 sensor_task_register(ci, via_update_sensor, 5); 1135 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1136 sensordev_install(&ci->ci_sensordev); 1137 } 1138 #endif 1139 1140 default: 1141 /* 1142 * C3 Nehemiah/Esther & later models: 1143 * First we check for extended feature flags, and then 1144 * (if present) retrieve the ones at 0xC0000001. In this 1145 * bit 2 tells us if the RNG is present. Bit 3 tells us 1146 * if the RNG has been enabled. In order to use the RNG 1147 * we need 3 things: We need an RNG, we need the FXSR bit 1148 * enabled in cr4 (SSE/SSE2 stuff), and we need to have 1149 * Bit 6 of MSR 0x110B set to 1 (the default), which will 1150 * show up as bit 3 set here. 1151 */ 1152 cpuid(0xC0000000, regs); /* Check for RNG */ 1153 val = regs[0]; 1154 if (val >= 0xC0000001) { 1155 cpuid(0xC0000001, regs); 1156 val = regs[3]; 1157 } else 1158 val = 0; 1159 1160 if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE)) 1161 printf("%s:", ci->ci_dev->dv_xname); 1162 1163 /* Enable RNG if present and disabled */ 1164 if (val & C3_CPUID_HAS_RNG) { 1165 extern int viac3_rnd_present; 1166 1167 if (!(val & C3_CPUID_DO_RNG)) { 1168 msreg = rdmsr(0x110B); 1169 msreg |= 0x40; 1170 wrmsr(0x110B, msreg); 1171 } 1172 viac3_rnd_present = 1; 1173 printf(" RNG"); 1174 } 1175 1176 /* Enable AES engine if present and disabled */ 1177 if (val & C3_CPUID_HAS_ACE) { 1178 #ifdef CRYPTO 1179 if (!(val & C3_CPUID_DO_ACE)) { 1180 msreg = rdmsr(0x1107); 1181 msreg |= (0x01 << 28); 1182 wrmsr(0x1107, msreg); 1183 } 1184 i386_has_xcrypt |= C3_HAS_AES; 1185 #endif /* CRYPTO */ 1186 printf(" AES"); 1187 } 1188 1189 /* Enable ACE2 engine if present and disabled */ 1190 if (val & C3_CPUID_HAS_ACE2) { 1191 #ifdef CRYPTO 1192 if (!(val & C3_CPUID_DO_ACE2)) { 1193 msreg = rdmsr(0x1107); 1194 msreg |= (0x01 << 28); 1195 wrmsr(0x1107, msreg); 1196 } 1197 i386_has_xcrypt |= C3_HAS_AESCTR; 1198 #endif /* CRYPTO */ 1199 printf(" AES-CTR"); 1200 } 1201 1202 /* Enable SHA engine if present and disabled */ 1203 if (val & C3_CPUID_HAS_PHE) { 1204 #ifdef CRYPTO 1205 if (!(val & C3_CPUID_DO_PHE)) { 1206 msreg = rdmsr(0x1107); 1207 msreg |= (0x01 << 28/**/); 1208 wrmsr(0x1107, msreg); 1209 } 1210 i386_has_xcrypt |= C3_HAS_SHA; 1211 #endif /* CRYPTO */ 1212 printf(" SHA1 SHA256"); 1213 } 1214 1215 /* Enable MM engine if present and disabled */ 1216 if (val & C3_CPUID_HAS_PMM) { 1217 #ifdef CRYPTO 1218 if (!(val & C3_CPUID_DO_PMM)) { 1219 msreg = rdmsr(0x1107); 1220 msreg |= (0x01 << 28/**/); 1221 wrmsr(0x1107, msreg); 1222 } 1223 i386_has_xcrypt |= C3_HAS_MM; 1224 #endif /* CRYPTO */ 1225 printf(" RSA"); 1226 } 1227 1228 printf("\n"); 1229 break; 1230 } 1231 } 1232 1233 #if !defined(SMALL_KERNEL) 1234 void 1235 via_update_sensor(void *args) 1236 { 1237 struct cpu_info *ci = (struct cpu_info *) args; 1238 u_int64_t msr; 1239 1240 switch (ci->ci_model) { 1241 case 0xa: 1242 case 0xd: 1243 msr = rdmsr(MSR_C7M_TMTEMPERATURE); 1244 break; 1245 case 0xf: 1246 msr = rdmsr(MSR_CENT_TMTEMPERATURE); 1247 break; 1248 } 1249 ci->ci_sensor.value = (msr & 0xffffff); 1250 /* micro degrees */ 1251 ci->ci_sensor.value *= 1000000; 1252 ci->ci_sensor.value += 273150000; 1253 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1254 } 1255 #endif 1256 1257 void 1258 cyrix6x86_cpu_setup(struct cpu_info *ci) 1259 { 1260 extern int clock_broken_latch; 1261 1262 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1263 case -1: /* M1 w/o cpuid */ 1264 case 2: /* M1 */ 1265 /* set up various cyrix registers */ 1266 /* Enable suspend on halt */ 1267 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 1268 /* enable access to ccr4/ccr5 */ 1269 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) | 0x10); 1270 /* cyrix's workaround for the "coma bug" */ 1271 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 1272 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 1273 cyrix_read_reg(0x33); cyrix_write_reg(0x33, 0); 1274 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 1275 /* disable access to ccr4/ccr5 */ 1276 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) & ~0x10); 1277 1278 printf("%s: xchg bug workaround performed\n", 1279 ci->ci_dev->dv_xname); 1280 break; /* fallthrough? */ 1281 case 4: /* GXm */ 1282 /* Unset the TSC bit until calibrate_delay() gets fixed. */ 1283 clock_broken_latch = 1; 1284 curcpu()->ci_feature_flags &= ~CPUID_TSC; 1285 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1286 break; 1287 } 1288 } 1289 1290 void 1291 natsem6x86_cpu_setup(struct cpu_info *ci) 1292 { 1293 extern int clock_broken_latch; 1294 int model = (ci->ci_signature >> 4) & 15; 1295 1296 clock_broken_latch = 1; 1297 switch (model) { 1298 case 4: 1299 cpu_feature &= ~CPUID_TSC; 1300 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1301 break; 1302 } 1303 } 1304 1305 void 1306 intel586_cpu_setup(struct cpu_info *ci) 1307 { 1308 if (!cpu_f00f_bug) { 1309 fix_f00f(); 1310 printf("%s: F00F bug workaround installed\n", 1311 ci->ci_dev->dv_xname); 1312 } 1313 } 1314 1315 #if !defined(SMALL_KERNEL) 1316 void 1317 amd_family5_setperf_setup(struct cpu_info *ci) 1318 { 1319 k6_powernow_init(); 1320 } 1321 #endif 1322 1323 void 1324 amd_family5_setup(struct cpu_info *ci) 1325 { 1326 int model = (ci->ci_signature >> 4) & 15; 1327 1328 switch (model) { 1329 case 0: /* AMD-K5 Model 0 */ 1330 /* 1331 * According to the AMD Processor Recognition App Note, 1332 * the AMD-K5 Model 0 uses the wrong bit to indicate 1333 * support for global PTEs, instead using bit 9 (APIC) 1334 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1335 */ 1336 if (cpu_feature & CPUID_APIC) 1337 cpu_feature = (cpu_feature & ~CPUID_APIC) | CPUID_PGE; 1338 /* 1339 * XXX But pmap_pg_g is already initialized -- need to kick 1340 * XXX the pmap somehow. How does the MP branch do this? 1341 */ 1342 break; 1343 case 12: 1344 case 13: 1345 #if !defined(SMALL_KERNEL) 1346 setperf_setup = amd_family5_setperf_setup; 1347 #endif 1348 break; 1349 } 1350 } 1351 1352 #if !defined(SMALL_KERNEL) 1353 void 1354 amd_family6_setperf_setup(struct cpu_info *ci) 1355 { 1356 int family = (ci->ci_signature >> 8) & 15; 1357 1358 switch (family) { 1359 case 6: 1360 k7_powernow_init(); 1361 break; 1362 case 15: 1363 k8_powernow_init(); 1364 break; 1365 } 1366 if (ci->ci_family >= 0x10) 1367 k1x_init(ci); 1368 } 1369 #endif 1370 1371 void 1372 amd_family6_setup(struct cpu_info *ci) 1373 { 1374 #if !defined(SMALL_KERNEL) 1375 int family = (ci->ci_signature >> 8) & 15; 1376 extern void (*pagezero)(void *, size_t); 1377 extern void sse2_pagezero(void *, size_t); 1378 extern void i686_pagezero(void *, size_t); 1379 1380 if (cpu_feature & CPUID_SSE2) 1381 pagezero = sse2_pagezero; 1382 else 1383 pagezero = i686_pagezero; 1384 1385 setperf_setup = amd_family6_setperf_setup; 1386 1387 if (family == 0xf) { 1388 amd64_errata(ci); 1389 } 1390 #endif 1391 } 1392 1393 #if !defined(SMALL_KERNEL) 1394 /* 1395 * Temperature read on the CPU is relative to the maximum 1396 * temperature supported by the CPU, Tj(Max). 1397 * Refer to: 1398 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual.pdf 1399 * Section 35 and 1400 * http://www.intel.com/content/dam/www/public/us/en/documents/ 1401 * white-papers/cpu-monitoring-dts-peci-paper.pdf 1402 * 1403 * The temperature on Intel CPUs can be between 70 and 105 degC, since 1404 * Westmere we can read the TJmax from the die. For older CPUs we have 1405 * to guess or use undocumented MSRs. Then we subtract the temperature 1406 * portion of thermal status from max to get current temperature. 1407 */ 1408 void 1409 intelcore_update_sensor(void *args) 1410 { 1411 struct cpu_info *ci = (struct cpu_info *) args; 1412 u_int64_t msr; 1413 int max = 100; 1414 1415 /* Only some Core family chips have MSR_TEMPERATURE_TARGET. */ 1416 if (ci->ci_model == 0x0e && 1417 (rdmsr(MSR_TEMPERATURE_TARGET_UNDOCUMENTED) & 1418 MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED)) 1419 max = 85; 1420 1421 /* 1422 * Newer CPUs can tell you what their max temperature is. 1423 * See: '64-ia-32-architectures-software-developer- 1424 * vol-3c-part-3-manual.pdf' 1425 */ 1426 if (ci->ci_model > 0x17 && ci->ci_model != 0x1c && 1427 ci->ci_model != 0x26 && ci->ci_model != 0x27 && 1428 ci->ci_model != 0x35 && ci->ci_model != 0x36) 1429 max = MSR_TEMPERATURE_TARGET_TJMAX( 1430 rdmsr(MSR_TEMPERATURE_TARGET)); 1431 1432 msr = rdmsr(MSR_THERM_STATUS); 1433 if (msr & MSR_THERM_STATUS_VALID_BIT) { 1434 ci->ci_sensor.value = max - MSR_THERM_STATUS_TEMP(msr); 1435 /* micro degrees */ 1436 ci->ci_sensor.value *= 1000000; 1437 /* kelvin */ 1438 ci->ci_sensor.value += 273150000; 1439 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1440 } else { 1441 ci->ci_sensor.value = 0; 1442 ci->ci_sensor.flags |= SENSOR_FINVALID; 1443 } 1444 } 1445 1446 void 1447 intel686_cpusensors_setup(struct cpu_info *ci) 1448 { 1449 if (!CPU_IS_PRIMARY(ci) || (ci->ci_feature_tpmflags & TPM_SENSOR) == 0) 1450 return; 1451 1452 /* Setup the sensors structures */ 1453 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 1454 sizeof(ci->ci_sensordev.xname)); 1455 ci->ci_sensor.type = SENSOR_TEMP; 1456 sensor_task_register(ci, intelcore_update_sensor, 5); 1457 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1458 sensordev_install(&ci->ci_sensordev); 1459 } 1460 #endif 1461 1462 #if !defined(SMALL_KERNEL) 1463 void 1464 intel686_setperf_setup(struct cpu_info *ci) 1465 { 1466 int family = (ci->ci_signature >> 8) & 15; 1467 int step = ci->ci_signature & 15; 1468 1469 if (cpu_ecxfeature & CPUIDECX_EST) { 1470 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1471 est_init(ci, CPUVENDOR_INTEL); 1472 else 1473 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1474 ci->ci_dev->dv_xname); 1475 } else if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) == 1476 (CPUID_ACPI | CPUID_TM)) 1477 p4tcc_init(family, step); 1478 } 1479 #endif 1480 1481 void 1482 intel686_common_cpu_setup(struct cpu_info *ci) 1483 { 1484 1485 #if !defined(SMALL_KERNEL) 1486 setperf_setup = intel686_setperf_setup; 1487 cpusensors_setup = intel686_cpusensors_setup; 1488 { 1489 extern void (*pagezero)(void *, size_t); 1490 extern void sse2_pagezero(void *, size_t); 1491 extern void i686_pagezero(void *, size_t); 1492 1493 if (cpu_feature & CPUID_SSE2) 1494 pagezero = sse2_pagezero; 1495 else 1496 pagezero = i686_pagezero; 1497 } 1498 #endif 1499 /* 1500 * Make sure SYSENTER is disabled. 1501 */ 1502 if (cpu_feature & CPUID_SEP) 1503 wrmsr(MSR_SYSENTER_CS, 0); 1504 } 1505 1506 void 1507 intel686_cpu_setup(struct cpu_info *ci) 1508 { 1509 int model = (ci->ci_signature >> 4) & 15; 1510 int step = ci->ci_signature & 15; 1511 u_quad_t msr119; 1512 1513 intel686_common_cpu_setup(ci); 1514 1515 /* 1516 * Original PPro returns SYSCALL in CPUID but is non-functional. 1517 * From Intel Application Note #485. 1518 */ 1519 if ((model == 1) && (step < 3)) 1520 ci->ci_feature_flags &= ~CPUID_SEP; 1521 1522 /* 1523 * Disable the Pentium3 serial number. 1524 */ 1525 if ((model == 7) && (ci->ci_feature_flags & CPUID_PSN)) { 1526 msr119 = rdmsr(MSR_BBL_CR_CTL); 1527 msr119 |= 0x0000000000200000LL; 1528 wrmsr(MSR_BBL_CR_CTL, msr119); 1529 1530 printf("%s: disabling processor serial number\n", 1531 ci->ci_dev->dv_xname); 1532 ci->ci_feature_flags &= ~CPUID_PSN; 1533 ci->ci_level = 2; 1534 } 1535 1536 #if !defined(SMALL_KERNEL) 1537 p3_early = (model == 8 && step == 1) ? 1 : 0; 1538 update_cpuspeed = p3_update_cpuspeed; 1539 #endif 1540 } 1541 1542 void 1543 intel686_p4_cpu_setup(struct cpu_info *ci) 1544 { 1545 intel686_common_cpu_setup(ci); 1546 1547 #if !defined(SMALL_KERNEL) 1548 update_cpuspeed = p4_update_cpuspeed; 1549 #endif 1550 } 1551 1552 void 1553 tm86_cpu_setup(struct cpu_info *ci) 1554 { 1555 #if !defined(SMALL_KERNEL) 1556 longrun_init(); 1557 #endif 1558 } 1559 1560 char * 1561 intel686_cpu_name(int model) 1562 { 1563 char *ret = NULL; 1564 1565 switch (model) { 1566 case 5: 1567 switch (cpu_cache_edx & 0xFF) { 1568 case 0x40: 1569 case 0x41: 1570 ret = "Celeron"; 1571 break; 1572 /* 0x42 should not exist in this model. */ 1573 case 0x43: 1574 ret = "Pentium II"; 1575 break; 1576 case 0x44: 1577 case 0x45: 1578 ret = "Pentium II Xeon"; 1579 break; 1580 } 1581 break; 1582 case 7: 1583 switch (cpu_cache_edx & 0xFF) { 1584 /* 0x40 - 0x42 should not exist in this model. */ 1585 case 0x43: 1586 ret = "Pentium III"; 1587 break; 1588 case 0x44: 1589 case 0x45: 1590 ret = "Pentium III Xeon"; 1591 break; 1592 } 1593 break; 1594 } 1595 1596 return (ret); 1597 } 1598 1599 char * 1600 cyrix3_cpu_name(int model, int step) 1601 { 1602 char *name = NULL; 1603 1604 switch (model) { 1605 case 7: 1606 if (step < 8) 1607 name = "C3 Samuel 2"; 1608 else 1609 name = "C3 Ezra"; 1610 break; 1611 } 1612 return name; 1613 } 1614 1615 /* 1616 * Print identification for the given CPU. 1617 * XXX XXX 1618 * This is not as clean as one might like, because it references 1619 * 1620 * the "cpuid_level" and "cpu_vendor" globals. 1621 * cpuid_level isn't so bad, since both CPU's will hopefully 1622 * be of the same level. 1623 * 1624 * The Intel multiprocessor spec doesn't give us the cpu_vendor 1625 * information; however, the chance of multi-vendor SMP actually 1626 * ever *working* is sufficiently low that it's probably safe to assume 1627 * all processors are of the same vendor. 1628 */ 1629 void 1630 identifycpu(struct cpu_info *ci) 1631 { 1632 const char *name, *modifier, *vendorname, *token; 1633 int class = CPUCLASS_486, vendor, i, max; 1634 int family, model, step, modif, cachesize; 1635 const struct cpu_cpuid_nameclass *cpup = NULL; 1636 char *brandstr_from, *brandstr_to; 1637 char *cpu_device = ci->ci_dev->dv_xname; 1638 int skipspace; 1639 extern uint32_t cpu_meltdown; 1640 uint64_t msr, nmsr; 1641 1642 if (cpuid_level == -1) { 1643 name = "486DX"; 1644 vendor = CPUVENDOR_INTEL; 1645 vendorname = "Intel"; 1646 model = -1; 1647 step = -1; 1648 class = CPUCLASS_486; 1649 ci->cpu_setup = NULL; 1650 modifier = ""; 1651 token = ""; 1652 } else { 1653 max = sizeof (i386_cpuid_cpus) / sizeof (i386_cpuid_cpus[0]); 1654 modif = (ci->ci_signature >> 12) & 3; 1655 family = (ci->ci_signature >> 8) & 15; 1656 ci->ci_family = family; 1657 model = (ci->ci_signature >> 4) & 15; 1658 ci->ci_model = model; 1659 step = ci->ci_signature & 15; 1660 #ifdef CPUDEBUG 1661 printf("%s: cpuid level %d cache eax %x ebx %x ecx %x edx %x\n", 1662 cpu_device, cpuid_level, cpu_cache_eax, cpu_cache_ebx, 1663 cpu_cache_ecx, cpu_cache_edx); 1664 #endif 1665 if (family < CPU_MINFAMILY) 1666 panic("identifycpu: strange family value"); 1667 1668 for (i = 0; i < max; i++) { 1669 if (!strncmp(cpu_vendor, 1670 i386_cpuid_cpus[i].cpu_id, 12)) { 1671 cpup = &i386_cpuid_cpus[i]; 1672 break; 1673 } 1674 } 1675 1676 if (cpup == NULL) { 1677 vendor = CPUVENDOR_UNKNOWN; 1678 if (cpu_vendor[0] != '\0') 1679 vendorname = &cpu_vendor[0]; 1680 else 1681 vendorname = "Unknown"; 1682 if (family > CPU_MAXFAMILY) 1683 family = CPU_MAXFAMILY; 1684 class = family - 3; 1685 if (class > CPUCLASS_686) 1686 class = CPUCLASS_686; 1687 modifier = ""; 1688 name = ""; 1689 token = ""; 1690 ci->cpu_setup = NULL; 1691 } else { 1692 token = cpup->cpu_id; 1693 vendor = cpup->cpu_vendor; 1694 vendorname = cpup->cpu_vendorname; 1695 /* 1696 * Special hack for the VIA C3 series. 1697 * 1698 * VIA bought Centaur Technology from IDT in Aug 1999 1699 * and marketed the processors as VIA Cyrix III/C3. 1700 */ 1701 if (vendor == CPUVENDOR_IDT && family >= 6) { 1702 vendor = CPUVENDOR_VIA; 1703 vendorname = "VIA"; 1704 } 1705 modifier = modifiers[modif]; 1706 if (family > CPU_MAXFAMILY) { 1707 family = CPU_MAXFAMILY; 1708 model = CPU_DEFMODEL; 1709 } else if (model > CPU_MAXMODEL) 1710 model = CPU_DEFMODEL; 1711 i = family - CPU_MINFAMILY; 1712 1713 /* store extended family/model values for later use */ 1714 if ((vendor == CPUVENDOR_INTEL && 1715 (family == 0x6 || family == 0xf)) || 1716 (vendor == CPUVENDOR_AMD && family == 0xf)) { 1717 ci->ci_family += (ci->ci_signature >> 20) & 1718 0xff; 1719 ci->ci_model += ((ci->ci_signature >> 16) & 1720 0x0f) << 4; 1721 } 1722 1723 /* Special hack for the PentiumII/III series. */ 1724 if (vendor == CPUVENDOR_INTEL && family == 6 && 1725 (model == 5 || model == 7)) { 1726 name = intel686_cpu_name(model); 1727 /* Special hack for the VIA C3 series. */ 1728 } else if (vendor == CPUVENDOR_VIA && family == 6 && 1729 model == 7) { 1730 name = cyrix3_cpu_name(model, step); 1731 /* Special hack for the TMS5x00 series. */ 1732 } else if (vendor == CPUVENDOR_TRANSMETA && 1733 family == 5 && model == 4) { 1734 name = tm86_cpu_name(model); 1735 } else 1736 name = cpup->cpu_family[i].cpu_models[model]; 1737 if (name == NULL) { 1738 name = cpup->cpu_family[i].cpu_models[CPU_DEFMODEL]; 1739 if (name == NULL) 1740 name = ""; 1741 } 1742 class = cpup->cpu_family[i].cpu_class; 1743 ci->cpu_setup = cpup->cpu_family[i].cpu_setup; 1744 } 1745 } 1746 1747 /* Find the amount of on-chip L2 cache. */ 1748 cachesize = -1; 1749 if (vendor == CPUVENDOR_INTEL && cpuid_level >= 2 && family < 0xf) { 1750 int intel_cachetable[] = { 0, 128, 256, 512, 1024, 2048 }; 1751 1752 if ((cpu_cache_edx & 0xFF) >= 0x40 && 1753 (cpu_cache_edx & 0xFF) <= 0x45) 1754 cachesize = intel_cachetable[(cpu_cache_edx & 0xFF) - 0x40]; 1755 } else if (vendor == CPUVENDOR_AMD && class == CPUCLASS_686) { 1756 u_int regs[4]; 1757 cpuid(0x80000000, regs); 1758 1759 if (regs[0] >= 0x80000006) { 1760 cpuid(0x80000006, regs); 1761 cachesize = (regs[2] >> 16); 1762 } 1763 } 1764 1765 if (ci->ci_feature_flags & CPUID_CFLUSH) { 1766 u_int regs[4]; 1767 1768 /* to get the cacheline size you must do cpuid 1769 * with eax 0x01 1770 */ 1771 1772 cpuid(0x01, regs); 1773 ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8; 1774 } 1775 1776 if (vendor == CPUVENDOR_INTEL) { 1777 /* 1778 * PIII, Core Solo and Core Duo CPUs have known 1779 * errata stating: 1780 * "Page with PAT set to WC while associated MTRR is UC 1781 * may consolidate to UC". 1782 * Because of this it is best we just fallback to mtrrs 1783 * in this case. 1784 */ 1785 if (ci->ci_family == 6 && ci->ci_model < 15) 1786 ci->ci_feature_flags &= ~CPUID_PAT; 1787 } 1788 1789 /* Remove leading, trailing and duplicated spaces from cpu_brandstr */ 1790 brandstr_from = brandstr_to = cpu_brandstr; 1791 skipspace = 1; 1792 while (*brandstr_from != '\0') { 1793 if (!skipspace || *brandstr_from != ' ') { 1794 skipspace = 0; 1795 *(brandstr_to++) = *brandstr_from; 1796 } 1797 if (*brandstr_from == ' ') 1798 skipspace = 1; 1799 brandstr_from++; 1800 } 1801 if (skipspace && brandstr_to > cpu_brandstr) 1802 brandstr_to--; 1803 *brandstr_to = '\0'; 1804 1805 if (cpu_brandstr[0] == '\0') { 1806 snprintf(cpu_brandstr, 48 /* sizeof(cpu_brandstr) */, 1807 "%s %s%s", vendorname, modifier, name); 1808 } 1809 1810 if (cachesize > -1) { 1811 snprintf(cpu_model, sizeof(cpu_model), 1812 "%s (%s%s%s%s-class, %dKB L2 cache)", 1813 cpu_brandstr, 1814 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1815 ((*token) ? "\" " : ""), classnames[class], cachesize); 1816 } else { 1817 snprintf(cpu_model, sizeof(cpu_model), 1818 "%s (%s%s%s%s-class)", 1819 cpu_brandstr, 1820 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1821 ((*token) ? "\" " : ""), classnames[class]); 1822 } 1823 1824 printf("%s: %s", cpu_device, cpu_model); 1825 1826 if (ci->ci_feature_flags && (ci->ci_feature_flags & CPUID_TSC)) { 1827 /* Has TSC, check if it's constant */ 1828 switch (vendor) { 1829 case CPUVENDOR_INTEL: 1830 if ((ci->ci_family == 0x0f && ci->ci_model >= 0x03) || 1831 (ci->ci_family == 0x06 && ci->ci_model >= 0x0e)) { 1832 ci->ci_flags |= CPUF_CONST_TSC; 1833 } 1834 break; 1835 case CPUVENDOR_VIA: 1836 if (ci->ci_model >= 0x0f) { 1837 ci->ci_flags |= CPUF_CONST_TSC; 1838 } 1839 break; 1840 } 1841 calibrate_cyclecounter(); 1842 if (cpuspeed > 994) { 1843 int ghz, fr; 1844 1845 ghz = (cpuspeed + 9) / 1000; 1846 fr = ((cpuspeed + 9) / 10 ) % 100; 1847 if (fr) 1848 printf(" %d.%02d GHz", ghz, fr); 1849 else 1850 printf(" %d GHz", ghz); 1851 } else { 1852 printf(" %d MHz", cpuspeed); 1853 } 1854 } 1855 1856 if (cpuid_level != -1) 1857 printf(", %02x-%02x-%02x", ci->ci_family, ci->ci_model, 1858 step); 1859 1860 if ((cpu_ecxfeature & CPUIDECX_HV) == 0) { 1861 uint64_t level = 0; 1862 uint32_t dummy; 1863 1864 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 && 1865 ci->ci_family >= 0x0f) { 1866 level = rdmsr(MSR_PATCH_LEVEL); 1867 } else if (strcmp(cpu_vendor, "GenuineIntel") == 0 && 1868 ci->ci_family >= 6) { 1869 wrmsr(MSR_BIOS_SIGN, 0); 1870 CPUID(1, dummy, dummy, dummy, dummy); 1871 level = rdmsr(MSR_BIOS_SIGN) >> 32; 1872 } 1873 if (level != 0) 1874 printf(", patch %08llx", level); 1875 } 1876 1877 printf("\n"); 1878 1879 if (ci->ci_feature_flags) { 1880 int numbits = 0; 1881 1882 printf("%s: ", cpu_device); 1883 max = sizeof(i386_cpuid_features) / 1884 sizeof(i386_cpuid_features[0]); 1885 for (i = 0; i < max; i++) { 1886 if (ci->ci_feature_flags & 1887 i386_cpuid_features[i].feature_bit) { 1888 printf("%s%s", (numbits == 0 ? "" : ","), 1889 i386_cpuid_features[i].feature_name); 1890 numbits++; 1891 } 1892 } 1893 max = sizeof(i386_cpuid_ecxfeatures) 1894 / sizeof(i386_cpuid_ecxfeatures[0]); 1895 for (i = 0; i < max; i++) { 1896 if (cpu_ecxfeature & 1897 i386_cpuid_ecxfeatures[i].feature_bit) { 1898 printf("%s%s", (numbits == 0 ? "" : ","), 1899 i386_cpuid_ecxfeatures[i].feature_name); 1900 numbits++; 1901 } 1902 } 1903 for (i = 0; i < nitems(i386_ecpuid_features); i++) { 1904 if (ecpu_feature & 1905 i386_ecpuid_features[i].feature_bit) { 1906 printf("%s%s", (numbits == 0 ? "" : ","), 1907 i386_ecpuid_features[i].feature_name); 1908 numbits++; 1909 } 1910 } 1911 for (i = 0; i < nitems(i386_ecpuid_ecxfeatures); i++) { 1912 if (ecpu_ecxfeature & 1913 i386_ecpuid_ecxfeatures[i].feature_bit) { 1914 printf("%s%s", (numbits == 0 ? "" : ","), 1915 i386_ecpuid_ecxfeatures[i].feature_name); 1916 numbits++; 1917 } 1918 } 1919 for (i = 0; i < nitems(i386_cpuid_eaxperf); i++) { 1920 if (cpu_perf_eax & 1921 i386_cpuid_eaxperf[i].feature_bit) { 1922 printf("%s%s", (numbits == 0 ? "" : ","), 1923 i386_cpuid_eaxperf[i].feature_name); 1924 numbits++; 1925 } 1926 } 1927 for (i = 0; i < nitems(i386_cpuid_edxapmi); i++) { 1928 if (cpu_apmi_edx & 1929 i386_cpuid_edxapmi[i].feature_bit) { 1930 printf("%s%s", (numbits == 0 ? "" : ","), 1931 i386_cpuid_edxapmi[i].feature_name); 1932 numbits++; 1933 } 1934 } 1935 1936 if (cpuid_level >= 0x07) { 1937 u_int dummy; 1938 1939 /* "Structured Extended Feature Flags" */ 1940 CPUID_LEAF(0x7, 0, dummy, 1941 ci->ci_feature_sefflags_ebx, 1942 ci->ci_feature_sefflags_ecx, 1943 ci->ci_feature_sefflags_edx); 1944 for (i = 0; i < nitems(cpu_seff0_ebxfeatures); i++) 1945 if (ci->ci_feature_sefflags_ebx & 1946 cpu_seff0_ebxfeatures[i].feature_bit) 1947 printf("%s%s", 1948 (numbits == 0 ? "" : ","), 1949 cpu_seff0_ebxfeatures[i].feature_name); 1950 for (i = 0; i < nitems(cpu_seff0_ecxfeatures); i++) 1951 if (ci->ci_feature_sefflags_ecx & 1952 cpu_seff0_ecxfeatures[i].feature_bit) 1953 printf("%s%s", 1954 (numbits == 0 ? "" : ","), 1955 cpu_seff0_ecxfeatures[i].feature_name); 1956 for (i = 0; i < nitems(cpu_seff0_edxfeatures); i++) 1957 if (ci->ci_feature_sefflags_edx & 1958 cpu_seff0_edxfeatures[i].feature_bit) 1959 printf("%s%s", 1960 (numbits == 0 ? "" : ","), 1961 cpu_seff0_edxfeatures[i].feature_name); 1962 } 1963 1964 if (!strcmp(cpu_vendor, "GenuineIntel") && 1965 cpuid_level >= 0x06 ) { 1966 u_int dummy; 1967 1968 CPUID(0x06, ci->ci_feature_tpmflags, dummy, 1969 dummy, dummy); 1970 max = nitems(cpu_tpm_eaxfeatures); 1971 for (i = 0; i < max; i++) 1972 if (ci->ci_feature_tpmflags & 1973 cpu_tpm_eaxfeatures[i].feature_bit) 1974 printf(",%s", cpu_tpm_eaxfeatures[i].feature_name); 1975 } 1976 1977 /* xsave subfeatures */ 1978 if (cpuid_level >= 0xd) { 1979 uint32_t dummy, val; 1980 1981 CPUID_LEAF(0xd, 1, val, dummy, dummy, dummy); 1982 for (i = 0; i < nitems(cpu_xsave_extfeatures); i++) 1983 if (val & cpu_xsave_extfeatures[i].feature_bit) 1984 printf(",%s", 1985 cpu_xsave_extfeatures[i].feature_name); 1986 } 1987 1988 if (cpu_meltdown) 1989 printf(",MELTDOWN"); 1990 1991 printf("\n"); 1992 } 1993 1994 /* 1995 * "Mitigation G-2" per AMD's Whitepaper "Software Techniques 1996 * for Managing Speculation on AMD Processors" 1997 * 1998 * By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch 1999 * serializing instruction. 2000 * 2001 * This MSR is available on all AMD families >= 10h, except 11h 2002 * where LFENCE is always serializing. 2003 */ 2004 if (!strcmp(cpu_vendor, "AuthenticAMD")) { 2005 if (ci->ci_family >= 0x10 && ci->ci_family != 0x11) { 2006 nmsr = msr = rdmsr(MSR_DE_CFG); 2007 nmsr |= DE_CFG_SERIALIZE_LFENCE; 2008 if (msr != nmsr) 2009 wrmsr(MSR_DE_CFG, nmsr); 2010 } 2011 if (family == 0x17 && ci->ci_model >= 0x31 && 2012 (cpu_ecxfeature & CPUIDECX_HV) == 0) { 2013 nmsr = msr = rdmsr(MSR_DE_CFG); 2014 nmsr |= DE_CFG_SERIALIZE_9; 2015 if (msr != nmsr) 2016 wrmsr(MSR_DE_CFG, nmsr); 2017 } 2018 } 2019 2020 /* 2021 * Attempt to disable Silicon Debug and lock the configuration 2022 * if it's enabled and unlocked. 2023 */ 2024 if (!strcmp(cpu_vendor, "GenuineIntel") && 2025 (cpu_ecxfeature & CPUIDECX_SDBG)) { 2026 uint64_t msr; 2027 2028 msr = rdmsr(IA32_DEBUG_INTERFACE); 2029 if ((msr & IA32_DEBUG_INTERFACE_ENABLE) && 2030 (msr & IA32_DEBUG_INTERFACE_LOCK) == 0) { 2031 msr &= IA32_DEBUG_INTERFACE_MASK; 2032 msr |= IA32_DEBUG_INTERFACE_LOCK; 2033 wrmsr(IA32_DEBUG_INTERFACE, msr); 2034 } else if (msr & IA32_DEBUG_INTERFACE_ENABLE) 2035 printf("%s: cannot disable silicon debug\n", 2036 cpu_device); 2037 } 2038 2039 if (CPU_IS_PRIMARY(ci)) { 2040 if (cpu_ecxfeature & CPUIDECX_RDRAND) 2041 has_rdrand = 1; 2042 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_RDSEED) 2043 has_rdseed = 1; 2044 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP) 2045 replacesmap(); 2046 } 2047 2048 #ifndef SMALL_KERNEL 2049 if (cpuspeed != 0 && cpu_cpuspeed == NULL) 2050 cpu_cpuspeed = pentium_cpuspeed; 2051 #endif 2052 2053 cpu_class = class; 2054 2055 ci->cpu_class = class; 2056 2057 /* 2058 * Enable ring 0 write protection. 2059 */ 2060 lcr0(rcr0() | CR0_WP); 2061 2062 /* 2063 * If we have FXSAVE/FXRESTOR, use them. 2064 */ 2065 if (cpu_feature & CPUID_FXSR) { 2066 i386_use_fxsave = 1; 2067 lcr4(rcr4() | CR4_OSFXSR); 2068 2069 /* 2070 * If we have SSE/SSE2, enable XMM exceptions, and 2071 * notify userland. 2072 */ 2073 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) { 2074 if (cpu_feature & CPUID_SSE) 2075 i386_has_sse = 1; 2076 if (cpu_feature & CPUID_SSE2) 2077 i386_has_sse2 = 1; 2078 lcr4(rcr4() | CR4_OSXMMEXCPT); 2079 } 2080 } else 2081 i386_use_fxsave = 0; 2082 2083 } 2084 2085 char * 2086 tm86_cpu_name(int model) 2087 { 2088 u_int32_t regs[4]; 2089 char *name = NULL; 2090 2091 cpuid(0x80860001, regs); 2092 2093 switch (model) { 2094 case 4: 2095 if (((regs[1] >> 16) & 0xff) >= 0x3) 2096 name = "TMS5800"; 2097 else 2098 name = "TMS5600"; 2099 } 2100 2101 return name; 2102 } 2103 2104 #ifndef SMALL_KERNEL 2105 void 2106 cyrix3_get_bus_clock(struct cpu_info *ci) 2107 { 2108 u_int64_t msr; 2109 int bus; 2110 2111 msr = rdmsr(MSR_EBL_CR_POWERON); 2112 bus = (msr >> 18) & 0x3; 2113 switch (bus) { 2114 case 0: 2115 bus_clock = BUS100; 2116 break; 2117 case 1: 2118 bus_clock = BUS133; 2119 break; 2120 case 2: 2121 bus_clock = BUS200; 2122 break; 2123 case 3: 2124 bus_clock = BUS166; 2125 break; 2126 } 2127 } 2128 2129 void 2130 p4_get_bus_clock(struct cpu_info *ci) 2131 { 2132 u_int64_t msr; 2133 int model, bus; 2134 2135 model = (ci->ci_signature >> 4) & 15; 2136 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2137 if (model < 2) { 2138 bus = (msr >> 21) & 0x7; 2139 switch (bus) { 2140 case 0: 2141 bus_clock = BUS100; 2142 break; 2143 case 1: 2144 bus_clock = BUS133; 2145 break; 2146 default: 2147 printf("%s: unknown Pentium 4 (model %d) " 2148 "EBC_FREQUENCY_ID value %d\n", 2149 ci->ci_dev->dv_xname, model, bus); 2150 break; 2151 } 2152 } else { 2153 bus = (msr >> 16) & 0x7; 2154 switch (bus) { 2155 case 0: 2156 bus_clock = (model == 2) ? BUS100 : BUS266; 2157 break; 2158 case 1: 2159 bus_clock = BUS133; 2160 break; 2161 case 2: 2162 bus_clock = BUS200; 2163 break; 2164 case 3: 2165 bus_clock = BUS166; 2166 break; 2167 default: 2168 printf("%s: unknown Pentium 4 (model %d) " 2169 "EBC_FREQUENCY_ID value %d\n", 2170 ci->ci_dev->dv_xname, model, bus); 2171 break; 2172 } 2173 } 2174 } 2175 2176 void 2177 p3_get_bus_clock(struct cpu_info *ci) 2178 { 2179 u_int64_t msr; 2180 int bus; 2181 2182 switch (ci->ci_model) { 2183 case 0x9: /* Pentium M (130 nm, Banias) */ 2184 bus_clock = BUS100; 2185 break; 2186 case 0xd: /* Pentium M (90 nm, Dothan) */ 2187 msr = rdmsr(MSR_FSB_FREQ); 2188 bus = (msr >> 0) & 0x7; 2189 switch (bus) { 2190 case 0: 2191 bus_clock = BUS100; 2192 break; 2193 case 1: 2194 bus_clock = BUS133; 2195 break; 2196 default: 2197 printf("%s: unknown Pentium M FSB_FREQ value %d", 2198 ci->ci_dev->dv_xname, bus); 2199 goto print_msr; 2200 } 2201 break; 2202 case 0x15: /* EP80579 no FSB */ 2203 break; 2204 case 0xe: /* Core Duo/Solo */ 2205 case 0xf: /* Core Xeon */ 2206 case 0x16: /* 65nm Celeron */ 2207 case 0x17: /* Core 2 Extreme/45nm Xeon */ 2208 case 0x1d: /* Xeon MP 7400 */ 2209 msr = rdmsr(MSR_FSB_FREQ); 2210 bus = (msr >> 0) & 0x7; 2211 switch (bus) { 2212 case 5: 2213 bus_clock = BUS100; 2214 break; 2215 case 1: 2216 bus_clock = BUS133; 2217 break; 2218 case 3: 2219 bus_clock = BUS166; 2220 break; 2221 case 2: 2222 bus_clock = BUS200; 2223 break; 2224 case 0: 2225 bus_clock = BUS266; 2226 break; 2227 case 4: 2228 bus_clock = BUS333; 2229 break; 2230 default: 2231 printf("%s: unknown Core FSB_FREQ value %d", 2232 ci->ci_dev->dv_xname, bus); 2233 goto print_msr; 2234 } 2235 break; 2236 case 0x1c: /* Atom */ 2237 case 0x26: /* Atom Z6xx */ 2238 case 0x36: /* Atom [DN]2xxx */ 2239 msr = rdmsr(MSR_FSB_FREQ); 2240 bus = (msr >> 0) & 0x7; 2241 switch (bus) { 2242 case 5: 2243 bus_clock = BUS100; 2244 break; 2245 case 1: 2246 bus_clock = BUS133; 2247 break; 2248 case 3: 2249 bus_clock = BUS166; 2250 break; 2251 case 2: 2252 bus_clock = BUS200; 2253 break; 2254 default: 2255 printf("%s: unknown Atom FSB_FREQ value %d", 2256 ci->ci_dev->dv_xname, bus); 2257 goto print_msr; 2258 } 2259 break; 2260 case 0x1: /* Pentium Pro, model 1 */ 2261 case 0x3: /* Pentium II, model 3 */ 2262 case 0x5: /* Pentium II, II Xeon, Celeron, model 5 */ 2263 case 0x6: /* Celeron, model 6 */ 2264 case 0x7: /* Pentium III, III Xeon, model 7 */ 2265 case 0x8: /* Pentium III, III Xeon, Celeron, model 8 */ 2266 case 0xa: /* Pentium III Xeon, model A */ 2267 case 0xb: /* Pentium III, model B */ 2268 msr = rdmsr(MSR_EBL_CR_POWERON); 2269 bus = (msr >> 18) & 0x3; 2270 switch (bus) { 2271 case 0: 2272 bus_clock = BUS66; 2273 break; 2274 case 1: 2275 bus_clock = BUS133; 2276 break; 2277 case 2: 2278 bus_clock = BUS100; 2279 break; 2280 default: 2281 printf("%s: unknown i686 EBL_CR_POWERON value %d", 2282 ci->ci_dev->dv_xname, bus); 2283 goto print_msr; 2284 } 2285 break; 2286 default: 2287 /* no FSB on modern Intel processors */ 2288 break; 2289 } 2290 return; 2291 print_msr: 2292 /* 2293 * Show the EBL_CR_POWERON MSR, so we'll at least have 2294 * some extra information, such as clock ratio, etc. 2295 */ 2296 printf(" (0x%llx)\n", rdmsr(MSR_EBL_CR_POWERON)); 2297 } 2298 2299 void 2300 p4_update_cpuspeed(void) 2301 { 2302 struct cpu_info *ci; 2303 u_int64_t msr; 2304 int mult; 2305 2306 ci = curcpu(); 2307 p4_get_bus_clock(ci); 2308 2309 if (bus_clock == 0) { 2310 printf("p4_update_cpuspeed: unknown bus clock\n"); 2311 return; 2312 } 2313 2314 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2315 mult = ((msr >> 24) & 0xff); 2316 2317 cpuspeed = (bus_clock * mult) / 100; 2318 } 2319 2320 void 2321 p3_update_cpuspeed(void) 2322 { 2323 struct cpu_info *ci; 2324 u_int64_t msr; 2325 int mult; 2326 const u_int8_t mult_code[] = { 2327 50, 30, 40, 0, 55, 35, 45, 0, 0, 70, 80, 60, 0, 75, 0, 65 }; 2328 2329 ci = curcpu(); 2330 p3_get_bus_clock(ci); 2331 2332 if (bus_clock == 0) { 2333 printf("p3_update_cpuspeed: unknown bus clock\n"); 2334 return; 2335 } 2336 2337 msr = rdmsr(MSR_EBL_CR_POWERON); 2338 mult = (msr >> 22) & 0xf; 2339 mult = mult_code[mult]; 2340 if (!p3_early) 2341 mult += ((msr >> 27) & 0x1) * 40; 2342 2343 cpuspeed = (bus_clock * mult) / 1000; 2344 } 2345 2346 int 2347 pentium_cpuspeed(int *freq) 2348 { 2349 *freq = cpuspeed; 2350 return (0); 2351 } 2352 #endif /* !SMALL_KERNEL */ 2353 2354 /* 2355 * Send an interrupt to process. 2356 * 2357 * Stack is set up to allow sigcode stored 2358 * in u. to call routine, followed by kcall 2359 * to sigreturn routine below. After sigreturn 2360 * resets the signal mask, the stack, and the 2361 * frame pointer, it returns to the user 2362 * specified pc, psl. 2363 */ 2364 int 2365 sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip, 2366 int info, int onstack) 2367 { 2368 struct proc *p = curproc; 2369 struct trapframe *tf = p->p_md.md_regs; 2370 struct sigframe *fp, frame; 2371 register_t sp; 2372 2373 /* 2374 * Build the argument list for the signal handler. 2375 */ 2376 bzero(&frame, sizeof(frame)); 2377 frame.sf_signum = sig; 2378 2379 /* 2380 * Allocate space for the signal handler context. 2381 */ 2382 if ((p->p_sigstk.ss_flags & SS_DISABLE) == 0 && 2383 !sigonstack(tf->tf_esp) && onstack) 2384 sp = trunc_page((vaddr_t)p->p_sigstk.ss_sp + p->p_sigstk.ss_size); 2385 else 2386 sp = tf->tf_esp; 2387 2388 frame.sf_sc.sc_fpstate = NULL; 2389 if (p->p_md.md_flags & MDP_USEDFPU) { 2390 npxsave_proc(p, 1); 2391 sp -= sizeof(union savefpu); 2392 sp &= ~0xf; /* for XMM regs */ 2393 frame.sf_sc.sc_fpstate = (void *)sp; 2394 if (copyout(&p->p_addr->u_pcb.pcb_savefpu, 2395 (void *)sp, sizeof(union savefpu))) 2396 return 1; 2397 2398 /* Signal handlers get a completely clean FP state */ 2399 p->p_md.md_flags &= ~MDP_USEDFPU; 2400 } 2401 2402 fp = (struct sigframe *)sp - 1; 2403 frame.sf_scp = &fp->sf_sc; 2404 frame.sf_sip = NULL; 2405 frame.sf_handler = catcher; 2406 2407 /* 2408 * Build the signal context to be used by sigreturn. 2409 */ 2410 frame.sf_sc.sc_err = tf->tf_err; 2411 frame.sf_sc.sc_trapno = tf->tf_trapno; 2412 frame.sf_sc.sc_mask = mask; 2413 frame.sf_sc.sc_fs = tf->tf_fs; 2414 frame.sf_sc.sc_gs = tf->tf_gs; 2415 frame.sf_sc.sc_es = tf->tf_es; 2416 frame.sf_sc.sc_ds = tf->tf_ds; 2417 frame.sf_sc.sc_eflags = tf->tf_eflags; 2418 frame.sf_sc.sc_edi = tf->tf_edi; 2419 frame.sf_sc.sc_esi = tf->tf_esi; 2420 frame.sf_sc.sc_ebp = tf->tf_ebp; 2421 frame.sf_sc.sc_ebx = tf->tf_ebx; 2422 frame.sf_sc.sc_edx = tf->tf_edx; 2423 frame.sf_sc.sc_ecx = tf->tf_ecx; 2424 frame.sf_sc.sc_eax = tf->tf_eax; 2425 frame.sf_sc.sc_eip = tf->tf_eip; 2426 frame.sf_sc.sc_cs = tf->tf_cs; 2427 frame.sf_sc.sc_esp = tf->tf_esp; 2428 frame.sf_sc.sc_ss = tf->tf_ss; 2429 2430 if (info) { 2431 frame.sf_sip = &fp->sf_si; 2432 frame.sf_si = *ksip; 2433 } 2434 2435 /* XXX don't copyout siginfo if not needed? */ 2436 frame.sf_sc.sc_cookie = (long)&fp->sf_sc ^ p->p_p->ps_sigcookie; 2437 if (copyout(&frame, fp, sizeof(frame)) != 0) 2438 return 1; 2439 2440 /* 2441 * Build context to run handler in. 2442 */ 2443 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2444 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2445 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2446 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2447 tf->tf_eip = p->p_p->ps_sigcode; 2448 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2449 tf->tf_eflags &= ~(PSL_T|PSL_D|PSL_VM|PSL_AC); 2450 tf->tf_esp = (int)fp; 2451 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2452 2453 return 0; 2454 } 2455 2456 /* 2457 * System call to cleanup state after a signal 2458 * has been taken. Reset signal mask and 2459 * stack state from context left by sendsig (above). 2460 * Return to previous pc and psl as specified by 2461 * context left by sendsig. Check carefully to 2462 * make sure that the user has not modified the 2463 * psl to gain improper privileges or to cause 2464 * a machine fault. 2465 */ 2466 int 2467 sys_sigreturn(struct proc *p, void *v, register_t *retval) 2468 { 2469 struct sys_sigreturn_args /* { 2470 syscallarg(struct sigcontext *) sigcntxp; 2471 } */ *uap = v; 2472 struct sigcontext ksc, *scp = SCARG(uap, sigcntxp); 2473 struct trapframe *tf = p->p_md.md_regs; 2474 int error; 2475 2476 if (PROC_PC(p) != p->p_p->ps_sigcoderet) { 2477 sigexit(p, SIGILL); 2478 return (EPERM); 2479 } 2480 2481 if ((error = copyin((caddr_t)scp, &ksc, sizeof(*scp)))) 2482 return (error); 2483 2484 if (ksc.sc_cookie != ((long)scp ^ p->p_p->ps_sigcookie)) { 2485 sigexit(p, SIGILL); 2486 return (EFAULT); 2487 } 2488 2489 /* Prevent reuse of the sigcontext cookie */ 2490 ksc.sc_cookie = 0; 2491 (void)copyout(&ksc.sc_cookie, (caddr_t)scp + 2492 offsetof(struct sigcontext, sc_cookie), sizeof (ksc.sc_cookie)); 2493 2494 /* 2495 * Restore signal ksc. 2496 */ 2497 /* 2498 * Check for security violations. If we're returning to 2499 * protected mode, the CPU will validate the segment registers 2500 * automatically and generate a trap on violations. We handle 2501 * the trap, rather than doing all of the checking here. 2502 */ 2503 if (((ksc.sc_eflags ^ tf->tf_eflags) & PSL_USERSTATIC) != 0 || 2504 !USERMODE(ksc.sc_cs, ksc.sc_eflags)) 2505 return (EINVAL); 2506 2507 tf->tf_fs = ksc.sc_fs; 2508 tf->tf_gs = ksc.sc_gs; 2509 tf->tf_es = ksc.sc_es; 2510 tf->tf_ds = ksc.sc_ds; 2511 tf->tf_eflags = ksc.sc_eflags; 2512 tf->tf_edi = ksc.sc_edi; 2513 tf->tf_esi = ksc.sc_esi; 2514 tf->tf_ebp = ksc.sc_ebp; 2515 tf->tf_ebx = ksc.sc_ebx; 2516 tf->tf_edx = ksc.sc_edx; 2517 tf->tf_ecx = ksc.sc_ecx; 2518 tf->tf_eax = ksc.sc_eax; 2519 tf->tf_eip = ksc.sc_eip; 2520 tf->tf_cs = ksc.sc_cs; 2521 tf->tf_esp = ksc.sc_esp; 2522 tf->tf_ss = ksc.sc_ss; 2523 2524 if (p->p_md.md_flags & MDP_USEDFPU) 2525 npxsave_proc(p, 0); 2526 2527 if (ksc.sc_fpstate) { 2528 union savefpu *sfp = &p->p_addr->u_pcb.pcb_savefpu; 2529 2530 if ((error = copyin(ksc.sc_fpstate, sfp, sizeof(*sfp)))) 2531 return (error); 2532 if (i386_use_fxsave) 2533 sfp->sv_xmm.sv_env.en_mxcsr &= fpu_mxcsr_mask; 2534 p->p_md.md_flags |= MDP_USEDFPU; 2535 } 2536 2537 p->p_sigmask = ksc.sc_mask & ~sigcantmask; 2538 2539 return (EJUSTRETURN); 2540 } 2541 2542 #ifdef MULTIPROCESSOR 2543 /* force a CPU into the kernel, whether or not it's idle */ 2544 void 2545 cpu_kick(struct cpu_info *ci) 2546 { 2547 /* only need to kick other CPUs */ 2548 if (ci != curcpu()) { 2549 if (cpu_mwait_size > 0) { 2550 /* 2551 * If not idling, then send an IPI, else 2552 * just clear the "keep idling" bit. 2553 */ 2554 if ((ci->ci_mwait & MWAIT_IN_IDLE) == 0) 2555 i386_send_ipi(ci, I386_IPI_NOP); 2556 else 2557 atomic_clearbits_int(&ci->ci_mwait, 2558 MWAIT_KEEP_IDLING); 2559 } else { 2560 /* no mwait, so need an IPI */ 2561 i386_send_ipi(ci, I386_IPI_NOP); 2562 } 2563 } 2564 } 2565 #endif 2566 2567 /* 2568 * Notify the current process (p) that it has a signal pending, 2569 * process as soon as possible. 2570 */ 2571 void 2572 signotify(struct proc *p) 2573 { 2574 aston(p); 2575 cpu_kick(p->p_cpu); 2576 } 2577 2578 #ifdef MULTIPROCESSOR 2579 void 2580 cpu_unidle(struct cpu_info *ci) 2581 { 2582 if (cpu_mwait_size > 0 && (ci->ci_mwait & MWAIT_ONLY)) { 2583 /* 2584 * Just clear the "keep idling" bit; if it wasn't 2585 * idling then we didn't need to do anything anyway. 2586 */ 2587 atomic_clearbits_int(&ci->ci_mwait, MWAIT_KEEP_IDLING); 2588 return; 2589 } 2590 2591 if (ci != curcpu()) 2592 i386_send_ipi(ci, I386_IPI_NOP); 2593 } 2594 #endif 2595 2596 int waittime = -1; 2597 struct pcb dumppcb; 2598 2599 __dead void 2600 boot(int howto) 2601 { 2602 #if NACPI > 0 2603 if ((howto & RB_POWERDOWN) != 0 && acpi_softc) 2604 acpi_softc->sc_state = ACPI_STATE_S5; 2605 #endif 2606 2607 if ((howto & RB_POWERDOWN) != 0) 2608 lid_action = 0; 2609 2610 if ((howto & RB_RESET) != 0) 2611 goto doreset; 2612 2613 if (cold) { 2614 if ((howto & RB_USERREQ) == 0) 2615 howto |= RB_HALT; 2616 goto haltsys; 2617 } 2618 2619 boothowto = howto; 2620 if ((howto & RB_NOSYNC) == 0 && waittime < 0) { 2621 waittime = 0; 2622 vfs_shutdown(curproc); 2623 2624 if ((howto & RB_TIMEBAD) == 0) { 2625 resettodr(); 2626 } else { 2627 printf("WARNING: not updating battery clock\n"); 2628 } 2629 } 2630 if_downall(); 2631 2632 uvm_shutdown(); 2633 splhigh(); 2634 cold = 1; 2635 2636 if ((howto & RB_DUMP) != 0) 2637 dumpsys(); 2638 2639 haltsys: 2640 config_suspend_all(DVACT_POWERDOWN); 2641 2642 #ifdef MULTIPROCESSOR 2643 i386_broadcast_ipi(I386_IPI_HALT); 2644 #endif 2645 2646 if ((howto & RB_HALT) != 0) { 2647 #if NACPI > 0 && !defined(SMALL_KERNEL) 2648 extern int acpi_enabled; 2649 2650 if (acpi_enabled) { 2651 delay(500000); 2652 if ((howto & RB_POWERDOWN) != 0) 2653 acpi_powerdown(); 2654 } 2655 #endif 2656 2657 #if NAPM > 0 2658 if ((howto & RB_POWERDOWN) != 0) { 2659 int rv; 2660 2661 printf("\nAttempting to power down...\n"); 2662 /* 2663 * Turn off, if we can. But try to turn disk off and 2664 * wait a bit first--some disk drives are slow to 2665 * clean up and users have reported disk corruption. 2666 * 2667 * If apm_set_powstate() fails the first time, don't 2668 * try to turn the system off. 2669 */ 2670 delay(500000); 2671 apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2672 delay(500000); 2673 rv = apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2674 if (rv == 0 || rv == ENXIO) { 2675 delay(500000); 2676 (void) apm_set_powstate(APM_DEV_ALLDEVS, 2677 APM_SYS_OFF); 2678 } 2679 } 2680 #endif 2681 printf("\n"); 2682 printf("The operating system has halted.\n"); 2683 printf("Please press any key to reboot.\n\n"); 2684 cnpollc(1); /* for proper keyboard command handling */ 2685 cngetc(); 2686 cnpollc(0); 2687 } 2688 2689 doreset: 2690 printf("rebooting...\n"); 2691 cpu_reset(); 2692 for (;;) 2693 continue; 2694 /* NOTREACHED */ 2695 } 2696 2697 /* 2698 * This is called by configure to set dumplo and dumpsize. 2699 * Dumps always skip the first block of disk space 2700 * in case there might be a disk label stored there. 2701 * If there is extra space, put dump at the end to 2702 * reduce the chance that swapping trashes it. 2703 */ 2704 void 2705 dumpconf(void) 2706 { 2707 int nblks; /* size of dump area */ 2708 int i; 2709 2710 if (dumpdev == NODEV || 2711 (nblks = (bdevsw[major(dumpdev)].d_psize)(dumpdev)) == 0) 2712 return; 2713 if (nblks <= ctod(1)) 2714 return; 2715 2716 /* Always skip the first block, in case there is a label there. */ 2717 if (dumplo < ctod(1)) 2718 dumplo = ctod(1); 2719 2720 for (i = 0; i < ndumpmem; i++) 2721 dumpsize = max(dumpsize, dumpmem[i].end); 2722 2723 /* Put dump at end of partition, and make it fit. */ 2724 if (dumpsize > dtoc(nblks - dumplo - 1)) 2725 dumpsize = dtoc(nblks - dumplo - 1); 2726 if (dumplo < nblks - ctod(dumpsize) - 1) 2727 dumplo = nblks - ctod(dumpsize) - 1; 2728 } 2729 2730 /* 2731 * cpu_dump: dump machine-dependent kernel core dump headers. 2732 */ 2733 int 2734 cpu_dump(void) 2735 { 2736 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2737 long buf[dbtob(1) / sizeof (long)]; 2738 kcore_seg_t *segp; 2739 2740 dump = bdevsw[major(dumpdev)].d_dump; 2741 2742 segp = (kcore_seg_t *)buf; 2743 2744 /* 2745 * Generate a segment header. 2746 */ 2747 CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU); 2748 segp->c_size = dbtob(1) - ALIGN(sizeof(*segp)); 2749 2750 return (dump(dumpdev, dumplo, (caddr_t)buf, dbtob(1))); 2751 } 2752 2753 /* 2754 * Doadump comes here after turning off memory management and 2755 * getting on the dump stack, either when called above, or by 2756 * the auto-restart code. 2757 */ 2758 static vaddr_t dumpspace; 2759 2760 vaddr_t 2761 reserve_dumppages(vaddr_t p) 2762 { 2763 2764 dumpspace = p; 2765 return (p + PAGE_SIZE); 2766 } 2767 2768 void 2769 dumpsys(void) 2770 { 2771 u_int i, j, npg; 2772 int maddr; 2773 daddr_t blkno; 2774 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2775 int error; 2776 char *str; 2777 extern int msgbufmapped; 2778 2779 /* Save registers. */ 2780 savectx(&dumppcb); 2781 2782 msgbufmapped = 0; /* don't record dump msgs in msgbuf */ 2783 if (dumpdev == NODEV) 2784 return; 2785 2786 /* 2787 * For dumps during autoconfiguration, 2788 * if dump device has already configured... 2789 */ 2790 if (dumpsize == 0) 2791 dumpconf(); 2792 if (dumplo < 0) 2793 return; 2794 printf("\ndumping to dev %x, offset %ld\n", dumpdev, dumplo); 2795 2796 error = (*bdevsw[major(dumpdev)].d_psize)(dumpdev); 2797 printf("dump "); 2798 if (error == -1) { 2799 printf("area unavailable\n"); 2800 return; 2801 } 2802 2803 #if 0 /* XXX this doesn't work. grr. */ 2804 /* toss any characters present prior to dump */ 2805 while (sget() != NULL); /*syscons and pccons differ */ 2806 #endif 2807 2808 /* scan through the dumpmem list */ 2809 dump = bdevsw[major(dumpdev)].d_dump; 2810 error = cpu_dump(); 2811 for (i = 0; !error && i < ndumpmem; i++) { 2812 2813 npg = dumpmem[i].end - dumpmem[i].start; 2814 maddr = ptoa(dumpmem[i].start); 2815 blkno = dumplo + btodb(maddr) + 1; 2816 #if 0 2817 printf("(%d %lld %d) ", maddr, (long long)blkno, npg); 2818 #endif 2819 for (j = npg; j--; maddr += NBPG, blkno += btodb(NBPG)) { 2820 2821 /* Print out how many MBs we have more to go. */ 2822 if (dbtob(blkno - dumplo) % (1024 * 1024) < NBPG) 2823 printf("%ld ", 2824 (ptoa(dumpsize) - maddr) / (1024 * 1024)); 2825 #if 0 2826 printf("(%x %lld) ", maddr, (long long)blkno); 2827 #endif 2828 pmap_enter(pmap_kernel(), dumpspace, maddr, 2829 PROT_READ, PMAP_WIRED); 2830 if ((error = (*dump)(dumpdev, blkno, 2831 (caddr_t)dumpspace, NBPG))) 2832 break; 2833 2834 #if 0 /* XXX this doesn't work. grr. */ 2835 /* operator aborting dump? */ 2836 if (sget() != NULL) { 2837 error = EINTR; 2838 break; 2839 } 2840 #endif 2841 } 2842 } 2843 2844 switch (error) { 2845 2846 case 0: str = "succeeded\n\n"; break; 2847 case ENXIO: str = "device bad\n\n"; break; 2848 case EFAULT: str = "device not ready\n\n"; break; 2849 case EINVAL: str = "area improper\n\n"; break; 2850 case EIO: str = "i/o error\n\n"; break; 2851 case EINTR: str = "aborted from console\n\n"; break; 2852 default: str = "error %d\n\n"; break; 2853 } 2854 printf(str, error); 2855 2856 delay(5000000); /* 5 seconds */ 2857 } 2858 2859 /* 2860 * Clear registers on exec 2861 */ 2862 void 2863 setregs(struct proc *p, struct exec_package *pack, u_long stack, 2864 struct ps_strings *arginfo) 2865 { 2866 struct pcb *pcb = &p->p_addr->u_pcb; 2867 struct pmap *pmap = vm_map_pmap(&p->p_vmspace->vm_map); 2868 struct trapframe *tf = p->p_md.md_regs; 2869 2870 #if NNPX > 0 2871 /* If we were using the FPU, forget about it. */ 2872 if (pcb->pcb_fpcpu != NULL) 2873 npxsave_proc(p, 0); 2874 p->p_md.md_flags &= ~MDP_USEDFPU; 2875 #endif 2876 2877 initcodesegment(&pmap->pm_codeseg); 2878 setsegment(&pcb->pcb_threadsegs[TSEG_FS], 0, 2879 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2880 setsegment(&pcb->pcb_threadsegs[TSEG_GS], 0, 2881 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2882 2883 /* 2884 * And update the GDT since we return to the user process 2885 * by leaving the syscall (we don't do another pmap_activate()). 2886 */ 2887 curcpu()->ci_gdt[GUCODE_SEL].sd = pmap->pm_codeseg; 2888 curcpu()->ci_gdt[GUFS_SEL].sd = pcb->pcb_threadsegs[TSEG_FS]; 2889 curcpu()->ci_gdt[GUGS_SEL].sd = pcb->pcb_threadsegs[TSEG_GS]; 2890 2891 /* 2892 * And reset the hiexec marker in the pmap. 2893 */ 2894 pmap->pm_hiexec = 0; 2895 2896 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2897 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2898 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2899 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2900 tf->tf_edi = 0; 2901 tf->tf_esi = 0; 2902 tf->tf_ebp = 0; 2903 tf->tf_ebx = (int)p->p_p->ps_strings; 2904 tf->tf_edx = 0; 2905 tf->tf_ecx = 0; 2906 tf->tf_eax = 0; 2907 tf->tf_eip = pack->ep_entry; 2908 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2909 tf->tf_eflags = PSL_USERSET; 2910 tf->tf_esp = stack; 2911 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2912 } 2913 2914 /* 2915 * Initialize segments and descriptor tables 2916 */ 2917 2918 /* IDT is now a full page, so we can map it in u-k */ 2919 union { 2920 struct gate_descriptor idt[NIDT]; 2921 char align[PAGE_SIZE]; 2922 } _idt_region __aligned(PAGE_SIZE); 2923 #define idt_region _idt_region.idt 2924 struct gate_descriptor *idt = idt_region; 2925 2926 extern struct user *proc0paddr; 2927 2928 void 2929 setgate(struct gate_descriptor *gd, void *func, int args, int type, int dpl, 2930 int seg) 2931 { 2932 2933 gd->gd_looffset = (int)func; 2934 gd->gd_selector = GSEL(seg, SEL_KPL); 2935 gd->gd_stkcpy = args; 2936 gd->gd_xx = 0; 2937 gd->gd_type = type; 2938 gd->gd_dpl = dpl; 2939 gd->gd_p = 1; 2940 gd->gd_hioffset = (int)func >> 16; 2941 } 2942 2943 void 2944 unsetgate(struct gate_descriptor *gd) 2945 { 2946 gd->gd_p = 0; 2947 gd->gd_hioffset = 0; 2948 gd->gd_looffset = 0; 2949 gd->gd_selector = 0; 2950 gd->gd_xx = 0; 2951 gd->gd_stkcpy = 0; 2952 gd->gd_type = 0; 2953 gd->gd_dpl = 0; 2954 } 2955 2956 void 2957 setregion(struct region_descriptor *rd, void *base, size_t limit) 2958 { 2959 rd->rd_limit = (int)limit; 2960 rd->rd_base = (int)base; 2961 } 2962 2963 void 2964 initcodesegment(struct segment_descriptor *cs) 2965 { 2966 if (cpu_pae) { 2967 /* 2968 * When code execution is managed using NX feature 2969 * in pmapae.c, GUCODE_SEL should cover userland. 2970 */ 2971 setsegment(cs, 0, atop(VM_MAXUSER_ADDRESS - 1), 2972 SDT_MEMERA, SEL_UPL, 1, 1); 2973 } else { 2974 /* 2975 * For pmap.c's non-PAE/NX line-in-the-sand execution, reset 2976 * the code segment limit to I386_MAX_EXE_ADDR in the pmap; 2977 * this gets copied into the GDT for GUCODE_SEL by 2978 * pmap_activate(). Similarly, reset the base of each of 2979 * the two thread data segments to zero in the pcb; they'll 2980 * get copied into the GDT for GUFS_SEL and GUGS_SEL. 2981 */ 2982 setsegment(cs, 0, atop(I386_MAX_EXE_ADDR - 1), 2983 SDT_MEMERA, SEL_UPL, 1, 1); 2984 } 2985 } 2986 2987 void 2988 setsegment(struct segment_descriptor *sd, void *base, size_t limit, int type, 2989 int dpl, int def32, int gran) 2990 { 2991 2992 sd->sd_lolimit = (int)limit; 2993 sd->sd_lobase = (int)base; 2994 sd->sd_type = type; 2995 sd->sd_dpl = dpl; 2996 sd->sd_p = 1; 2997 sd->sd_hilimit = (int)limit >> 16; 2998 sd->sd_xx = 0; 2999 sd->sd_def32 = def32; 3000 sd->sd_gran = gran; 3001 sd->sd_hibase = (int)base >> 24; 3002 } 3003 3004 #define IDTVEC(name) __CONCAT(X, name) 3005 extern int IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 3006 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(dble), IDTVEC(fpusegm), 3007 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), IDTVEC(page), 3008 IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), IDTVEC(syscall), IDTVEC(mchk), 3009 IDTVEC(simd); 3010 3011 extern int IDTVEC(f00f_redirect); 3012 3013 int cpu_f00f_bug = 0; 3014 3015 void 3016 fix_f00f(void) 3017 { 3018 struct region_descriptor region; 3019 vaddr_t va; 3020 paddr_t pa; 3021 void *p; 3022 3023 /* Allocate two new pages */ 3024 va = (vaddr_t)km_alloc(NBPG*2, &kv_any, &kp_zero, &kd_waitok); 3025 p = (void *)(va + NBPG - 7*sizeof(*idt)); 3026 3027 /* Copy over old IDT */ 3028 bcopy(idt, p, sizeof(idt_region)); 3029 idt = p; 3030 3031 /* Fix up paging redirect */ 3032 setgate(&idt[ 14], &IDTVEC(f00f_redirect), 0, SDT_SYS386IGT, SEL_KPL, 3033 GCODE_SEL); 3034 3035 /* Map first page RO */ 3036 pmap_pte_setbits(va, 0, PG_RW); 3037 3038 /* add k-u read-only mappings XXX old IDT stays in place */ 3039 /* XXX hshoexer: are f00f affected CPUs affected by meltdown? */ 3040 pmap_extract(pmap_kernel(), va, &pa); 3041 pmap_enter_special(va, pa, PROT_READ, 0); 3042 pmap_extract(pmap_kernel(), va + PAGE_SIZE, &pa); 3043 pmap_enter_special(va + PAGE_SIZE, pa, PROT_READ, 0); 3044 3045 /* Reload idtr */ 3046 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3047 lidt(®ion); 3048 3049 /* Tell the rest of the world */ 3050 cpu_f00f_bug = 1; 3051 } 3052 3053 #ifdef MULTIPROCESSOR 3054 void 3055 cpu_init_idt(void) 3056 { 3057 struct region_descriptor region; 3058 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3059 lidt(®ion); 3060 } 3061 #endif /* MULTIPROCESSOR */ 3062 3063 void 3064 init386(paddr_t first_avail) 3065 { 3066 int i, kb; 3067 struct region_descriptor region; 3068 bios_memmap_t *im; 3069 3070 proc0.p_addr = proc0paddr; 3071 cpu_info_primary.ci_self = &cpu_info_primary; 3072 cpu_info_primary.ci_curpcb = &proc0.p_addr->u_pcb; 3073 cpu_info_primary.ci_tss = &cpu_info_full_primary.cif_tss; 3074 cpu_info_primary.ci_nmi_tss = &cpu_info_full_primary.cif_nmi_tss; 3075 cpu_info_primary.ci_gdt = (void *)&cpu_info_full_primary.cif_gdt; 3076 3077 /* make bootstrap gdt gates and memory segments */ 3078 setsegment(&cpu_info_primary.ci_gdt[GCODE_SEL].sd, 0, 0xfffff, 3079 SDT_MEMERA, SEL_KPL, 1, 1); 3080 setsegment(&cpu_info_primary.ci_gdt[GICODE_SEL].sd, 0, 0xfffff, 3081 SDT_MEMERA, SEL_KPL, 1, 1); 3082 setsegment(&cpu_info_primary.ci_gdt[GDATA_SEL].sd, 0, 0xfffff, 3083 SDT_MEMRWA, SEL_KPL, 1, 1); 3084 setsegment(&cpu_info_primary.ci_gdt[GUCODE_SEL].sd, 0, 3085 atop(I386_MAX_EXE_ADDR) - 1, SDT_MEMERA, SEL_UPL, 1, 1); 3086 setsegment(&cpu_info_primary.ci_gdt[GUDATA_SEL].sd, 0, 3087 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3088 setsegment(&cpu_info_primary.ci_gdt[GCPU_SEL].sd, &cpu_info_primary, 3089 sizeof(struct cpu_info)-1, SDT_MEMRWA, SEL_KPL, 0, 0); 3090 setsegment(&cpu_info_primary.ci_gdt[GUFS_SEL].sd, 0, 3091 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3092 setsegment(&cpu_info_primary.ci_gdt[GUGS_SEL].sd, 0, 3093 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3094 setsegment(&cpu_info_primary.ci_gdt[GTSS_SEL].sd, 3095 cpu_info_primary.ci_tss, sizeof(struct i386tss)-1, 3096 SDT_SYS386TSS, SEL_KPL, 0, 0); 3097 setsegment(&cpu_info_primary.ci_gdt[GNMITSS_SEL].sd, 3098 cpu_info_primary.ci_nmi_tss, sizeof(struct i386tss)-1, 3099 SDT_SYS386TSS, SEL_KPL, 0, 0); 3100 3101 /* exceptions */ 3102 setgate(&idt[ 0], &IDTVEC(div), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3103 setgate(&idt[ 1], &IDTVEC(dbg), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3104 setgate(&idt[ 2], NULL, 0, SDT_SYSTASKGT, SEL_KPL, GNMITSS_SEL); 3105 setgate(&idt[ 3], &IDTVEC(bpt), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3106 setgate(&idt[ 4], &IDTVEC(ofl), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3107 setgate(&idt[ 5], &IDTVEC(bnd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3108 setgate(&idt[ 6], &IDTVEC(ill), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3109 setgate(&idt[ 7], &IDTVEC(dna), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3110 setgate(&idt[ 8], &IDTVEC(dble), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3111 setgate(&idt[ 9], &IDTVEC(fpusegm), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3112 setgate(&idt[ 10], &IDTVEC(tss), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3113 setgate(&idt[ 11], &IDTVEC(missing), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3114 setgate(&idt[ 12], &IDTVEC(stk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3115 setgate(&idt[ 13], &IDTVEC(prot), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3116 setgate(&idt[ 14], &IDTVEC(page), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3117 setgate(&idt[ 15], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3118 setgate(&idt[ 16], &IDTVEC(fpu), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3119 setgate(&idt[ 17], &IDTVEC(align), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3120 setgate(&idt[ 18], &IDTVEC(mchk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3121 setgate(&idt[ 19], &IDTVEC(simd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3122 for (i = 20; i < NRSVIDT; i++) 3123 setgate(&idt[i], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3124 for (i = NRSVIDT; i < NIDT; i++) 3125 unsetgate(&idt[i]); 3126 setgate(&idt[128], &IDTVEC(syscall), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3127 3128 setregion(®ion, cpu_info_primary.ci_gdt, GDT_SIZE - 1); 3129 lgdt(®ion); 3130 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3131 lidt(®ion); 3132 3133 /* 3134 * Initialize the I/O port and I/O mem extent maps. 3135 * Note: we don't have to check the return value since 3136 * creation of a fixed extent map will never fail (since 3137 * descriptor storage has already been allocated). 3138 * 3139 * N.B. The iomem extent manages _all_ physical addresses 3140 * on the machine. When the amount of RAM is found, the two 3141 * extents of RAM are allocated from the map (0 -> ISA hole 3142 * and end of ISA hole -> end of RAM). 3143 */ 3144 ioport_ex = extent_create("ioport", 0x0, 0xffff, M_DEVBUF, 3145 (caddr_t)ioport_ex_storage, sizeof(ioport_ex_storage), 3146 EX_NOCOALESCE|EX_NOWAIT); 3147 iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF, 3148 (caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage), 3149 EX_NOCOALESCE|EX_NOWAIT); 3150 3151 #if NISA > 0 3152 isa_defaultirq(); 3153 #endif 3154 3155 /* 3156 * Attach the glass console early in case we need to display a panic. 3157 */ 3158 cninit(); 3159 3160 /* 3161 * Saving SSE registers won't work if the save area isn't 3162 * 16-byte aligned. 3163 */ 3164 if (offsetof(struct user, u_pcb.pcb_savefpu) & 0xf) 3165 panic("init386: pcb_savefpu not 16-byte aligned"); 3166 3167 /* call pmap initialization to make new kernel address space */ 3168 pmap_bootstrap((vaddr_t)atdevbase + IOM_SIZE); 3169 3170 /* 3171 * Boot arguments are in a single page specified by /boot. 3172 * 3173 * We require the "new" vector form, as well as memory ranges 3174 * to be given in bytes rather than KB. 3175 */ 3176 if ((bootapiver & (BAPIV_VECTOR | BAPIV_BMEMMAP)) == 3177 (BAPIV_VECTOR | BAPIV_BMEMMAP)) { 3178 if (bootargc > NBPG) 3179 panic("too many boot args"); 3180 3181 if (extent_alloc_region(iomem_ex, (paddr_t)bootargv, bootargc, 3182 EX_NOWAIT)) 3183 panic("cannot reserve /boot args memory"); 3184 3185 pmap_enter(pmap_kernel(), (vaddr_t)bootargp, (paddr_t)bootargv, 3186 PROT_READ | PROT_WRITE, 3187 PROT_READ | PROT_WRITE | PMAP_WIRED); 3188 3189 bios_getopt(); 3190 3191 } else 3192 panic("/boot too old: upgrade!"); 3193 3194 #ifdef DIAGNOSTIC 3195 if (bios_memmap == NULL) 3196 panic("no BIOS memory map supplied"); 3197 #endif 3198 3199 /* 3200 * account all the memory passed in the map from /boot 3201 * calculate avail_end and count the physmem. 3202 */ 3203 avail_end = 0; 3204 physmem = 0; 3205 #ifdef DEBUG 3206 printf("memmap:"); 3207 #endif 3208 for(i = 0, im = bios_memmap; im->type != BIOS_MAP_END; im++) 3209 if (im->type == BIOS_MAP_FREE) { 3210 paddr_t a, e; 3211 #ifdef DEBUG 3212 printf(" %llx-%llx", im->addr, im->addr + im->size); 3213 #endif 3214 3215 if (im->addr >= 0x100000000ULL) { 3216 #ifdef DEBUG 3217 printf("-H"); 3218 #endif 3219 continue; 3220 } 3221 3222 a = round_page(im->addr); 3223 if (im->addr + im->size <= 0xfffff000ULL) 3224 e = trunc_page(im->addr + im->size); 3225 else { 3226 #ifdef DEBUG 3227 printf("-T"); 3228 #endif 3229 e = 0xfffff000; 3230 } 3231 3232 /* skip first 16 pages due to SMI corruption */ 3233 if (a < 16 * NBPG) 3234 a = 16 * NBPG; 3235 3236 #ifdef MULTIPROCESSOR 3237 /* skip MP trampoline code page */ 3238 if (a < MP_TRAMPOLINE + NBPG) 3239 a = MP_TRAMPOLINE + NBPG; 3240 3241 /* skip MP trampoline data page */ 3242 if (a < MP_TRAMP_DATA + NBPG) 3243 a = MP_TRAMP_DATA + NBPG; 3244 #endif /* MULTIPROCESSOR */ 3245 3246 #if NACPI > 0 && !defined(SMALL_KERNEL) 3247 /* skip ACPI resume trampoline code page */ 3248 if (a < ACPI_TRAMPOLINE + NBPG) 3249 a = ACPI_TRAMPOLINE + NBPG; 3250 3251 /* skip ACPI resume trampoline data page */ 3252 if (a < ACPI_TRAMP_DATA + NBPG) 3253 a = ACPI_TRAMP_DATA + NBPG; 3254 #endif /* ACPI */ 3255 3256 #ifdef HIBERNATE 3257 /* skip hibernate reserved pages */ 3258 if (a < HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE) 3259 a = HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE; 3260 #endif /* HIBERNATE */ 3261 3262 /* skip shorter than page regions */ 3263 if (a >= e || (e - a) < NBPG) { 3264 #ifdef DEBUG 3265 printf("-S"); 3266 #endif 3267 continue; 3268 } 3269 3270 /* 3271 * XXX Some buggy ACPI BIOSes use memory that 3272 * they declare as free. Current worst offender 3273 * is Supermicro 5019D-FTN4. Typically the 3274 * affected memory areas are small blocks 3275 * between areas reserved for ACPI and other 3276 * BIOS goo. So skip areas smaller than 32 MB 3277 * above the 16 MB boundary (to avoid 3278 * affecting legacy stuff). 3279 */ 3280 if (a > 16*1024*1024 && (e - a) < 32*1024*1024) { 3281 #ifdef DEBUG 3282 printf("-X"); 3283 #endif 3284 continue; 3285 } 3286 3287 /* skip legacy IO region */ 3288 if ((a > IOM_BEGIN && a < IOM_END) || 3289 (e > IOM_BEGIN && e < IOM_END)) { 3290 #ifdef DEBUG 3291 printf("-I"); 3292 #endif 3293 continue; 3294 } 3295 3296 if (extent_alloc_region(iomem_ex, a, e - a, EX_NOWAIT)) 3297 /* XXX What should we do? */ 3298 printf("\nWARNING: CAN'T ALLOCATE RAM (%lx-%lx)" 3299 " FROM IOMEM EXTENT MAP!\n", a, e); 3300 3301 physmem += atop(e - a); 3302 dumpmem[i].start = atop(a); 3303 dumpmem[i].end = atop(e); 3304 i++; 3305 avail_end = max(avail_end, e); 3306 } 3307 3308 ndumpmem = i; 3309 avail_end -= round_page(MSGBUFSIZE); 3310 3311 #ifdef DEBUG 3312 printf(": %lx\n", avail_end); 3313 #endif 3314 if (physmem < atop(4 * 1024 * 1024)) { 3315 printf("\awarning: too little memory available;" 3316 "running in degraded mode\npress a key to confirm\n\n"); 3317 cnpollc(1); 3318 cngetc(); 3319 cnpollc(0); 3320 } 3321 3322 #ifdef DEBUG 3323 printf("physload: "); 3324 #endif 3325 kb = atop(KERNTEXTOFF - KERNBASE); 3326 if (kb > atop(IOM_END)) { 3327 paddr_t lim = atop(IOM_END); 3328 #ifdef DEBUG 3329 printf(" %lx-%x (<16M)", lim, kb); 3330 #endif 3331 uvm_page_physload(lim, kb, lim, kb, 0); 3332 } 3333 3334 for (i = 0; i < ndumpmem; i++) { 3335 paddr_t a, e; 3336 3337 a = dumpmem[i].start; 3338 e = dumpmem[i].end; 3339 if (a < atop(first_avail) && e > atop(first_avail)) 3340 a = atop(first_avail); 3341 if (e > atop(avail_end)) 3342 e = atop(avail_end); 3343 3344 if (a < e) { 3345 #ifdef DEBUG 3346 printf(" %lx-%lx", a, e); 3347 #endif 3348 uvm_page_physload(a, e, a, e, 0); 3349 } 3350 } 3351 #ifdef DEBUG 3352 printf("\n"); 3353 #endif 3354 3355 tlbflush(); 3356 #if 0 3357 #if NISADMA > 0 3358 /* 3359 * Some motherboards/BIOSes remap the 384K of RAM that would 3360 * normally be covered by the ISA hole to the end of memory 3361 * so that it can be used. However, on a 16M system, this 3362 * would cause bounce buffers to be allocated and used. 3363 * This is not desirable behaviour, as more than 384K of 3364 * bounce buffers might be allocated. As a work-around, 3365 * we round memory down to the nearest 1M boundary if 3366 * we're using any isadma devices and the remapped memory 3367 * is what puts us over 16M. 3368 */ 3369 if (extmem > (15*1024) && extmem < (16*1024)) { 3370 printf("Warning: ignoring %dk of remapped memory\n", 3371 extmem - (15*1024)); 3372 extmem = (15*1024); 3373 } 3374 #endif 3375 #endif 3376 3377 #ifdef DDB 3378 db_machine_init(); 3379 ddb_init(); 3380 if (boothowto & RB_KDB) 3381 db_enter(); 3382 #endif 3383 3384 softintr_init(); 3385 } 3386 3387 /* 3388 * consinit: 3389 * initialize the system console. 3390 */ 3391 void 3392 consinit(void) 3393 { 3394 /* Already done in init386(). */ 3395 } 3396 3397 void 3398 cpu_reset(void) 3399 { 3400 struct region_descriptor region; 3401 3402 intr_disable(); 3403 3404 if (cpuresetfn) 3405 (*cpuresetfn)(); 3406 3407 /* 3408 * The keyboard controller has 4 random output pins, one of which is 3409 * connected to the RESET pin on the CPU in many PCs. We tell the 3410 * keyboard controller to pulse this line a couple of times. 3411 */ 3412 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3413 delay(100000); 3414 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3415 delay(100000); 3416 3417 /* 3418 * Try to cause a triple fault and watchdog reset by setting the 3419 * IDT to point to nothing. 3420 */ 3421 bzero((caddr_t)idt, sizeof(idt_region)); 3422 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3423 lidt(®ion); 3424 __asm volatile("divl %0,%1" : : "q" (0), "a" (0)); 3425 3426 /* 3427 * Try to cause a triple fault and watchdog reset by unmapping the 3428 * entire address space. 3429 */ 3430 bzero((caddr_t)PTD, NBPG); 3431 tlbflush(); 3432 3433 for (;;) 3434 continue; 3435 /* NOTREACHED */ 3436 } 3437 3438 void 3439 cpu_initclocks(void) 3440 { 3441 (*initclock_func)(); /* lapic or i8254 */ 3442 } 3443 3444 void 3445 cpu_startclock(void) 3446 { 3447 (*startclock_func)(); 3448 } 3449 3450 void 3451 need_resched(struct cpu_info *ci) 3452 { 3453 ci->ci_want_resched = 1; 3454 3455 /* There's a risk we'll be called before the idle threads start */ 3456 if (ci->ci_curproc) { 3457 aston(ci->ci_curproc); 3458 cpu_kick(ci); 3459 } 3460 } 3461 3462 /* Allocate an IDT vector slot within the given range. 3463 * XXX needs locking to avoid MP allocation races. 3464 */ 3465 3466 int 3467 idt_vec_alloc(int low, int high) 3468 { 3469 int vec; 3470 3471 for (vec = low; vec <= high; vec++) 3472 if (idt[vec].gd_p == 0) 3473 return (vec); 3474 return (0); 3475 } 3476 3477 void 3478 idt_vec_set(int vec, void (*function)(void)) 3479 { 3480 setgate(&idt[vec], function, 0, SDT_SYS386IGT, SEL_KPL, GICODE_SEL); 3481 } 3482 3483 void 3484 idt_vec_free(int vec) 3485 { 3486 unsetgate(&idt[vec]); 3487 } 3488 3489 const struct sysctl_bounded_args cpuctl_vars[] = { 3490 { CPU_LIDACTION, &lid_action, 0, 2 }, 3491 { CPU_CPUID, &cpu_id, SYSCTL_INT_READONLY }, 3492 { CPU_OSFXSR, &i386_use_fxsave, SYSCTL_INT_READONLY }, 3493 { CPU_SSE, &i386_has_sse, SYSCTL_INT_READONLY }, 3494 { CPU_SSE2, &i386_has_sse2, SYSCTL_INT_READONLY }, 3495 { CPU_XCRYPT, &i386_has_xcrypt, SYSCTL_INT_READONLY }, 3496 }; 3497 3498 /* 3499 * machine dependent system variables. 3500 */ 3501 int 3502 cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp, 3503 size_t newlen, struct proc *p) 3504 { 3505 dev_t dev; 3506 3507 switch (name[0]) { 3508 case CPU_CONSDEV: 3509 if (namelen != 1) 3510 return (ENOTDIR); /* overloaded */ 3511 3512 if (cn_tab != NULL) 3513 dev = cn_tab->cn_dev; 3514 else 3515 dev = NODEV; 3516 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3517 #if NBIOS > 0 3518 case CPU_BIOS: 3519 return bios_sysctl(name + 1, namelen - 1, oldp, oldlenp, 3520 newp, newlen, p); 3521 #endif 3522 case CPU_BLK2CHR: 3523 if (namelen != 2) 3524 return (ENOTDIR); /* overloaded */ 3525 dev = blktochr((dev_t)name[1]); 3526 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3527 case CPU_CHR2BLK: 3528 if (namelen != 2) 3529 return (ENOTDIR); /* overloaded */ 3530 dev = chrtoblk((dev_t)name[1]); 3531 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3532 case CPU_ALLOWAPERTURE: 3533 #ifdef APERTURE 3534 if (securelevel > 0) 3535 return (sysctl_int_lower(oldp, oldlenp, newp, newlen, 3536 &allowaperture)); 3537 else 3538 return (sysctl_int(oldp, oldlenp, newp, newlen, 3539 &allowaperture)); 3540 #else 3541 return (sysctl_rdint(oldp, oldlenp, newp, 0)); 3542 #endif 3543 case CPU_CPUVENDOR: 3544 return (sysctl_rdstring(oldp, oldlenp, newp, cpu_vendor)); 3545 case CPU_CPUFEATURE: 3546 return (sysctl_rdint(oldp, oldlenp, newp, curcpu()->ci_feature_flags)); 3547 case CPU_KBDRESET: 3548 return (sysctl_securelevel_int(oldp, oldlenp, newp, newlen, 3549 &kbd_reset)); 3550 #if NPCKBC > 0 && NUKBD > 0 3551 case CPU_FORCEUKBD: 3552 { 3553 int error; 3554 3555 if (forceukbd) 3556 return (sysctl_rdint(oldp, oldlenp, newp, forceukbd)); 3557 3558 error = sysctl_int(oldp, oldlenp, newp, newlen, &forceukbd); 3559 if (forceukbd) 3560 pckbc_release_console(); 3561 return (error); 3562 } 3563 #endif 3564 default: 3565 return (sysctl_bounded_arr(cpuctl_vars, nitems(cpuctl_vars), 3566 name, namelen, oldp, oldlenp, newp, newlen)); 3567 } 3568 /* NOTREACHED */ 3569 } 3570 3571 int 3572 bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags, 3573 bus_space_handle_t *bshp) 3574 { 3575 int error; 3576 struct extent *ex; 3577 3578 /* 3579 * Pick the appropriate extent map. 3580 */ 3581 if (t == I386_BUS_SPACE_IO) { 3582 ex = ioport_ex; 3583 if (flags & BUS_SPACE_MAP_LINEAR) 3584 return (EINVAL); 3585 } else if (t == I386_BUS_SPACE_MEM) { 3586 ex = iomem_ex; 3587 } else { 3588 panic("bus_space_map: bad bus space tag"); 3589 } 3590 3591 /* 3592 * Before we go any further, let's make sure that this 3593 * region is available. 3594 */ 3595 error = extent_alloc_region(ex, bpa, size, 3596 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0)); 3597 if (error) 3598 return (error); 3599 3600 /* 3601 * For I/O space, that's all she wrote. 3602 */ 3603 if (t == I386_BUS_SPACE_IO) { 3604 *bshp = bpa; 3605 return (0); 3606 } 3607 3608 if (IOM_BEGIN <= bpa && bpa <= IOM_END) { 3609 *bshp = (bus_space_handle_t)ISA_HOLE_VADDR(bpa); 3610 return (0); 3611 } 3612 3613 /* 3614 * For memory space, map the bus physical address to 3615 * a kernel virtual address. 3616 */ 3617 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3618 if (error) { 3619 if (extent_free(ex, bpa, size, EX_NOWAIT | 3620 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3621 printf("bus_space_map: pa 0x%lx, size 0x%lx\n", 3622 bpa, size); 3623 printf("bus_space_map: can't free region\n"); 3624 } 3625 } 3626 3627 return (error); 3628 } 3629 3630 int 3631 _bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, 3632 int flags, bus_space_handle_t *bshp) 3633 { 3634 /* 3635 * For I/O space, that's all she wrote. 3636 */ 3637 if (t == I386_BUS_SPACE_IO) { 3638 *bshp = bpa; 3639 return (0); 3640 } 3641 3642 /* 3643 * For memory space, map the bus physical address to 3644 * a kernel virtual address. 3645 */ 3646 return (bus_mem_add_mapping(bpa, size, flags, bshp)); 3647 } 3648 3649 int 3650 bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend, 3651 bus_size_t size, bus_size_t alignment, bus_size_t boundary, 3652 int flags, bus_addr_t *bpap, bus_space_handle_t *bshp) 3653 { 3654 struct extent *ex; 3655 u_long bpa; 3656 int error; 3657 3658 /* 3659 * Pick the appropriate extent map. 3660 */ 3661 if (t == I386_BUS_SPACE_IO) { 3662 ex = ioport_ex; 3663 } else if (t == I386_BUS_SPACE_MEM) { 3664 ex = iomem_ex; 3665 } else { 3666 panic("bus_space_alloc: bad bus space tag"); 3667 } 3668 3669 /* 3670 * Sanity check the allocation against the extent's boundaries. 3671 */ 3672 if (rstart < ex->ex_start || rend > ex->ex_end) 3673 panic("bus_space_alloc: bad region start/end"); 3674 3675 /* 3676 * Do the requested allocation. 3677 */ 3678 error = extent_alloc_subregion(ex, rstart, rend, size, alignment, 0, 3679 boundary, EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0), 3680 &bpa); 3681 3682 if (error) 3683 return (error); 3684 3685 /* 3686 * For I/O space, that's all she wrote. 3687 */ 3688 if (t == I386_BUS_SPACE_IO) { 3689 *bshp = *bpap = bpa; 3690 return (0); 3691 } 3692 3693 /* 3694 * For memory space, map the bus physical address to 3695 * a kernel virtual address. 3696 */ 3697 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3698 if (error) { 3699 if (extent_free(iomem_ex, bpa, size, EX_NOWAIT | 3700 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3701 printf("bus_space_alloc: pa 0x%lx, size 0x%lx\n", 3702 bpa, size); 3703 printf("bus_space_alloc: can't free region\n"); 3704 } 3705 } 3706 3707 *bpap = bpa; 3708 3709 return (error); 3710 } 3711 3712 int 3713 bus_mem_add_mapping(bus_addr_t bpa, bus_size_t size, int flags, 3714 bus_space_handle_t *bshp) 3715 { 3716 paddr_t pa, endpa; 3717 vaddr_t va; 3718 bus_size_t map_size; 3719 int pmap_flags = PMAP_NOCACHE; 3720 3721 pa = trunc_page(bpa); 3722 endpa = round_page(bpa + size); 3723 3724 #ifdef DIAGNOSTIC 3725 if (endpa <= pa && endpa != 0) 3726 panic("bus_mem_add_mapping: overflow"); 3727 #endif 3728 3729 map_size = endpa - pa; 3730 3731 va = (vaddr_t)km_alloc(map_size, &kv_any, &kp_none, &kd_nowait); 3732 if (va == 0) 3733 return (ENOMEM); 3734 3735 *bshp = (bus_space_handle_t)(va + (bpa & PGOFSET)); 3736 3737 if (flags & BUS_SPACE_MAP_CACHEABLE) 3738 pmap_flags = 0; 3739 else if (flags & BUS_SPACE_MAP_PREFETCHABLE) 3740 pmap_flags = PMAP_WC; 3741 3742 for (; map_size > 0; 3743 pa += PAGE_SIZE, va += PAGE_SIZE, map_size -= PAGE_SIZE) 3744 pmap_kenter_pa(va, pa | pmap_flags, 3745 PROT_READ | PROT_WRITE); 3746 pmap_update(pmap_kernel()); 3747 3748 return 0; 3749 } 3750 3751 void 3752 bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3753 { 3754 struct extent *ex; 3755 u_long va, endva; 3756 bus_addr_t bpa; 3757 3758 /* 3759 * Find the correct extent and bus physical address. 3760 */ 3761 if (t == I386_BUS_SPACE_IO) { 3762 ex = ioport_ex; 3763 bpa = bsh; 3764 } else if (t == I386_BUS_SPACE_MEM) { 3765 ex = iomem_ex; 3766 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3767 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3768 goto ok; 3769 3770 va = trunc_page(bsh); 3771 endva = round_page(bsh + size); 3772 3773 #ifdef DIAGNOSTIC 3774 if (endva <= va) 3775 panic("bus_space_unmap: overflow"); 3776 #endif 3777 3778 (void) pmap_extract(pmap_kernel(), va, &bpa); 3779 bpa += (bsh & PGOFSET); 3780 3781 pmap_kremove(va, endva - va); 3782 pmap_update(pmap_kernel()); 3783 3784 /* 3785 * Free the kernel virtual mapping. 3786 */ 3787 km_free((void *)va, endva - va, &kv_any, &kp_none); 3788 } else 3789 panic("bus_space_unmap: bad bus space tag"); 3790 3791 ok: 3792 if (extent_free(ex, bpa, size, 3793 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3794 printf("bus_space_unmap: %s 0x%lx, size 0x%lx\n", 3795 (t == I386_BUS_SPACE_IO) ? "port" : "pa", bpa, size); 3796 printf("bus_space_unmap: can't free region\n"); 3797 } 3798 } 3799 3800 void 3801 _bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size, 3802 bus_addr_t *adrp) 3803 { 3804 u_long va, endva; 3805 bus_addr_t bpa; 3806 3807 /* 3808 * Find the correct bus physical address. 3809 */ 3810 if (t == I386_BUS_SPACE_IO) { 3811 bpa = bsh; 3812 } else if (t == I386_BUS_SPACE_MEM) { 3813 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3814 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3815 goto ok; 3816 3817 va = trunc_page(bsh); 3818 endva = round_page(bsh + size); 3819 3820 #ifdef DIAGNOSTIC 3821 if (endva <= va) 3822 panic("_bus_space_unmap: overflow"); 3823 #endif 3824 3825 (void) pmap_extract(pmap_kernel(), va, &bpa); 3826 bpa += (bsh & PGOFSET); 3827 3828 pmap_kremove(va, endva - va); 3829 pmap_update(pmap_kernel()); 3830 3831 /* 3832 * Free the kernel virtual mapping. 3833 */ 3834 km_free((void *)va, endva - va, &kv_any, &kp_none); 3835 } else 3836 panic("bus_space_unmap: bad bus space tag"); 3837 3838 ok: 3839 if (adrp != NULL) 3840 *adrp = bpa; 3841 } 3842 3843 void 3844 bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3845 { 3846 3847 /* bus_space_unmap() does all that we need to do. */ 3848 bus_space_unmap(t, bsh, size); 3849 } 3850 3851 int 3852 bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh, 3853 bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) 3854 { 3855 *nbshp = bsh + offset; 3856 return (0); 3857 } 3858 3859 paddr_t 3860 bus_space_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off, int prot, int flags) 3861 { 3862 /* Can't mmap I/O space. */ 3863 if (t == I386_BUS_SPACE_IO) 3864 return (-1); 3865 3866 return (addr + off); 3867 } 3868 3869 #ifdef DIAGNOSTIC 3870 void 3871 splassert_check(int wantipl, const char *func) 3872 { 3873 if (lapic_tpr < wantipl) 3874 splassert_fail(wantipl, lapic_tpr, func); 3875 if (wantipl == IPL_NONE && curcpu()->ci_idepth != 0) 3876 splassert_fail(-1, curcpu()->ci_idepth, func); 3877 } 3878 #endif 3879 3880 int 3881 copyin32(const uint32_t *uaddr, uint32_t *kaddr) 3882 { 3883 if ((vaddr_t)uaddr & 0x3) 3884 return EFAULT; 3885 3886 /* copyin(9) is atomic */ 3887 return copyin(uaddr, kaddr, sizeof(uint32_t)); 3888 } 3889 3890 /* 3891 * True if the system has any non-level interrupts which are shared 3892 * on the same pin. 3893 */ 3894 int intr_shared_edge; 3895 3896 /* 3897 * Software interrupt registration 3898 * 3899 * We hand-code this to ensure that it's atomic. 3900 */ 3901 void 3902 softintr(int sir) 3903 { 3904 struct cpu_info *ci = curcpu(); 3905 3906 __asm volatile("orl %1, %0" : 3907 "=m" (ci->ci_ipending) : "ir" (1 << sir)); 3908 } 3909 3910 /* 3911 * Raise current interrupt priority level, and return the old one. 3912 */ 3913 int 3914 splraise(int ncpl) 3915 { 3916 int ocpl; 3917 3918 KASSERT(ncpl >= IPL_NONE); 3919 3920 _SPLRAISE(ocpl, ncpl); 3921 return (ocpl); 3922 } 3923 3924 /* 3925 * Restore an old interrupt priority level. If any thereby unmasked 3926 * interrupts are pending, call Xspllower() to process them. 3927 */ 3928 void 3929 splx(int ncpl) 3930 { 3931 _SPLX(ncpl); 3932 } 3933 3934 /* 3935 * Same as splx(), but we return the old value of spl, for the 3936 * benefit of some splsoftclock() callers. 3937 */ 3938 int 3939 spllower(int ncpl) 3940 { 3941 int ocpl = lapic_tpr; 3942 3943 splx(ncpl); 3944 return (ocpl); 3945 } 3946 3947 int 3948 intr_handler(struct intrframe *frame, struct intrhand *ih) 3949 { 3950 int rc; 3951 #ifdef MULTIPROCESSOR 3952 int need_lock; 3953 3954 if (ih->ih_flags & IPL_MPSAFE) 3955 need_lock = 0; 3956 else 3957 need_lock = 1; 3958 3959 if (need_lock) 3960 __mp_lock(&kernel_lock); 3961 #endif 3962 rc = (*ih->ih_fun)(ih->ih_arg ? ih->ih_arg : frame); 3963 #ifdef MULTIPROCESSOR 3964 if (need_lock) 3965 __mp_unlock(&kernel_lock); 3966 #endif 3967 return rc; 3968 } 3969 3970 void 3971 intr_barrier(void *ih) 3972 { 3973 sched_barrier(NULL); 3974 } 3975 3976 #ifdef SUSPEND 3977 3978 void 3979 intr_enable_wakeup(void) 3980 { 3981 } 3982 3983 void 3984 intr_disable_wakeup(void) 3985 { 3986 } 3987 3988 #endif 3989 3990 unsigned int 3991 cpu_rnd_messybits(void) 3992 { 3993 struct timespec ts; 3994 3995 nanotime(&ts); 3996 return (ts.tv_nsec ^ (ts.tv_sec << 20)); 3997 } 3998 3999 int i386_delay_quality; 4000 4001 void 4002 delay_init(void(*fn)(int), int fn_quality) 4003 { 4004 if (fn_quality > i386_delay_quality) { 4005 delay_func = fn; 4006 i386_delay_quality = fn_quality; 4007 } 4008 } 4009 4010 void 4011 delay_fini(void (*fn)(int)) 4012 { 4013 if (delay_func == fn) { 4014 delay_func = i8254_delay; 4015 i386_delay_quality = 0; 4016 } 4017 } 4018