xref: /netbsd-src/sys/dev/pci/qat/qat_hw15reg.h (revision 87bee1d0282418fa954c1037956c296d640039b9)
1 /*	$NetBSD: qat_hw15reg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
2 
3 /*
4  * Copyright (c) 2019 Internet Initiative Japan, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26  * POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 /*
30  *   Copyright(c) 2007-2013 Intel Corporation. All rights reserved.
31  *
32  *   Redistribution and use in source and binary forms, with or without
33  *   modification, are permitted provided that the following conditions
34  *   are met:
35  *
36  *     * Redistributions of source code must retain the above copyright
37  *       notice, this list of conditions and the following disclaimer.
38  *     * Redistributions in binary form must reproduce the above copyright
39  *       notice, this list of conditions and the following disclaimer in
40  *       the documentation and/or other materials provided with the
41  *       distribution.
42  *     * Neither the name of Intel Corporation nor the names of its
43  *       contributors may be used to endorse or promote products derived
44  *       from this software without specific prior written permission.
45  *
46  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
47  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
48  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
49  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
50  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
51  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
52  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
56  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57  */
58 
59 #ifndef _DEV_PCI_QAT_HW15REG_H_
60 #define _DEV_PCI_QAT_HW15REG_H_
61 
62 /* Default message size in bytes */
63 #define FW_REQ_DEFAULT_SZ_HW15		64
64 #define FW_RESP_DEFAULT_SZ_HW15		64
65 
66 #define ADMIN_RING_SIZE		256
67 #define RING_NUM_ADMIN_TX	0
68 #define RING_NUM_ADMIN_RX	1
69 
70 /* -------------------------------------------------------------------------- */
71 /* accel */
72 
73 #define ARCH_IF_FLAGS_VALID_FLAG		__BIT(7)
74 #define ARCH_IF_FLAGS_RESP_RING_TYPE		__BITS(4, 3)
75 #define  ARCH_IF_FLAGS_RESP_RING_TYPE_SHIFT	3
76 #define  ARCH_IF_FLAGS_RESP_RING_TYPE_SCRATCH	(0 << ARCH_IF_FLAGS_RESP_RING_TYPE_SHIFT)
77 #define  ARCH_IF_FLAGS_RESP_RING_TYPE_NN	(1 << ARCH_IF_FLAGS_RESP_RING_TYPE_SHIFT)
78 #define  ARCH_IF_FLAGS_RESP_RING_TYPE_ET	(2 << ARCH_IF_FLAGS_RESP_RING_TYPE_SHIFT)
79 #define ARCH_IF_FLAGS_RESP_TYPE			__BITS(2, 0)
80 #define  ARCH_IF_FLAGS_RESP_TYPE_SHIFT		0
81 #define   ARCH_IF_FLAGS_RESP_TYPE_A		(0 << ARCH_IF_FLAGS_RESP_TYPE_SHIFT)
82 #define   ARCH_IF_FLAGS_RESP_TYPE_B		(1 << ARCH_IF_FLAGS_RESP_TYPE_SHIFT)
83 #define   ARCH_IF_FLAGS_RESP_TYPE_C		(2 << ARCH_IF_FLAGS_RESP_TYPE_SHIFT)
84 #define   ARCH_IF_FLAGS_RESP_TYPE_S		(3 << ARCH_IF_FLAGS_RESP_TYPE_SHIFT)
85 
86 enum arch_if_req {
87 	ARCH_IF_REQ_NULL,		/* NULL request type */
88 
89 	/* QAT-AE Service Request Type IDs - 01 to 20 */
90 	ARCH_IF_REQ_QAT_FW_INIT,	/* QAT-FW Initialization Request */
91 	ARCH_IF_REQ_QAT_FW_ADMIN,	/* QAT-FW Administration Request */
92 	ARCH_IF_REQ_QAT_FW_PKE,		/* QAT-FW PKE Request */
93 	ARCH_IF_REQ_QAT_FW_LA,		/* QAT-FW Lookaside Request */
94 	ARCH_IF_REQ_QAT_FW_IPSEC,	/* QAT-FW IPSec Request */
95 	ARCH_IF_REQ_QAT_FW_SSL,		/* QAT-FW SSL Request */
96 	ARCH_IF_REQ_QAT_FW_DMA,		/* QAT-FW DMA Request */
97 	ARCH_IF_REQ_QAT_FW_STORAGE,	/* QAT-FW Storage Request */
98 	ARCH_IF_REQ_QAT_FW_COMPRESS,	/* QAT-FW Compression Request */
99 	ARCH_IF_REQ_QAT_FW_PATMATCH,	/* QAT-FW Pattern Matching Request */
100 
101 	/* IP Service (Range Match and Exception) Blocks Request Type IDs 21 - 30 */
102 	ARCH_IF_REQ_RM_FLOW_MISS = 21,	/* RM flow miss request */
103 	ARCH_IF_REQ_RM_FLOW_TIMER_EXP,	/* RM flow timer exp Request */
104 	ARCH_IF_REQ_IP_SERVICES_RFC_LOOKUP_UPDATE, /* RFC Lookup request */
105 	ARCH_IF_REQ_IP_SERVICES_CONFIG_UPDATE,	/* Config Update request */
106 	ARCH_IF_REQ_IP_SERVICES_FCT_CONFIG,	/* FCT Config request */
107 	ARCH_IF_REQ_IP_SERVICES_NEXT_HOP_TIMER_EXPIRY, /* NH Timer expiry request */
108 	ARCH_IF_REQ_IP_SERVICES_EXCEPTION,	/* Exception processign request */
109 	ARCH_IF_REQ_IP_SERVICES_STACK_DRIVER,	/* Send to SD request */
110 	ARCH_IF_REQ_IP_SERVICES_ACTION_HANDLER,	/* Send to AH request */
111 	ARCH_IF_REQ_IP_SERVICES_EVENT_HANDLER,	/* Send to EH request */
112 	ARCH_IF_REQ_DELIMITER			/* End delimiter */
113 };
114 
115 struct arch_if_req_hdr {
116 	uint8_t resp_dest_id;
117 	/* Opaque identifier passed from the request to response to allow
118 	 * response handler perform any further processing */
119 	uint8_t resp_pipe_id;
120 	/* Response pipe to write the response associated with this request to */
121 	uint8_t req_type;
122 	/* Definition of the service described by the request */
123 	uint8_t flags;
124 	/* Request and response control flags */
125 };
126 
127 struct arch_if_resp_hdr {
128 	uint8_t dest_id;
129 	/* Opaque identifier passed from the request to response to allow
130 	 * response handler perform any further processing */
131 	uint8_t serv_id;
132 	/* Definition of the service id generating the response */
133 	uint8_t resp_type;
134 	/* Definition of the service described by the request */
135 	uint8_t flags;
136 	/* Request and response control flags */
137 };
138 
139 struct fw_comn_req_hdr {
140 	struct arch_if_req_hdr arch_if;
141 	/* Common arch fields used by all ICP interface requests. Remaining
142 	 * fields are specific to the common QAT FW service. */
143 	uint16_t comn_req_flags;
144 	/* Flags used to describe common processing required by the request and
145 	 * the meaning of parameters in it i.e. differentiating between a buffer
146 	 * descriptor and a flat buffer pointer in the source (src) and destination
147 	 * (dest) data address fields. Full definition of the fields is given
148 	 * below */
149 	uint8_t content_desc_params_sz;
150 	/* Size of the content descriptor parameters in quad words. These
151 	 * parameters describe the session setup configuration info for the
152 	 * slices that this request relies upon i.e. the configuration word and
153 	 * cipher key needed by the cipher slice if there is a request for cipher
154 	 * processing. The format of the parameters are contained in icp_qat_hw.h
155 	 * and vary depending on the algorithm and mode being used. It is the
156 	 * clients responsibility to ensure this structure is correctly packed */
157 	uint8_t content_desc_hdr_sz;
158 	/* Size of the content descriptor header in quad words. This information
159 	 * is read into the QAT AE xfr registers */
160 	uint64_t content_desc_addr;
161 	/* Address of the content descriptor containing both the content header
162 	 * the size of which is defined by content_desc_hdr_sz followed by the
163 	 * content parameters whose size is described bycontent_desc_params_sz
164 	 */
165 };
166 
167 struct fw_comn_req_mid {
168 	uint64_t opaque_data;
169 	/* Opaque data passed unmodified from the request to response messages
170 	 * by firmware (fw) */
171 	uint64_t src_data_addr;
172 	/* Generic definition of the source data supplied to the QAT AE. The
173 	 * common flags are used to further describe the attributes of this
174 	 * field */
175 	uint64_t dest_data_addr;
176 	/* Generic definition of the destination data supplied to the QAT AE.
177 	 * The common flags are used to further describe the attributes of this
178 	 * field */
179 };
180 
181 union fw_comn_req_ftr {
182 	uint64_t next_request_addr;
183 	/* Overloaded field, for stateful requests, this field is the pointer to
184 	   next request descriptor */
185 	struct {
186 		uint32_t src_length;
187 		/* Length of source flat buffer incase src buffer type is flat */
188 		uint32_t dst_length;
189 		/* Length of source flat buffer incase dst buffer type is flat */
190 	} s;
191 };
192 
193 union fw_comn_error {
194 	struct {
195 		uint8_t resrvd;		/* 8 bit reserved field */
196 		uint8_t comn_err_code;	/**< 8 bit common error code */
197 	} s;
198 	/* Structure which is used for non-compression responses */
199 
200 	struct {
201 		uint8_t xlat_err_code;	/* 8 bit translator error field */
202 		uint8_t cmp_err_code;	/* 8 bit compression error field */
203 	} s1;
204 	/* Structure which is used for compression responses */
205 };
206 
207 struct fw_comn_resp_hdr {
208 	struct arch_if_resp_hdr arch_if;
209 	/* Common arch fields used by all ICP interface response messages. The
210 	 * remaining fields are specific to the QAT FW */
211 	union fw_comn_error comn_error;
212 	/* This field is overloaded to allow for one 8 bit common error field
213 	 * or two 8 bit error fields from compression and translator  */
214 	uint8_t comn_status;
215 	/* Status field which specifies which slice(s) report an error */
216 	uint8_t serv_cmd_id;
217 	/* For services that define multiple commands this field represents the
218 	 * command. If only 1 command is supported then this field will be 0 */
219 	uint64_t opaque_data;
220 	/* Opaque data passed from the request to the response message */
221 };
222 
223 
224 #define RING_MASK_TABLE_ENTRY_LOG_SZ			(5)
225 
226 #define FW_INIT_RING_MASK_SET(table, id)			\
227 		table->firt_ring_mask[id >> RING_MASK_TABLE_ENTRY_LOG_SZ] =\
228 		table->firt_ring_mask[id >> RING_MASK_TABLE_ENTRY_LOG_SZ] | \
229 		(1 << (id & 0x1f))
230 
231 struct fw_init_ring_params {
232 	uint8_t firp_curr_weight;	/* Current ring weight (working copy),
233 					 * has to be equal to init_weight */
234 	uint8_t firp_init_weight;	/* Initial ring weight: -1 ... 0
235 					 * -1 is equal to FF, -2 is equal to FE,
236 					 * the weighting uses negative logic
237 					 * where FF means poll the ring once,
238 					 * -2 is poll the ring twice,
239 					 * 0 is poll the ring 255 times */
240 	uint8_t firp_ring_pvl;		/* Ring Privilege Level. */
241 	uint8_t firp_reserved;		/* Reserved field which must be set
242 					 * to 0 by the client */
243 };
244 
245 #define INIT_RING_TABLE_SZ		128
246 #define INIT_RING_TABLE_LW_SZ		4
247 
248 struct fw_init_ring_table {
249 	struct fw_init_ring_params firt_bulk_rings[INIT_RING_TABLE_SZ];
250 					/* array of ring parameters */
251 	uint32_t firt_ring_mask[INIT_RING_TABLE_LW_SZ];
252 					/* Structure to hold the bit masks for
253 					 * 128 rings. */
254 };
255 
256 struct fw_init_set_ae_info_hdr {
257 	uint16_t init_slice_mask;	/* Init time flags to set the ownership of the slices */
258 	uint16_t resrvd;		/* Reserved field and must be set to 0 by the client */
259 	uint8_t init_qat_id;		/* Init time qat id described in the request */
260 	uint8_t init_ring_cluster_id;	/* Init time ring cluster Id */
261 	uint8_t init_trgt_id;		/* Init time target AE id described in the request */
262 	uint8_t init_cmd_id;		/* Init time command that is described in the request */
263 };
264 
265 struct fw_init_set_ae_info {
266 	uint64_t init_shram_mask;	/* Init time shram mask to set the page ownership in page pool of AE*/
267 	uint64_t resrvd;		/* Reserved field and must be set to 0 by the client */
268 };
269 
270 struct fw_init_set_ring_info_hdr {
271 	uint32_t resrvd;		/* Reserved field and must be set to 0 by the client */
272 	uint16_t init_ring_tbl_sz;	/* Init time information to state size of the ring table */
273 	uint8_t init_trgt_id;		/* Init time target AE id described in the request */
274 	uint8_t init_cmd_id;		/* Init time command that is described in the request */
275 };
276 
277 struct fw_init_set_ring_info {
278 	uint64_t init_ring_table_ptr;	/* Pointer to weighting information for 128 rings  */
279 	uint64_t resrvd;		/* Reserved field and must be set to 0 by the client */
280 };
281 
282 struct fw_init_trng_hdr {
283 	uint32_t resrvd;	/* Reserved field and must be set to 0 by the client */
284 	union {
285 		uint8_t resrvd;	/* Reserved field set to if cmd type is trng disable */
286 		uint8_t init_trng_cfg_sz;	/* Size of the trng config word in QW*/
287 	} u;
288 	uint8_t resrvd1;	/* Reserved field and must be set to 0 by the client */
289 	uint8_t init_trgt_id;	/* Init time target AE id described in the request */
290 	uint8_t init_cmd_id;	/* Init time command that is described in the request */
291 };
292 
293 struct fw_init_trng {
294 	union {
295 		uint64_t resrvd;	/* Reserved field set to 0 if cmd type is trng disable */
296 		uint64_t init_trng_cfg_ptr;	/* Pointer to TRNG Slice config word*/
297 	} u;
298 	uint64_t resrvd;		/* Reserved field and must be set to 0 by the client */
299 };
300 
301 struct fw_init_req {
302 	struct fw_comn_req_hdr comn_hdr;	/* Common request header */
303 	union {
304 		struct fw_init_set_ae_info_hdr set_ae_info;
305 		/* INIT SET_AE_INFO request header structure */
306 		struct fw_init_set_ring_info_hdr set_ring_info;
307 		/* INIT SET_RING_INFO request header structure */
308 		struct fw_init_trng_hdr init_trng;
309 		/* INIT TRNG ENABLE/DISABLE request header structure */
310 	} u;
311 	struct fw_comn_req_mid comn_mid;	/* Common request middle section */
312 	union {
313 		struct fw_init_set_ae_info set_ae_info;
314 		/* INIT SET_AE_INFO request data structure */
315 		struct fw_init_set_ring_info set_ring_info;
316 		/* INIT SET_RING_INFO request data structure */
317 		struct fw_init_trng init_trng;
318 		/* INIT TRNG ENABLE/DISABLE request data structure */
319 	} u1;
320 };
321 
322 enum fw_init_cmd_id {
323 	FW_INIT_CMD_SET_AE_INFO,	/* Setup AE Info command type */
324 	FW_INIT_CMD_SET_RING_INFO,	/* Setup Ring Info command type */
325 	FW_INIT_CMD_TRNG_ENABLE,	/* TRNG Enable command type */
326 	FW_INIT_CMD_TRNG_DISABLE,	/* TRNG Disable command type */
327 	FW_INIT_CMD_DELIMITER		/* Delimiter type */
328 };
329 
330 struct fw_init_resp {
331 	struct fw_comn_resp_hdr comn_resp;	/* Common interface response */
332 	uint8_t resrvd[64 - sizeof(struct fw_comn_resp_hdr)];
333 	/* XXX FW_RESP_DEFAULT_SZ_HW15 */
334 	/* Reserved padding out to the default response size */
335 };
336 
337 
338 /* -------------------------------------------------------------------------- */
339 /* look aside */
340 
341 #define COMN_REQ_ORD				UINT16_C(0x8000)
342 #define  COMN_REQ_ORD_SHIFT			15
343 #define   COMN_REQ_ORD_NONE			(0 << COMN_REQ_ORD_SHIFT)
344 #define   COMN_REQ_ORD_STRICT			(1 << COMN_REQ_ORD_SHIFT)
345 #define COMN_REQ_PTR_TYPE			UINT16_C(0x4000)
346 #define  COMN_REQ_PTR_TYPE_SHIFT		14
347 #define   COMN_REQ_PTR_TYPE_FLAT		(0 << COMN_REQ_PTR_TYPE_SHIFT)
348 #define   COMN_REQ_PTR_TYPE_SGL			(1 << COMN_REQ_PTR_TYPE_SHIFT)
349 #define COMN_REQ_RESERVED			UINT16_C(0x2000)
350 #define COMN_REQ_SHRAM_INIT			UINT16_C(0x1000)
351 #define  COMN_REQ_SHRAM_INIT_SHIFT		12
352 #define  COMN_REQ_SHRAM_INIT_REQUIRED		(1 << COMN_REQ_SHRAM_INIT_SHIFT)
353 #define COMN_REQ_REGEX_SLICE			UINT16_C(0x0800)
354 #define  COMN_REQ_REGEX_SLICE_SHIFT		11
355 #define   COMN_REQ_REGEX_SLICE_REQUIRED		(1 << COMN_REQ_REGEX_SLICE_SHIFT)
356 #define COMN_REQ_XLAT_SLICE			UINT16_C(0x0400)
357 #define  COMN_REQ_XLAT_SLICE_SHIFT		10
358 #define   COMN_REQ_XLAT_SLICE_REQUIRED		(1 << COMN_REQ_XLAT_SLICE_SHIFT)
359 #define COMN_REQ_CPR_SLICE			UINT16_C(0x0200)
360 #define  COMN_REQ_CPR_SLICE_SHIFT		9
361 #define   COMN_REQ_CPR_SLICE_REQUIRED		(1 << COMN_REQ_CPR_SLICE_SHIFT)
362 #define COMN_REQ_BULK_SLICE			UINT16_C(0x0100)
363 #define  COMN_REQ_BULK_SLICE_SHIFT		8
364 #define   COMN_REQ_BULK_SLICE_REQUIRED		(1 << COMN_REQ_BULK_SLICE_SHIFT)
365 #define COMN_REQ_STORAGE_SLICE			UINT16_C(0x0080)
366 #define  COMN_REQ_STORAGE_SLICE_SHIFT		7
367 #define   COMN_REQ_STORAGE_SLICE_REQUIRED	(1 << COMN_REQ_STORAGE_SLICE_SHIFT)
368 #define COMN_REQ_RND_SLICE			UINT16_C(0x0040)
369 #define  COMN_REQ_RND_SLICE_SHIFT		6
370 #define   COMN_REQ_RND_SLICE_REQUIRED		(1 << COMN_REQ_RND_SLICE_SHIFT)
371 #define COMN_REQ_PKE1_SLICE			UINT16_C(0x0020)
372 #define  COMN_REQ_PKE1_SLICE_SHIFT		5
373 #define   COMN_REQ_PKE1_SLICE_REQUIRED		(1 << COMN_REQ_PKE1_SLICE_SHIFT)
374 #define COMN_REQ_PKE0_SLICE			UINT16_C(0x0010)
375 #define  COMN_REQ_PKE0_SLICE_SHIFT		4
376 #define   COMN_REQ_PKE0_SLICE_REQUIRED		(1 << COMN_REQ_PKE0_SLICE_SHIFT)
377 #define COMN_REQ_AUTH1_SLICE			UINT16_C(0x0008)
378 #define  COMN_REQ_AUTH1_SLICE_SHIFT		3
379 #define   COMN_REQ_AUTH1_SLICE_REQUIRED		(1 << COMN_REQ_AUTH1_SLICE_SHIFT)
380 #define COMN_REQ_AUTH0_SLICE			UINT16_C(0x0004)
381 #define  COMN_REQ_AUTH0_SLICE_SHIFT		2
382 #define   COMN_REQ_AUTH0_SLICE_REQUIRED		(1 << COMN_REQ_AUTH0_SLICE_SHIFT)
383 #define COMN_REQ_CIPHER1_SLICE			UINT16_C(0x0002)
384 #define  COMN_REQ_CIPHER1_SLICE_SHIFT		1
385 #define   COMN_REQ_CIPHER1_SLICE_REQUIRED	(1 << COMN_REQ_CIPHER1_SLICE_SHIFT)
386 #define COMN_REQ_CIPHER0_SLICE			UINT16_C(0x0001)
387 #define  COMN_REQ_CIPHER0_SLICE_SHIFT		0
388 #define   COMN_REQ_CIPHER0_SLICE_REQUIRED	(1 << COMN_REQ_CIPHER0_SLICE_SHIFT)
389 
390 #define COMN_REQ_CY0_ONLY(shram)			\
391 		COMN_REQ_ORD_STRICT |			\
392 		COMN_REQ_PTR_TYPE_FLAT |		\
393 		(shram) |				\
394 		COMN_REQ_RND_SLICE_REQUIRED | 		\
395 		COMN_REQ_PKE0_SLICE_REQUIRED |		\
396 		COMN_REQ_AUTH0_SLICE_REQUIRED |		\
397 		COMN_REQ_CIPHER0_SLICE_REQUIRED;
398 #define COMN_REQ_CY1_ONLY(shram)			\
399 		COMN_REQ_ORD_STRICT |			\
400 		COMN_REQ_PTR_TYPE_FLAT |		\
401 		(shram) |				\
402 		COMN_REQ_PKE1_SLICE_REQUIRED |		\
403 		COMN_REQ_AUTH1_SLICE_REQUIRED |		\
404 		COMN_REQ_CIPHER1_SLICE_REQUIRED;
405 
406 #define COMN_RESP_CRYPTO_STATUS		__BIT(7)
407 #define COMN_RESP_PKE_STATUS		__BIT(6)
408 #define COMN_RESP_CMP_STATUS		__BIT(5)
409 #define COMN_RESP_XLAT_STATUS		__BIT(4)
410 #define COMN_RESP_PM_STATUS		__BIT(3)
411 #define COMN_RESP_INIT_ADMIN_STATUS	__BIT(2)
412 
413 #define COMN_STATUS_FLAG_OK		0
414 #define COMN_STATUS_FLAG_ERROR		1
415 
416 struct fw_la_ssl_tls_common {
417 	uint8_t out_len;	/* Number of bytes of key material to output. */
418 	uint8_t label_len;	/* Number of bytes of label for SSL and bytes
419 				 * for TLS key generation  */
420 };
421 
422 struct fw_la_mgf_common {
423 	uint8_t hash_len;
424 	/* Number of bytes of hash output by the QAT per iteration */
425 	uint8_t seed_len;
426 	/* Number of bytes of seed provided in src buffer for MGF1 */
427 };
428 
429 struct fw_cipher_hdr {
430 	uint8_t state_sz;
431 	/* State size in quad words of the cipher algorithm used in this session.
432 	 * Set to zero if the algorithm doesnt provide any state */
433 	uint8_t offset;
434 	/* Quad word offset from the content descriptor parameters address i.e.
435 	 * (content_address + (cd_hdr_sz << 3)) to the parameters for the cipher
436 	 * processing */
437 	uint8_t curr_id;
438 	/* Initialised with the cipher slice type */
439 	uint8_t next_id;
440 	/* Set to the next slice to pass the ciphered data through.
441 	 * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
442 	 * anymore slices after cipher */
443 	uint16_t resrvd;
444 	/* Reserved padding byte to bring the struct to the word boundary. MUST be
445 	 * set to 0 */
446 	uint8_t state_padding_sz;
447 	/* State padding size in quad words. Set to 0 if no padding is required. */
448 	uint8_t key_sz;
449 	/* Key size in quad words of the cipher algorithm used in this session */
450 };
451 
452 struct fw_auth_hdr {
453 	uint8_t hash_flags;
454 	/* General flags defining the processing to perform. 0 is normal processing
455 	 * and 1 means there is a nested hash processing loop to go through */
456 	uint8_t offset;
457 	/* Quad word offset from the content descriptor parameters address to the
458 	 * parameters for the auth processing */
459 	uint8_t curr_id;
460 	/* Initialised with the auth slice type */
461 	uint8_t next_id;
462 	/* Set to the next slice to pass data through.
463 	 * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
464 	 * anymore slices after auth */
465 	union {
466 		uint8_t inner_prefix_sz;
467 		/* Size in bytes of the inner prefix data */
468 		uint8_t aad_sz;
469 		/* Size in bytes of padded AAD data to prefix to the packet for CCM
470 		 *  or GCM processing */
471 	} u;
472 
473 	uint8_t outer_prefix_sz;
474 	/* Size in bytes of outer prefix data */
475 	uint8_t final_sz;
476 	/* Size in bytes of digest to be returned to the client if requested */
477 	uint8_t inner_res_sz;
478 	/* Size in bytes of the digest from the inner hash algorithm */
479 	uint8_t resrvd;
480 	/* This field is unused, assumed value is zero. */
481 	uint8_t inner_state1_sz;
482 	/* Size in bytes of inner hash state1 data. Must be a qword multiple */
483 	uint8_t inner_state2_off;
484 	/* Quad word offset from the content descriptor parameters pointer to the
485 	 * inner state2 value */
486 	uint8_t inner_state2_sz;
487 	/* Size in bytes of inner hash state2 data. Must be a qword multiple */
488 	uint8_t outer_config_off;
489 	/* Quad word offset from the content descriptor parameters pointer to the
490 	 * outer configuration information */
491 	uint8_t outer_state1_sz;
492 	/* Size in bytes of the outer state1 value */
493 	uint8_t outer_res_sz;
494 	/* Size in bytes of digest from the outer auth algorithm */
495 	uint8_t outer_prefix_off;
496 	/* Quad word offset from the start of the inner prefix data to the outer
497 	 * prefix information. Should equal the rounded inner prefix size, converted
498 	 * to qwords  */
499 };
500 
501 #define FW_AUTH_HDR_FLAG_DO_NESTED	1
502 #define FW_AUTH_HDR_FLAG_NO_NESTED	0
503 
504 struct fw_la_comn_req {
505 	union {
506 		uint16_t la_flags;
507 		/* Definition of the common LA processing flags used for the
508 		 * bulk processing */
509 		union {
510 			struct fw_la_ssl_tls_common ssl_tls_common;
511 			/* For TLS or SSL Key Generation, this field is
512 			 * overloaded with ssl_tls common information */
513 			struct fw_la_mgf_common mgf_common;
514 			/* For MGF Key Generation, this field is overloaded with
515 			   mgf information */
516 		} u;
517 	} u;
518 
519 	union {
520 		uint8_t resrvd;
521 		/* If not useRd by a request this field must be set to 0 */
522 		uint8_t tls_seed_len;
523 		/* Byte Len of tls seed */
524 		uint8_t req_params_blk_sz;
525 		/* For bulk processing this field represents the request
526 		 * parameters block size */
527 		uint8_t trng_cfg_sz;
528 		/* This field is used for TRNG_ENABLE requests to indicate the
529 		 * size of the TRNG Slice configuration word. Size is in QW's */
530 	} u1;
531 	uint8_t la_cmd_id;
532 	/* Definition of the LA command defined by this request */
533 
534 };
535 
536 #define LA_FLAGS_GCM_IV_LEN_FLAG	__BIT(9)
537 #define LA_FLAGS_PROTO			__BITS(8, 6)
538 #define LA_FLAGS_PROTO_SNOW_3G		__SHIFTIN(4, LA_FLAGS_PROTO)
539 #define LA_FLAGS_PROTO_GCM		__SHIFTIN(2, LA_FLAGS_PROTO)
540 #define LA_FLAGS_PROTO_CCM		__SHIFTIN(1, LA_FLAGS_PROTO)
541 #define LA_FLAGS_PROTO_NO		__SHIFTIN(0, LA_FLAGS_PROTO)
542 #define LA_FLAGS_DIGEST_IN_BUFFER	__BIT(5)
543 #define LA_FLAGS_CMP_AUTH_RES		__BIT(4)
544 #define LA_FLAGS_RET_AUTH_RES		__BIT(3)
545 #define LA_FLAGS_UPDATE_STATE		__BIT(2)
546 #define LA_FLAGS_PARTIAL		__BITS(1, 0)
547 
548 
549 struct fw_la_bulk_req {
550 	struct fw_comn_req_hdr comn_hdr;
551 	/* Common request header */
552 	uint32_t flow_id;
553 	/* Field used by Firmware to limit the number of stateful requests
554 	 * for a session being processed at a given point of time */
555 	struct fw_la_comn_req comn_la_req;
556 	/* Common LA request parameters */
557 	struct fw_comn_req_mid comn_mid;
558 	/* Common request middle section */
559 	uint64_t req_params_addr;
560 	/* Memory address of the request parameters */
561 	union fw_comn_req_ftr comn_ftr;
562 	/* Common request footer */
563 };
564 
565 struct fw_la_resp {
566 	struct fw_comn_resp_hdr comn_resp;
567 	uint8_t resrvd[64 - sizeof(struct fw_comn_resp_hdr)];
568 	/* FW_RESP_DEFAULT_SZ_HW15 */
569 };
570 
571 struct fw_la_cipher_req_params {
572 	uint8_t resrvd;
573 	/* Reserved field and assumed set to 0 */
574 	uint8_t cipher_state_sz;
575 	/* Number of quad words of state data for the cipher algorithm */
576 	uint8_t curr_id;
577 	/* Initialised with the cipher slice type */
578 	uint8_t next_id;
579 	/* Set to the next slice to pass the ciphered data through.
580 	 * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
581 	 * anymore slices after cipher */
582 	uint16_t resrvd1;
583 	/* Reserved field, should be set to zero*/
584 	uint8_t resrvd2;
585 	/* Reserved field, should be set to zero*/
586 	uint8_t next_offset;
587 	/* Offset in bytes to the next request parameter block */
588 	uint32_t cipher_off;
589 	/* Byte offset from the start of packet to the cipher data region */
590 	uint32_t cipher_len;
591 	/* Byte length of the cipher data region */
592 	uint64_t state_address;
593 	/* Flat buffer address in memory of the cipher state information. Unused
594 	 * if the state size is 0 */
595 };
596 
597 struct fw_la_auth_req_params {
598 	uint8_t auth_res_sz;
599 	/* Size in quad words of digest information to validate */
600 	uint8_t hash_state_sz;
601 	/* Number of quad words of inner and outer hash prefix data to process */
602 	uint8_t curr_id;
603 	/* Initialised with the auth slice type */
604 	uint8_t next_id;
605 	/* Set to the next slice to pass the auth data through.
606 	 * Set to ICP_QAT_FW_SLICE_NULL for in-place auth-only requests
607 	 * Set to ICP_QAT_FW_SLICE_DRAM_WR for all other request types
608 	 * if the data is not to go through anymore slices after auth */
609 	union {
610 		uint16_t resrvd;
611 		/* Reserved field should be set to zero for bulk services */
612 		uint16_t tls_secret_len;
613 		/* Length of Secret information for TLS.   */
614 	} u;
615 	uint8_t resrvd;
616 	/* Reserved field, should be set to zero*/
617 	uint8_t next_offset;
618 	/* offset in bytes to the next request parameter block */
619 	uint32_t auth_off;
620 	/* Byte offset from the start of packet to the auth data region */
621 	uint32_t auth_len;
622 	/* Byte length of the auth data region */
623 	union {
624 		uint64_t prefix_addr;
625 		/* Address of the prefix information */
626 		uint64_t aad_addr;
627 		/* Address of the AAD info in DRAM. Used for the CCM and GCM
628 		 * protocols */
629 	} u1;
630 	uint64_t auth_res_address;
631 	/* Address of the auth result information to validate or the location to
632 	 * writeback the digest information to */
633 };
634 
635 
636 #endif
637