1 /* $NetBSD: imx31_icu.c,v 1.8 2022/02/12 03:24:34 riastradh Exp $ */
2 /*-
3 * Copyright (c) 2007 The NetBSD Foundation, Inc.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: imx31_icu.c,v 1.8 2022/02/12 03:24:34 riastradh Exp $");
32
33 #define _INTR_PRIVATE
34
35 #include "locators.h"
36
37 #include <sys/param.h>
38 #include <sys/evcnt.h>
39 #include <sys/device.h>
40 #include <sys/atomic.h>
41
42 #include <uvm/uvm_extern.h>
43
44 #include <machine/intr.h>
45
46 #include <arm/cpu.h>
47 #include <arm/armreg.h>
48 #include <arm/cpufunc.h>
49
50 #include <machine/autoconf.h>
51 #include <sys/bus.h>
52
53 #include <arm/imx/imx31reg.h>
54 #include <arm/imx/imx31var.h>
55
56 static void avic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
57 static void avic_block_irqs(struct pic_softc *, size_t, uint32_t);
58 static void avic_establish_irq(struct pic_softc *, struct intrsource *);
59 static void avic_source_name(struct pic_softc *, int, char *, size_t);
60
61 const struct pic_ops avic_pic_ops = {
62 .pic_unblock_irqs = avic_unblock_irqs,
63 .pic_block_irqs = avic_block_irqs,
64 .pic_establish_irq = avic_establish_irq,
65 .pic_source_name = avic_source_name
66 };
67
68 struct avic_softc {
69 struct pic_softc avic_pic;
70 bus_space_tag_t avic_memt;
71 bus_space_handle_t avic_memh;
72 };
73
74 extern struct cfdriver avic_cd;
75
76 #define INTC_READ(avic, reg) \
77 bus_space_read_4((avic)->avic_memt, (avic)->avic_memh, (reg))
78 #define INTC_WRITE(avic, reg, val) \
79 bus_space_write_4((avic)->avic_memt, (avic)->avic_memh, (reg), (val))
80 #define HW_TO_SW_IPL(ipl) ((ipl) + 1)
81 #define SW_TO_HW_IPL(ipl) ((ipl) - 1)
82
83 void
avic_unblock_irqs(struct pic_softc * pic,size_t irq_base,uint32_t irq_mask)84 avic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
85 {
86 struct avic_softc * const avic = (void *) pic;
87 #if 0
88 if (irq_base == 0)
89 INTC_WRITE(avic, IMX31_INTENABLEL, irq_mask);
90 else
91 INTC_WRITE(avic, IMX31_INTENABLEH, irq_mask);
92 #else
93 uint32_t irq;
94 while ((irq = ffs(irq_mask)) != 0) {
95 irq--;
96 irq_base += irq;
97 irq_mask >>= irq;
98 INTC_WRITE(avic, IMX31_INTENNUM, irq_base);
99 }
100 #endif
101 }
102
103 void
avic_block_irqs(struct pic_softc * pic,size_t irq_base,uint32_t irq_mask)104 avic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
105 {
106 struct avic_softc * const avic = (void *) pic;
107 #if 0
108 if (irq_base == 0)
109 INTC_WRITE(avic, IMX31_INTDISABLEL, irq_mask);
110 else
111 INTC_WRITE(avic, IMX31_INTDISABLEH, irq_mask);
112 #else
113 uint32_t irq;
114 while ((irq = ffs(irq_mask)) != 0) {
115 irq--;
116 irq_base += irq;
117 irq_mask >>= irq;
118 INTC_WRITE(avic, IMX31_INTDISNUM, irq_base);
119 }
120 #endif
121 }
122
123 void
avic_establish_irq(struct pic_softc * pic,struct intrsource * is)124 avic_establish_irq(struct pic_softc *pic, struct intrsource *is)
125 {
126 struct avic_softc * const avic = (void *) pic;
127 bus_addr_t priority_reg;
128 int priority_shift;
129 uint32_t v;
130
131 KASSERT(is->is_irq < 64);
132 KASSERT(is->is_ipl < 16);
133
134 priority_reg = IMX31_NIPRIORITY0 - (is->is_irq >> 3);
135 priority_shift = (is->is_irq & 7) * 4;
136 v = INTC_READ(avic, priority_reg);
137 v &= ~(0x0f << priority_shift);
138 v |= SW_TO_HW_IPL(is->is_ipl) << priority_shift;
139 INTC_WRITE(avic, priority_reg, v);
140
141 KASSERT(is->is_type == IST_LEVEL);
142 }
143
144 static const char * const avic_intr_source_names[] = AVIC_INTR_SOURCE_NAMES;
145
146 void
avic_source_name(struct pic_softc * pic,int irq,char * buf,size_t len)147 avic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len)
148 {
149 strlcpy(buf, avic_intr_source_names[irq], len);
150 }
151
152 void
imx31_irq_handler(void * frame)153 imx31_irq_handler(void *frame)
154 {
155 struct avic_softc * const avic = device_lookup_private(&avic_cd, 0);
156 struct pic_softc * const pic = &avic->avic_pic;
157 int32_t saved_nimask;
158 int32_t irq;
159 int ipl, newipl, oldipl;
160
161 saved_nimask = INTC_READ(avic, IMX31_NIMASK);
162 for (;;) {
163 irq = INTC_READ(avic, IMX31_NIVECSR);
164 if (irq < 0)
165 break;
166 ipl = (int16_t) irq;
167 KASSERT(ipl >= 0);
168 irq >>= 16;
169 KASSERT(irq < 64);
170 KASSERT(pic->pic_sources[irq] != NULL);
171
172 /*
173 * If this interrupt is not above the current spl,
174 * mark it as pending and try again.
175 */
176 newipl = HW_TO_SW_IPL(ipl);
177 if (newipl <= curcpu()->ci_cpl) {
178 pic_mark_pending(pic, irq);
179 continue;
180 }
181
182 /*
183 * Before enabling interrupts, mask out lower priority
184 * interrupts and raise SPL to its equivalent.
185 */
186
187 INTC_WRITE(avic, IMX31_NIMASK, ipl);
188 oldipl = _splraise(newipl);
189 cpsie(I32_bit);
190
191 pic_dispatch(pic->pic_sources[irq], frame);
192
193 /*
194 * Disable interrupts again. Drop SPL. Restore saved
195 * HW interrupt level.
196 */
197 cpsid(I32_bit);
198 splx(oldipl);
199 INTC_WRITE(avic, IMX31_NIMASK, saved_nimask);
200 }
201 }
202
203 static int avic_match(device_t, cfdata_t, void *);
204 static void avic_attach(device_t, device_t, void *);
205
206 CFATTACH_DECL_NEW(avic, sizeof(struct avic_softc),
207 avic_match, avic_attach, NULL, NULL);
208
209 int
avic_match(device_t parent,cfdata_t self,void * aux)210 avic_match(device_t parent, cfdata_t self, void *aux)
211 {
212 struct ahb_attach_args * const ahba = aux;
213
214 if (ahba->ahba_addr != INTC_BASE)
215 return 0;
216
217 return 1;
218 }
219
220 void
avic_attach(device_t parent,device_t self,void * aux)221 avic_attach(device_t parent, device_t self, void *aux)
222 {
223 struct avic_softc * const avic = device_private(self);
224 struct ahb_attach_args * const ahba = aux;
225 int error;
226
227 KASSERT(ahba->ahba_irqbase != AHBCF_IRQBASE_DEFAULT);
228 KASSERT(device_unit(self) == 0);
229
230 if (ahba->ahba_size == AHBCF_SIZE_DEFAULT)
231 ahba->ahba_size = INTC_SIZE;
232
233 avic->avic_memt = ahba->ahba_memt;
234 error = bus_space_map(avic->avic_memt, ahba->ahba_addr, ahba->ahba_size,
235 0, &avic->avic_memh);
236 if (error)
237 panic("avic_attach: failed to map register %#lx-%#lx: %d",
238 ahba->ahba_addr, ahba->ahba_addr + ahba->ahba_size - 1,
239 error);
240
241 avic->avic_pic.pic_ops = &avic_pic_ops;
242 avic->avic_pic.pic_maxsources = 64;
243 strlcpy(avic->avic_pic.pic_name, device_xname(self),
244 sizeof(avic->avic_pic.pic_name));
245
246 pic_add(&avic->avic_pic, ahba->ahba_irqbase);
247 aprint_normal(": interrupts %d..%d\n",
248 ahba->ahba_irqbase, ahba->ahba_irqbase + 63);
249 #if 0
250 softintr_init();
251 #endif
252 }
253