1 /* $NetBSD: nouveau_dispnv50_wndw.c,v 1.2 2021/12/18 23:45:32 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv50_wndw.c,v 1.2 2021/12/18 23:45:32 riastradh Exp $");
26
27 #include "wndw.h"
28 #include "wimm.h"
29
30 #include <nvif/class.h>
31 #include <nvif/cl0002.h>
32
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_fourcc.h>
35
36 #include "nouveau_bo.h"
37
38 static void
nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma * ctxdma)39 nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma)
40 {
41 nvif_object_fini(&ctxdma->object);
42 list_del(&ctxdma->head);
43 kfree(ctxdma);
44 }
45
46 static struct nv50_wndw_ctxdma *
nv50_wndw_ctxdma_new(struct nv50_wndw * wndw,struct nouveau_framebuffer * fb)47 nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct nouveau_framebuffer *fb)
48 {
49 struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
50 struct nv50_wndw_ctxdma *ctxdma;
51 const u8 kind = fb->nvbo->kind;
52 const u32 handle = 0xfb000000 | kind;
53 struct {
54 struct nv_dma_v0 base;
55 union {
56 struct nv50_dma_v0 nv50;
57 struct gf100_dma_v0 gf100;
58 struct gf119_dma_v0 gf119;
59 };
60 } args = {};
61 u32 argc = sizeof(args.base);
62 int ret;
63
64 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) {
65 if (ctxdma->object.handle == handle)
66 return ctxdma;
67 }
68
69 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
70 return ERR_PTR(-ENOMEM);
71 list_add(&ctxdma->head, &wndw->ctxdma.list);
72
73 args.base.target = NV_DMA_V0_TARGET_VRAM;
74 args.base.access = NV_DMA_V0_ACCESS_RDWR;
75 args.base.start = 0;
76 args.base.limit = drm->client.device.info.ram_user - 1;
77
78 if (drm->client.device.info.chipset < 0x80) {
79 args.nv50.part = NV50_DMA_V0_PART_256;
80 argc += sizeof(args.nv50);
81 } else
82 if (drm->client.device.info.chipset < 0xc0) {
83 args.nv50.part = NV50_DMA_V0_PART_256;
84 args.nv50.kind = kind;
85 argc += sizeof(args.nv50);
86 } else
87 if (drm->client.device.info.chipset < 0xd0) {
88 args.gf100.kind = kind;
89 argc += sizeof(args.gf100);
90 } else {
91 args.gf119.page = GF119_DMA_V0_PAGE_LP;
92 args.gf119.kind = kind;
93 argc += sizeof(args.gf119);
94 }
95
96 ret = nvif_object_init(wndw->ctxdma.parent, handle, NV_DMA_IN_MEMORY,
97 &args, argc, &ctxdma->object);
98 if (ret) {
99 nv50_wndw_ctxdma_del(ctxdma);
100 return ERR_PTR(ret);
101 }
102
103 return ctxdma;
104 }
105
106 int
nv50_wndw_wait_armed(struct nv50_wndw * wndw,struct nv50_wndw_atom * asyw)107 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
108 {
109 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
110 if (asyw->set.ntfy) {
111 return wndw->func->ntfy_wait_begun(disp->sync,
112 asyw->ntfy.offset,
113 wndw->wndw.base.device);
114 }
115 return 0;
116 }
117
118 void
nv50_wndw_flush_clr(struct nv50_wndw * wndw,u32 * interlock,bool flush,struct nv50_wndw_atom * asyw)119 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush,
120 struct nv50_wndw_atom *asyw)
121 {
122 union nv50_wndw_atom_mask clr = {
123 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask),
124 };
125 if (clr.sema ) wndw->func-> sema_clr(wndw);
126 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw);
127 if (clr.xlut ) wndw->func-> xlut_clr(wndw);
128 if (clr.csc ) wndw->func-> csc_clr(wndw);
129 if (clr.image) wndw->func->image_clr(wndw);
130
131 interlock[wndw->interlock.type] |= wndw->interlock.data;
132 }
133
134 void
nv50_wndw_flush_set(struct nv50_wndw * wndw,u32 * interlock,struct nv50_wndw_atom * asyw)135 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock,
136 struct nv50_wndw_atom *asyw)
137 {
138 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
139 asyw->image.mode = 0;
140 asyw->image.interval = 1;
141 }
142
143 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
144 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
145 if (asyw->set.image) wndw->func->image_set(wndw, asyw);
146
147 if (asyw->set.xlut ) {
148 if (asyw->ilut) {
149 asyw->xlut.i.offset =
150 nv50_lut_load(&wndw->ilut, asyw->xlut.i.buffer,
151 asyw->ilut, asyw->xlut.i.load);
152 }
153 wndw->func->xlut_set(wndw, asyw);
154 }
155
156 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw);
157 if (asyw->set.scale) wndw->func->scale_set(wndw, asyw);
158 if (asyw->set.blend) wndw->func->blend_set(wndw, asyw);
159 if (asyw->set.point) {
160 if (asyw->set.point = false, asyw->set.mask)
161 interlock[wndw->interlock.type] |= wndw->interlock.data;
162 interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm;
163
164 wndw->immd->point(wndw, asyw);
165 wndw->immd->update(wndw, interlock);
166 } else {
167 interlock[wndw->interlock.type] |= wndw->interlock.data;
168 }
169 }
170
171 void
nv50_wndw_ntfy_enable(struct nv50_wndw * wndw,struct nv50_wndw_atom * asyw)172 nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
173 {
174 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
175
176 asyw->ntfy.handle = wndw->wndw.sync.handle;
177 asyw->ntfy.offset = wndw->ntfy;
178 asyw->ntfy.awaken = false;
179 asyw->set.ntfy = true;
180
181 wndw->func->ntfy_reset(disp->sync, wndw->ntfy);
182 wndw->ntfy ^= 0x10;
183 }
184
185 static void
nv50_wndw_atomic_check_release(struct nv50_wndw * wndw,struct nv50_wndw_atom * asyw,struct nv50_head_atom * asyh)186 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
187 struct nv50_wndw_atom *asyw,
188 struct nv50_head_atom *asyh)
189 {
190 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
191 NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
192 wndw->func->release(wndw, asyw, asyh);
193 asyw->ntfy.handle = 0;
194 asyw->sema.handle = 0;
195 }
196
197 static int
nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom * asyw)198 nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw)
199 {
200 switch (asyw->state.fb->format->format) {
201 case DRM_FORMAT_YUYV: asyw->image.format = 0x28; break;
202 case DRM_FORMAT_UYVY: asyw->image.format = 0x29; break;
203 default:
204 WARN_ON(1);
205 return -EINVAL;
206 }
207 asyw->image.colorspace = 1;
208 return 0;
209 }
210
211 static int
nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom * asyw)212 nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw)
213 {
214 switch (asyw->state.fb->format->format) {
215 case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break;
216 case DRM_FORMAT_XRGB8888 :
217 case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break;
218 case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break;
219 case DRM_FORMAT_XRGB1555 :
220 case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break;
221 case DRM_FORMAT_XBGR2101010 :
222 case DRM_FORMAT_ABGR2101010 : asyw->image.format = 0xd1; break;
223 case DRM_FORMAT_XBGR8888 :
224 case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break;
225 case DRM_FORMAT_XRGB2101010 :
226 case DRM_FORMAT_ARGB2101010 : asyw->image.format = 0xdf; break;
227 case DRM_FORMAT_XBGR16161616F:
228 case DRM_FORMAT_ABGR16161616F: asyw->image.format = 0xca; break;
229 default:
230 return -EINVAL;
231 }
232 asyw->image.colorspace = 0;
233 return 0;
234 }
235
236 static int
nv50_wndw_atomic_check_acquire(struct nv50_wndw * wndw,bool modeset,struct nv50_wndw_atom * armw,struct nv50_wndw_atom * asyw,struct nv50_head_atom * asyh)237 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset,
238 struct nv50_wndw_atom *armw,
239 struct nv50_wndw_atom *asyw,
240 struct nv50_head_atom *asyh)
241 {
242 struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb);
243 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
244 int ret;
245
246 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
247
248 if (asyw->state.fb != armw->state.fb || !armw->visible || modeset) {
249 asyw->image.w = fb->base.width;
250 asyw->image.h = fb->base.height;
251 asyw->image.kind = fb->nvbo->kind;
252
253 ret = nv50_wndw_atomic_check_acquire_rgb(asyw);
254 if (ret) {
255 ret = nv50_wndw_atomic_check_acquire_yuv(asyw);
256 if (ret)
257 return ret;
258 }
259
260 if (asyw->image.kind) {
261 asyw->image.layout = 0;
262 if (drm->client.device.info.chipset >= 0xc0)
263 asyw->image.blockh = fb->nvbo->mode >> 4;
264 else
265 asyw->image.blockh = fb->nvbo->mode;
266 asyw->image.blocks[0] = fb->base.pitches[0] / 64;
267 asyw->image.pitch[0] = 0;
268 } else {
269 asyw->image.layout = 1;
270 asyw->image.blockh = 0;
271 asyw->image.blocks[0] = 0;
272 asyw->image.pitch[0] = fb->base.pitches[0];
273 }
274
275 if (!asyh->state.async_flip)
276 asyw->image.interval = 1;
277 else
278 asyw->image.interval = 0;
279 asyw->image.mode = asyw->image.interval ? 0 : 1;
280 asyw->set.image = wndw->func->image_set != NULL;
281 }
282
283 if (wndw->func->scale_set) {
284 asyw->scale.sx = asyw->state.src_x >> 16;
285 asyw->scale.sy = asyw->state.src_y >> 16;
286 asyw->scale.sw = asyw->state.src_w >> 16;
287 asyw->scale.sh = asyw->state.src_h >> 16;
288 asyw->scale.dw = asyw->state.crtc_w;
289 asyw->scale.dh = asyw->state.crtc_h;
290 if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale)))
291 asyw->set.scale = true;
292 }
293
294 if (wndw->func->blend_set) {
295 asyw->blend.depth = 255 - asyw->state.normalized_zpos;
296 asyw->blend.k1 = asyw->state.alpha >> 8;
297 switch (asyw->state.pixel_blend_mode) {
298 case DRM_MODE_BLEND_PREMULTI:
299 asyw->blend.src_color = 2; /* K1 */
300 asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */
301 break;
302 case DRM_MODE_BLEND_COVERAGE:
303 asyw->blend.src_color = 5; /* K1_TIMES_SRC */
304 asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */
305 break;
306 case DRM_MODE_BLEND_PIXEL_NONE:
307 default:
308 asyw->blend.src_color = 2; /* K1 */
309 asyw->blend.dst_color = 4; /* NEG_K1 */
310 break;
311 }
312 if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend)))
313 asyw->set.blend = true;
314 }
315
316 if (wndw->immd) {
317 asyw->point.x = asyw->state.crtc_x;
318 asyw->point.y = asyw->state.crtc_y;
319 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
320 asyw->set.point = true;
321 }
322
323 return wndw->func->acquire(wndw, asyw, asyh);
324 }
325
326 static int
nv50_wndw_atomic_check_lut(struct nv50_wndw * wndw,struct nv50_wndw_atom * armw,struct nv50_wndw_atom * asyw,struct nv50_head_atom * asyh)327 nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw,
328 struct nv50_wndw_atom *armw,
329 struct nv50_wndw_atom *asyw,
330 struct nv50_head_atom *asyh)
331 {
332 struct drm_property_blob *ilut = asyh->state.degamma_lut;
333
334 /* I8 format without an input LUT makes no sense, and the
335 * HW error-checks for this.
336 *
337 * In order to handle legacy gamma, when there's no input
338 * LUT we need to steal the output LUT and use it instead.
339 */
340 if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) {
341 /* This should be an error, but there's legacy clients
342 * that do a modeset before providing a gamma table.
343 *
344 * We keep the window disabled to avoid angering HW.
345 */
346 if (!(ilut = asyh->state.gamma_lut)) {
347 asyw->visible = false;
348 return 0;
349 }
350
351 if (wndw->func->ilut)
352 asyh->wndw.olut |= BIT(wndw->id);
353 } else {
354 asyh->wndw.olut &= ~BIT(wndw->id);
355 }
356
357 if (!ilut && wndw->func->ilut_identity &&
358 asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F &&
359 asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) {
360 static struct drm_property_blob dummy = {};
361 ilut = &dummy;
362 }
363
364 /* Recalculate LUT state. */
365 memset(&asyw->xlut, 0x00, sizeof(asyw->xlut));
366 if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) {
367 if (!wndw->func->ilut(wndw, asyw, drm_color_lut_size(ilut))) {
368 DRM_DEBUG_KMS("Invalid ilut\n");
369 return -EINVAL;
370 }
371 asyw->xlut.handle = wndw->wndw.vram.handle;
372 asyw->xlut.i.buffer = !asyw->xlut.i.buffer;
373 asyw->set.xlut = true;
374 } else {
375 asyw->clr.xlut = armw->xlut.handle != 0;
376 }
377
378 /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */
379 if (wndw->func->olut_core &&
380 (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle)))
381 asyw->set.xlut = true;
382
383 if (wndw->func->csc && asyh->state.ctm) {
384 const struct drm_color_ctm *ctm = asyh->state.ctm->data;
385 wndw->func->csc(wndw, asyw, ctm);
386 asyw->csc.valid = true;
387 asyw->set.csc = true;
388 } else {
389 asyw->csc.valid = false;
390 asyw->clr.csc = armw->csc.valid;
391 }
392
393 /* Can't do an immediate flip while changing the LUT. */
394 asyh->state.async_flip = false;
395 return 0;
396 }
397
398 static int
nv50_wndw_atomic_check(struct drm_plane * plane,struct drm_plane_state * state)399 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
400 {
401 struct nouveau_drm *drm = nouveau_drm(plane->dev);
402 struct nv50_wndw *wndw = nv50_wndw(plane);
403 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
404 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
405 struct nv50_head_atom *harm = NULL, *asyh = NULL;
406 bool modeset = false;
407 int ret;
408
409 NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
410
411 /* Fetch the assembly state for the head the window will belong to,
412 * and determine whether the window will be visible.
413 */
414 if (asyw->state.crtc) {
415 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
416 if (IS_ERR(asyh))
417 return PTR_ERR(asyh);
418 modeset = drm_atomic_crtc_needs_modeset(&asyh->state);
419 asyw->visible = asyh->state.active;
420 } else {
421 asyw->visible = false;
422 }
423
424 /* Fetch assembly state for the head the window used to belong to. */
425 if (armw->state.crtc) {
426 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
427 if (IS_ERR(harm))
428 return PTR_ERR(harm);
429 }
430
431 /* LUT configuration can potentially cause the window to be disabled. */
432 if (asyw->visible && wndw->func->xlut_set &&
433 (!armw->visible ||
434 asyh->state.color_mgmt_changed ||
435 asyw->state.fb->format->format !=
436 armw->state.fb->format->format)) {
437 ret = nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh);
438 if (ret)
439 return ret;
440 }
441
442 /* Calculate new window state. */
443 if (asyw->visible) {
444 ret = nv50_wndw_atomic_check_acquire(wndw, modeset,
445 armw, asyw, asyh);
446 if (ret)
447 return ret;
448
449 asyh->wndw.mask |= BIT(wndw->id);
450 } else
451 if (armw->visible) {
452 nv50_wndw_atomic_check_release(wndw, asyw, harm);
453 harm->wndw.mask &= ~BIT(wndw->id);
454 } else {
455 return 0;
456 }
457
458 /* Aside from the obvious case where the window is actively being
459 * disabled, we might also need to temporarily disable the window
460 * when performing certain modeset operations.
461 */
462 if (!asyw->visible || modeset) {
463 asyw->clr.ntfy = armw->ntfy.handle != 0;
464 asyw->clr.sema = armw->sema.handle != 0;
465 asyw->clr.xlut = armw->xlut.handle != 0;
466 if (asyw->clr.xlut && asyw->visible)
467 asyw->set.xlut = asyw->xlut.handle != 0;
468 asyw->clr.csc = armw->csc.valid;
469 if (wndw->func->image_clr)
470 asyw->clr.image = armw->image.handle[0] != 0;
471 }
472
473 return 0;
474 }
475
476 static void
nv50_wndw_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * old_state)477 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
478 {
479 struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb);
480 struct nouveau_drm *drm = nouveau_drm(plane->dev);
481
482 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
483 if (!old_state->fb)
484 return;
485
486 nouveau_bo_unpin(fb->nvbo);
487 }
488
489 static int
nv50_wndw_prepare_fb(struct drm_plane * plane,struct drm_plane_state * state)490 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
491 {
492 struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb);
493 struct nouveau_drm *drm = nouveau_drm(plane->dev);
494 struct nv50_wndw *wndw = nv50_wndw(plane);
495 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
496 struct nv50_head_atom *asyh;
497 struct nv50_wndw_ctxdma *ctxdma;
498 int ret;
499
500 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb);
501 if (!asyw->state.fb)
502 return 0;
503
504 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
505 if (ret)
506 return ret;
507
508 if (wndw->ctxdma.parent) {
509 ctxdma = nv50_wndw_ctxdma_new(wndw, fb);
510 if (IS_ERR(ctxdma)) {
511 nouveau_bo_unpin(fb->nvbo);
512 return PTR_ERR(ctxdma);
513 }
514
515 asyw->image.handle[0] = ctxdma->object.handle;
516 }
517
518 asyw->state.fence = dma_resv_get_excl_rcu(fb->nvbo->bo.base.resv);
519 asyw->image.offset[0] = fb->nvbo->bo.offset;
520
521 if (wndw->func->prepare) {
522 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
523 if (IS_ERR(asyh))
524 return PTR_ERR(asyh);
525
526 wndw->func->prepare(wndw, asyh, asyw);
527 }
528
529 return 0;
530 }
531
532 static const struct drm_plane_helper_funcs
533 nv50_wndw_helper = {
534 .prepare_fb = nv50_wndw_prepare_fb,
535 .cleanup_fb = nv50_wndw_cleanup_fb,
536 .atomic_check = nv50_wndw_atomic_check,
537 };
538
539 static void
nv50_wndw_atomic_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)540 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
541 struct drm_plane_state *state)
542 {
543 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
544 __drm_atomic_helper_plane_destroy_state(&asyw->state);
545 kfree(asyw);
546 }
547
548 static struct drm_plane_state *
nv50_wndw_atomic_duplicate_state(struct drm_plane * plane)549 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
550 {
551 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
552 struct nv50_wndw_atom *asyw;
553 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
554 return NULL;
555 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
556 asyw->sema = armw->sema;
557 asyw->ntfy = armw->ntfy;
558 asyw->ilut = NULL;
559 asyw->xlut = armw->xlut;
560 asyw->csc = armw->csc;
561 asyw->image = armw->image;
562 asyw->point = armw->point;
563 asyw->clr.mask = 0;
564 asyw->set.mask = 0;
565 return &asyw->state;
566 }
567
568 static int
nv50_wndw_zpos_default(struct drm_plane * plane)569 nv50_wndw_zpos_default(struct drm_plane *plane)
570 {
571 return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 :
572 (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255;
573 }
574
575 static void
nv50_wndw_reset(struct drm_plane * plane)576 nv50_wndw_reset(struct drm_plane *plane)
577 {
578 struct nv50_wndw_atom *asyw;
579
580 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
581 return;
582
583 if (plane->state)
584 plane->funcs->atomic_destroy_state(plane, plane->state);
585
586 __drm_atomic_helper_plane_reset(plane, &asyw->state);
587 plane->state->zpos = nv50_wndw_zpos_default(plane);
588 plane->state->normalized_zpos = nv50_wndw_zpos_default(plane);
589 }
590
591 static void
nv50_wndw_destroy(struct drm_plane * plane)592 nv50_wndw_destroy(struct drm_plane *plane)
593 {
594 struct nv50_wndw *wndw = nv50_wndw(plane);
595 struct nv50_wndw_ctxdma *ctxdma, *ctxtmp;
596
597 list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) {
598 nv50_wndw_ctxdma_del(ctxdma);
599 }
600
601 nvif_notify_fini(&wndw->notify);
602 nv50_dmac_destroy(&wndw->wimm);
603 nv50_dmac_destroy(&wndw->wndw);
604
605 nv50_lut_fini(&wndw->ilut);
606
607 drm_plane_cleanup(&wndw->plane);
608 kfree(wndw);
609 }
610
611 const struct drm_plane_funcs
612 nv50_wndw = {
613 .update_plane = drm_atomic_helper_update_plane,
614 .disable_plane = drm_atomic_helper_disable_plane,
615 .destroy = nv50_wndw_destroy,
616 .reset = nv50_wndw_reset,
617 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
618 .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
619 };
620
621 static int
nv50_wndw_notify(struct nvif_notify * notify)622 nv50_wndw_notify(struct nvif_notify *notify)
623 {
624 return NVIF_NOTIFY_KEEP;
625 }
626
627 void
nv50_wndw_fini(struct nv50_wndw * wndw)628 nv50_wndw_fini(struct nv50_wndw *wndw)
629 {
630 nvif_notify_put(&wndw->notify);
631 }
632
633 void
nv50_wndw_init(struct nv50_wndw * wndw)634 nv50_wndw_init(struct nv50_wndw *wndw)
635 {
636 nvif_notify_get(&wndw->notify);
637 }
638
639 int
nv50_wndw_new_(const struct nv50_wndw_func * func,struct drm_device * dev,enum drm_plane_type type,const char * name,int index,const u32 * format,u32 heads,enum nv50_disp_interlock_type interlock_type,u32 interlock_data,struct nv50_wndw ** pwndw)640 nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,
641 enum drm_plane_type type, const char *name, int index,
642 const u32 *format, u32 heads,
643 enum nv50_disp_interlock_type interlock_type, u32 interlock_data,
644 struct nv50_wndw **pwndw)
645 {
646 struct nouveau_drm *drm = nouveau_drm(dev);
647 struct nvif_mmu *mmu = &drm->client.mmu;
648 struct nv50_disp *disp = nv50_disp(dev);
649 struct nv50_wndw *wndw;
650 int nformat;
651 int ret;
652
653 if (!(wndw = *pwndw = kzalloc(sizeof(*wndw), GFP_KERNEL)))
654 return -ENOMEM;
655 wndw->func = func;
656 wndw->id = index;
657 wndw->interlock.type = interlock_type;
658 wndw->interlock.data = interlock_data;
659
660 wndw->ctxdma.parent = &wndw->wndw.base.user;
661 INIT_LIST_HEAD(&wndw->ctxdma.list);
662
663 for (nformat = 0; format[nformat]; nformat++);
664
665 ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw,
666 format, nformat, NULL,
667 type, "%s-%d", name, index);
668 if (ret) {
669 kfree(*pwndw);
670 *pwndw = NULL;
671 return ret;
672 }
673
674 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
675
676 if (wndw->func->ilut) {
677 ret = nv50_lut_init(disp, mmu, &wndw->ilut);
678 if (ret)
679 return ret;
680 }
681
682 wndw->notify.func = nv50_wndw_notify;
683
684 if (wndw->func->blend_set) {
685 ret = drm_plane_create_zpos_property(&wndw->plane,
686 nv50_wndw_zpos_default(&wndw->plane), 0, 254);
687 if (ret)
688 return ret;
689
690 ret = drm_plane_create_alpha_property(&wndw->plane);
691 if (ret)
692 return ret;
693
694 ret = drm_plane_create_blend_mode_property(&wndw->plane,
695 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
696 BIT(DRM_MODE_BLEND_PREMULTI) |
697 BIT(DRM_MODE_BLEND_COVERAGE));
698 if (ret)
699 return ret;
700 } else {
701 ret = drm_plane_create_zpos_immutable_property(&wndw->plane,
702 nv50_wndw_zpos_default(&wndw->plane));
703 if (ret)
704 return ret;
705 }
706
707 return 0;
708 }
709
710 int
nv50_wndw_new(struct nouveau_drm * drm,enum drm_plane_type type,int index,struct nv50_wndw ** pwndw)711 nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
712 struct nv50_wndw **pwndw)
713 {
714 struct {
715 s32 oclass;
716 int version;
717 int (*new)(struct nouveau_drm *, enum drm_plane_type,
718 int, s32, struct nv50_wndw **);
719 } wndws[] = {
720 { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
721 { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },
722 {}
723 };
724 struct nv50_disp *disp = nv50_disp(drm->dev);
725 int cid, ret;
726
727 cid = nvif_mclass(&disp->disp->object, wndws);
728 if (cid < 0) {
729 NV_ERROR(drm, "No supported window class\n");
730 return cid;
731 }
732
733 ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw);
734 if (ret)
735 return ret;
736
737 return nv50_wimm_init(drm, *pwndw);
738 }
739