1 /* $NetBSD: nouveau_nvkm_engine_gr_ctxgv100.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_ctxgv100.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $");
26
27 #include "ctxgf100.h"
28
29 /*******************************************************************************
30 * PGRAPH context implementation
31 ******************************************************************************/
32
33 const struct gf100_gr_init
34 gv100_grctx_init_sw_veid_bundle_init_0[] = {
35 { 0x00001000, 64, 0x00100000, 0x00000008 },
36 { 0x00000941, 64, 0x00100000, 0x00000000 },
37 { 0x0000097e, 64, 0x00100000, 0x00000000 },
38 { 0x0000097f, 64, 0x00100000, 0x00000100 },
39 { 0x0000035c, 64, 0x00100000, 0x00000000 },
40 { 0x0000035d, 64, 0x00100000, 0x00000000 },
41 { 0x00000a08, 64, 0x00100000, 0x00000000 },
42 { 0x00000a09, 64, 0x00100000, 0x00000000 },
43 { 0x00000a0a, 64, 0x00100000, 0x00000000 },
44 { 0x00000352, 64, 0x00100000, 0x00000000 },
45 { 0x00000353, 64, 0x00100000, 0x00000000 },
46 { 0x00000358, 64, 0x00100000, 0x00000000 },
47 { 0x00000359, 64, 0x00100000, 0x00000000 },
48 { 0x00000370, 64, 0x00100000, 0x00000000 },
49 { 0x00000371, 64, 0x00100000, 0x00000000 },
50 { 0x00000372, 64, 0x00100000, 0x000fffff },
51 { 0x00000366, 64, 0x00100000, 0x00000000 },
52 { 0x00000367, 64, 0x00100000, 0x00000000 },
53 { 0x00000368, 64, 0x00100000, 0x00000fff },
54 { 0x00000623, 64, 0x00100000, 0x00000000 },
55 { 0x00000624, 64, 0x00100000, 0x00000000 },
56 { 0x0001e100, 1, 0x00000001, 0x02000001 },
57 {}
58 };
59
60 static const struct gf100_gr_pack
61 gv100_grctx_pack_sw_veid_bundle_init[] = {
62 { gv100_grctx_init_sw_veid_bundle_init_0 },
63 {}
64 };
65
66 void
gv100_grctx_generate_attrib(struct gf100_grctx * info)67 gv100_grctx_generate_attrib(struct gf100_grctx *info)
68 {
69 struct gf100_gr *gr = info->gr;
70 const struct gf100_grctx_func *grctx = gr->func->grctx;
71 const u32 alpha = grctx->alpha_nr;
72 const u32 attrib = grctx->attrib_nr;
73 const u32 gfxp = grctx->gfxp_nr;
74 const int s = 12;
75 u32 size = grctx->alpha_nr_max * gr->tpc_total;
76 u32 ao = 0;
77 u32 bo = ao + size;
78 int gpc, ppc, b, n = 0;
79
80 for (gpc = 0; gpc < gr->gpc_nr; gpc++)
81 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max;
82 size = ((size * 0x20) + 127) & ~127;
83 b = mmio_vram(info, size, (1 << s), false);
84
85 mmio_refn(info, 0x418810, 0x80000000, s, b);
86 mmio_refn(info, 0x419848, 0x10000000, s, b);
87 mmio_refn(info, 0x419c2c, 0x10000000, s, b);
88 mmio_refn(info, 0x419e00, 0x00000000, s, b);
89 mmio_wr32(info, 0x419e04, 0x80000000 | size >> 7);
90 mmio_wr32(info, 0x405830, attrib);
91 mmio_wr32(info, 0x40585c, alpha);
92
93 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
94 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
95 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
96 const u32 bs = attrib * gr->ppc_tpc_max;
97 const u32 gs = gfxp * gr->ppc_tpc_max;
98 const u32 u = 0x418ea0 + (n * 0x04);
99 const u32 o = PPC_UNIT(gpc, ppc, 0);
100 if (!(gr->ppc_mask[gpc] & (1 << ppc)))
101 continue;
102 mmio_wr32(info, o + 0xc0, gs);
103 mmio_wr32(info, o + 0xf4, bo);
104 mmio_wr32(info, o + 0xf0, bs);
105 bo += gs;
106 mmio_wr32(info, o + 0xe4, as);
107 mmio_wr32(info, o + 0xf8, ao);
108 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
109 mmio_wr32(info, u, bs);
110 }
111 }
112
113 mmio_wr32(info, 0x4181e4, 0x00000100);
114 mmio_wr32(info, 0x41befc, 0x00000100);
115 }
116
117 void
gv100_grctx_generate_rop_mapping(struct gf100_gr * gr)118 gv100_grctx_generate_rop_mapping(struct gf100_gr *gr)
119 {
120 struct nvkm_device *device = gr->base.engine.subdev.device;
121 u32 data;
122 int i, j;
123
124 /* Pack tile map into register format. */
125 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
126 gr->screen_tile_row_offset);
127 for (i = 0; i < 11; i++) {
128 for (data = 0, j = 0; j < 6; j++)
129 data |= (gr->tile[i * 6 + j] & 0x1f) << (j * 5);
130 nvkm_wr32(device, 0x418b08 + (i * 4), data);
131 nvkm_wr32(device, 0x41bf00 + (i * 4), data);
132 nvkm_wr32(device, 0x40780c + (i * 4), data);
133 }
134
135 /* GPC_BROADCAST.TP_BROADCAST */
136 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
137 gr->screen_tile_row_offset);
138 for (i = 0, j = 1; i < 5; i++, j += 4) {
139 u8 v19 = (1 << (j + 0)) % gr->tpc_total;
140 u8 v20 = (1 << (j + 1)) % gr->tpc_total;
141 u8 v21 = (1 << (j + 2)) % gr->tpc_total;
142 u8 v22 = (1 << (j + 3)) % gr->tpc_total;
143 nvkm_wr32(device, 0x41bfb0 + (i * 4), (v22 << 24) |
144 (v21 << 16) |
145 (v20 << 8) |
146 v19);
147 }
148
149 /* UNK78xx */
150 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
151 gr->screen_tile_row_offset);
152 }
153
154 void
gv100_grctx_generate_r400088(struct gf100_gr * gr,bool on)155 gv100_grctx_generate_r400088(struct gf100_gr *gr, bool on)
156 {
157 struct nvkm_device *device = gr->base.engine.subdev.device;
158 nvkm_mask(device, 0x400088, 0x00060000, on ? 0x00060000 : 0x00000000);
159 }
160
161 static void
gv100_grctx_generate_sm_id(struct gf100_gr * gr,int gpc,int tpc,int sm)162 gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
163 {
164 struct nvkm_device *device = gr->base.engine.subdev.device;
165 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
166 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);
167 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
168 }
169
170 void
gv100_grctx_generate_unkn(struct gf100_gr * gr)171 gv100_grctx_generate_unkn(struct gf100_gr *gr)
172 {
173 struct nvkm_device *device = gr->base.engine.subdev.device;
174 nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
175 nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004);
176 nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000);
177 nvkm_mask(device, 0x405800, 0x08000000, 0x08000000);
178 nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);
179 }
180
181 void
gv100_grctx_unkn88c(struct gf100_gr * gr,bool on)182 gv100_grctx_unkn88c(struct gf100_gr *gr, bool on)
183 {
184 struct nvkm_device *device = gr->base.engine.subdev.device;
185 const u32 mask = 0x00000010, data = on ? mask : 0x00000000;
186 nvkm_mask(device, 0x40988c, mask, data);
187 nvkm_rd32(device, 0x40988c);
188 nvkm_mask(device, 0x41a88c, mask, data);
189 nvkm_rd32(device, 0x41a88c);
190 nvkm_mask(device, 0x408a14, mask, data);
191 nvkm_rd32(device, 0x408a14);
192 }
193
194 const struct gf100_grctx_func
195 gv100_grctx = {
196 .unkn88c = gv100_grctx_unkn88c,
197 .main = gf100_grctx_generate_main,
198 .unkn = gv100_grctx_generate_unkn,
199 .sw_veid_bundle_init = gv100_grctx_pack_sw_veid_bundle_init,
200 .bundle = gm107_grctx_generate_bundle,
201 .bundle_size = 0x3000,
202 .bundle_min_gpm_fifo_depth = 0x180,
203 .bundle_token_limit = 0x1680,
204 .pagepool = gp100_grctx_generate_pagepool,
205 .pagepool_size = 0x20000,
206 .attrib = gv100_grctx_generate_attrib,
207 .attrib_nr_max = 0x6c0,
208 .attrib_nr = 0x480,
209 .alpha_nr_max = 0xc00,
210 .alpha_nr = 0x800,
211 .gfxp_nr = 0xd10,
212 .sm_id = gv100_grctx_generate_sm_id,
213 .rop_mapping = gv100_grctx_generate_rop_mapping,
214 .dist_skip_table = gm200_grctx_generate_dist_skip_table,
215 .r406500 = gm200_grctx_generate_r406500,
216 .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
217 .smid_config = gp100_grctx_generate_smid_config,
218 .r400088 = gv100_grctx_generate_r400088,
219 };
220