1 /* $NetBSD: nouveau_nvkm_engine_gr_ctxgp100.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs <bskeggs@redhat.com>
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_ctxgp100.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $");
28
29 #include "ctxgf100.h"
30
31 #include <subdev/fb.h>
32
33 /*******************************************************************************
34 * PGRAPH context implementation
35 ******************************************************************************/
36
37 void
gp100_grctx_generate_pagepool(struct gf100_grctx * info)38 gp100_grctx_generate_pagepool(struct gf100_grctx *info)
39 {
40 const struct gf100_grctx_func *grctx = info->gr->func->grctx;
41 const int s = 8;
42 const int b = mmio_vram(info, grctx->pagepool_size, (1 << s), true);
43 mmio_refn(info, 0x40800c, 0x00000000, s, b);
44 mmio_wr32(info, 0x408010, 0x8007d800);
45 mmio_refn(info, 0x419004, 0x00000000, s, b);
46 mmio_wr32(info, 0x419008, 0x00000000);
47 }
48
49 static void
gp100_grctx_generate_attrib(struct gf100_grctx * info)50 gp100_grctx_generate_attrib(struct gf100_grctx *info)
51 {
52 struct gf100_gr *gr = info->gr;
53 const struct gf100_grctx_func *grctx = gr->func->grctx;
54 const u32 alpha = grctx->alpha_nr;
55 const u32 attrib = grctx->attrib_nr;
56 const int s = 12;
57 const int max_batches = 0xffff;
58 u32 size = grctx->alpha_nr_max * gr->tpc_total;
59 u32 ao = 0;
60 u32 bo = ao + size;
61 int gpc, ppc, b, n = 0;
62
63 for (gpc = 0; gpc < gr->gpc_nr; gpc++)
64 size += grctx->attrib_nr_max * gr->ppc_nr[gpc] * gr->ppc_tpc_max;
65 size = ((size * 0x20) + 128) & ~127;
66 b = mmio_vram(info, size, (1 << s), false);
67
68 mmio_refn(info, 0x418810, 0x80000000, s, b);
69 mmio_refn(info, 0x419848, 0x10000000, s, b);
70 mmio_refn(info, 0x419c2c, 0x10000000, s, b);
71 mmio_refn(info, 0x419b00, 0x00000000, s, b);
72 mmio_wr32(info, 0x419b04, 0x80000000 | size >> 7);
73 mmio_wr32(info, 0x405830, attrib);
74 mmio_wr32(info, 0x40585c, alpha);
75 mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
76
77 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
78 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
79 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
80 const u32 bs = attrib * gr->ppc_tpc_max;
81 const u32 u = 0x418ea0 + (n * 0x04);
82 const u32 o = PPC_UNIT(gpc, ppc, 0);
83 if (!(gr->ppc_mask[gpc] & (1 << ppc)))
84 continue;
85 mmio_wr32(info, o + 0xc0, bs);
86 mmio_wr32(info, o + 0xf4, bo);
87 mmio_wr32(info, o + 0xf0, bs);
88 bo += grctx->attrib_nr_max * gr->ppc_tpc_max;
89 mmio_wr32(info, o + 0xe4, as);
90 mmio_wr32(info, o + 0xf8, ao);
91 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
92 mmio_wr32(info, u, bs);
93 }
94 }
95
96 mmio_wr32(info, 0x418eec, 0x00000000);
97 mmio_wr32(info, 0x41befc, 0x00000000);
98 }
99
100 void
gp100_grctx_generate_smid_config(struct gf100_gr * gr)101 gp100_grctx_generate_smid_config(struct gf100_gr *gr)
102 {
103 struct nvkm_device *device = gr->base.engine.subdev.device;
104 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
105 u32 dist[TPC_MAX / 4] = {}, gpcs[16] = {};
106 u8 sm, i;
107
108 for (sm = 0; sm < gr->sm_nr; sm++) {
109 const u8 gpc = gr->sm[sm].gpc;
110 const u8 tpc = gr->sm[sm].tpc;
111 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8);
112 gpcs[gpc + (gr->func->gpc_nr * (tpc / 4))] |= sm << ((tpc % 4) * 8);
113 }
114
115 for (i = 0; i < dist_nr; i++)
116 nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]);
117 for (i = 0; i < ARRAY_SIZE(gpcs); i++)
118 nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]);
119 }
120
121 const struct gf100_grctx_func
122 gp100_grctx = {
123 .main = gf100_grctx_generate_main,
124 .unkn = gk104_grctx_generate_unkn,
125 .bundle = gm107_grctx_generate_bundle,
126 .bundle_size = 0x3000,
127 .bundle_min_gpm_fifo_depth = 0x180,
128 .bundle_token_limit = 0x1080,
129 .pagepool = gp100_grctx_generate_pagepool,
130 .pagepool_size = 0x20000,
131 .attrib = gp100_grctx_generate_attrib,
132 .attrib_nr_max = 0x660,
133 .attrib_nr = 0x440,
134 .alpha_nr_max = 0xc00,
135 .alpha_nr = 0x800,
136 .sm_id = gm107_grctx_generate_sm_id,
137 .rop_mapping = gf117_grctx_generate_rop_mapping,
138 .dist_skip_table = gm200_grctx_generate_dist_skip_table,
139 .r406500 = gm200_grctx_generate_r406500,
140 .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
141 .tpc_mask = gm200_grctx_generate_tpc_mask,
142 .smid_config = gp100_grctx_generate_smid_config,
143 .r419a3c = gm200_grctx_generate_r419a3c,
144 };
145