1 /* $NetBSD: nouveau_nvkm_subdev_volt_gm20b.c,v 1.2 2021/12/18 23:45:42 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_volt_gm20b.c,v 1.2 2021/12/18 23:45:42 riastradh Exp $");
27
28 #include "priv.h"
29 #include "gk20a.h"
30
31 #include <core/tegra.h>
32
33 static const struct cvb_coef gm20b_cvb_coef[] = {
34 /* KHz, c0, c1, c2 */
35 /* 76800 */ { 1786666, -85625, 1632 },
36 /* 153600 */ { 1846729, -87525, 1632 },
37 /* 230400 */ { 1910480, -89425, 1632 },
38 /* 307200 */ { 1977920, -91325, 1632 },
39 /* 384000 */ { 2049049, -93215, 1632 },
40 /* 460800 */ { 2122872, -95095, 1632 },
41 /* 537600 */ { 2201331, -96985, 1632 },
42 /* 614400 */ { 2283479, -98885, 1632 },
43 /* 691200 */ { 2369315, -100785, 1632 },
44 /* 768000 */ { 2458841, -102685, 1632 },
45 /* 844800 */ { 2550821, -104555, 1632 },
46 /* 921600 */ { 2647676, -106455, 1632 },
47 };
48
49 static const struct cvb_coef gm20b_na_cvb_coef[] = {
50 /* KHz, c0, c1, c2, c3, c4, c5 */
51 /* 76800 */ { 814294, 8144, -940, 808, -21583, 226 },
52 /* 153600 */ { 856185, 8144, -940, 808, -21583, 226 },
53 /* 230400 */ { 898077, 8144, -940, 808, -21583, 226 },
54 /* 307200 */ { 939968, 8144, -940, 808, -21583, 226 },
55 /* 384000 */ { 981860, 8144, -940, 808, -21583, 226 },
56 /* 460800 */ { 1023751, 8144, -940, 808, -21583, 226 },
57 /* 537600 */ { 1065642, 8144, -940, 808, -21583, 226 },
58 /* 614400 */ { 1107534, 8144, -940, 808, -21583, 226 },
59 /* 691200 */ { 1149425, 8144, -940, 808, -21583, 226 },
60 /* 768000 */ { 1191317, 8144, -940, 808, -21583, 226 },
61 /* 844800 */ { 1233208, 8144, -940, 808, -21583, 226 },
62 /* 921600 */ { 1275100, 8144, -940, 808, -21583, 226 },
63 /* 998400 */ { 1316991, 8144, -940, 808, -21583, 226 },
64 };
65
66 static const u32 speedo_to_vmin[] = {
67 /* 0, 1, 2, 3, 4, */
68 950000, 840000, 818750, 840000, 810000,
69 };
70
71 int
gm20b_volt_new(struct nvkm_device * device,int index,struct nvkm_volt ** pvolt)72 gm20b_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt)
73 {
74 struct nvkm_device_tegra *tdev = device->func->tegra(device);
75 struct gk20a_volt *volt;
76 u32 vmin;
77
78 if (tdev->gpu_speedo_id >= ARRAY_SIZE(speedo_to_vmin)) {
79 nvdev_error(device, "unsupported speedo %d\n",
80 tdev->gpu_speedo_id);
81 return -EINVAL;
82 }
83
84 volt = kzalloc(sizeof(*volt), GFP_KERNEL);
85 if (!volt)
86 return -ENOMEM;
87 *pvolt = &volt->base;
88
89 vmin = speedo_to_vmin[tdev->gpu_speedo_id];
90
91 if (tdev->gpu_speedo_id >= 1)
92 return gk20a_volt_ctor(device, index, gm20b_na_cvb_coef,
93 ARRAY_SIZE(gm20b_na_cvb_coef), vmin, volt);
94 else
95 return gk20a_volt_ctor(device, index, gm20b_cvb_coef,
96 ARRAY_SIZE(gm20b_cvb_coef), vmin, volt);
97 }
98