1 /* $NetBSD: nouveau_nvkm_engine_gr_gm20b.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_gm20b.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $");
26
27 #include "gf100.h"
28 #include "ctxgf100.h"
29
30 #include <core/firmware.h>
31 #include <subdev/acr.h>
32 #include <subdev/timer.h>
33
34 #include <nvfw/flcn.h>
35
36 #include <nvif/class.h>
37
38 void
gm20b_gr_acr_bld_patch(struct nvkm_acr * acr,u32 bld,s64 adjust)39 gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
40 {
41 struct flcn_bl_dmem_desc hdr;
42 u64 addr;
43
44 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
45 addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8);
46 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8);
47 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8);
48 addr = ((u64)hdr.data_dma_base1 << 40 | hdr.data_dma_base << 8);
49 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8);
50 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8);
51 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
52
53 flcn_bl_dmem_desc_dump(&acr->subdev, &hdr);
54 }
55
56 void
gm20b_gr_acr_bld_write(struct nvkm_acr * acr,u32 bld,struct nvkm_acr_lsfw * lsfw)57 gm20b_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
58 struct nvkm_acr_lsfw *lsfw)
59 {
60 const u64 base = lsfw->offset.img + lsfw->app_start_offset;
61 const u64 code = (base + lsfw->app_resident_code_offset) >> 8;
62 const u64 data = (base + lsfw->app_resident_data_offset) >> 8;
63 const struct flcn_bl_dmem_desc hdr = {
64 .ctx_dma = FALCON_DMAIDX_UCODE,
65 .code_dma_base = lower_32_bits(code),
66 .non_sec_code_off = lsfw->app_resident_code_offset,
67 .non_sec_code_size = lsfw->app_resident_code_size,
68 .code_entry_point = lsfw->app_imem_entry,
69 .data_dma_base = lower_32_bits(data),
70 .data_size = lsfw->app_resident_data_size,
71 .code_dma_base1 = upper_32_bits(code),
72 .data_dma_base1 = upper_32_bits(data),
73 };
74
75 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
76 }
77
78 const struct nvkm_acr_lsf_func
79 gm20b_gr_fecs_acr = {
80 .bld_size = sizeof(struct flcn_bl_dmem_desc),
81 .bld_write = gm20b_gr_acr_bld_write,
82 .bld_patch = gm20b_gr_acr_bld_patch,
83 };
84
85 static void
gm20b_gr_init_gpc_mmu(struct gf100_gr * gr)86 gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
87 {
88 struct nvkm_device *device = gr->base.engine.subdev.device;
89 u32 val;
90
91 /* Bypass MMU check for non-secure boot */
92 if (!device->acr) {
93 nvkm_wr32(device, 0x100ce4, 0xffffffff);
94
95 if (nvkm_rd32(device, 0x100ce4) != 0xffffffff)
96 nvdev_warn(device,
97 "cannot bypass secure boot - expect failure soon!\n");
98 }
99
100 val = nvkm_rd32(device, 0x100c80);
101 val &= 0xf000187f;
102 nvkm_wr32(device, 0x418880, val);
103 nvkm_wr32(device, 0x418890, 0);
104 nvkm_wr32(device, 0x418894, 0);
105
106 nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
107 nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
108 nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
109
110 nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800));
111 }
112
113 static void
gm20b_gr_set_hww_esr_report_mask(struct gf100_gr * gr)114 gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
115 {
116 struct nvkm_device *device = gr->base.engine.subdev.device;
117 nvkm_wr32(device, 0x419e44, 0xdffffe);
118 nvkm_wr32(device, 0x419e4c, 0x5);
119 }
120
121 static const struct gf100_gr_func
122 gm20b_gr = {
123 .oneinit_tiles = gm200_gr_oneinit_tiles,
124 .oneinit_sm_id = gm200_gr_oneinit_sm_id,
125 .init = gk20a_gr_init,
126 .init_zcull = gf117_gr_init_zcull,
127 .init_gpc_mmu = gm20b_gr_init_gpc_mmu,
128 .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
129 .trap_mp = gf100_gr_trap_mp,
130 .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask,
131 .rops = gm200_gr_rops,
132 .ppc_nr = 1,
133 .grctx = &gm20b_grctx,
134 .zbc = &gf100_gr_zbc,
135 .sclass = {
136 { -1, -1, FERMI_TWOD_A },
137 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
138 { -1, -1, MAXWELL_B, &gf100_fermi },
139 { -1, -1, MAXWELL_COMPUTE_B },
140 {}
141 }
142 };
143
144 static int
gm20b_gr_load(struct gf100_gr * gr,int ver,const struct gf100_gr_fwif * fwif)145 gm20b_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
146 {
147 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
148 int ret;
149
150 ret = nvkm_acr_lsfw_load_bl_inst_data_sig(subdev, &gr->fecs.falcon,
151 NVKM_ACR_LSF_FECS,
152 "gr/fecs_", ver, fwif->fecs);
153 if (ret)
154 return ret;
155
156
157 if (nvkm_firmware_load_blob(subdev, "gr/", "gpccs_inst", ver,
158 &gr->gpccs.inst) ||
159 nvkm_firmware_load_blob(subdev, "gr/", "gpccs_data", ver,
160 &gr->gpccs.data))
161 return -ENOENT;
162
163 gr->firmware = true;
164
165 return gk20a_gr_load_sw(gr, "gr/", ver);
166 }
167
168 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
169 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_bl.bin");
170 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_inst.bin");
171 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_data.bin");
172 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_sig.bin");
173 MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_inst.bin");
174 MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_data.bin");
175 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_ctx.bin");
176 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_nonctx.bin");
177 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_bundle_init.bin");
178 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin");
179 #endif
180
181 static const struct gf100_gr_fwif
182 gm20b_gr_fwif[] = {
183 { 0, gm20b_gr_load, &gm20b_gr, &gm20b_gr_fecs_acr },
184 {}
185 };
186
187 int
gm20b_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)188 gm20b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
189 {
190 return gf100_gr_new_(gm20b_gr_fwif, device, index, pgr);
191 }
192