1 /* $NetBSD: nouveau_nvkm_subdev_acr_gm20b.c,v 1.2 2021/12/18 23:45:38 riastradh Exp $ */
2
3 /*
4 * Copyright 2019 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_acr_gm20b.c,v 1.2 2021/12/18 23:45:38 riastradh Exp $");
26
27 #include "priv.h"
28
29 #include <core/firmware.h>
30 #include <core/memory.h>
31 #include <subdev/mmu.h>
32 #include <subdev/pmu.h>
33
34 #include <nvfw/acr.h>
35 #include <nvfw/flcn.h>
36
37 int
gm20b_acr_wpr_alloc(struct nvkm_acr * acr,u32 wpr_size)38 gm20b_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size)
39 {
40 struct nvkm_subdev *subdev = &acr->subdev;
41
42 acr->func->wpr_check(acr, &acr->wpr_start, &acr->wpr_end);
43
44 if ((acr->wpr_end - acr->wpr_start) < wpr_size) {
45 nvkm_error(subdev, "WPR image too big for WPR!\n");
46 return -ENOSPC;
47 }
48
49 return nvkm_memory_new(subdev->device, NVKM_MEM_TARGET_INST,
50 wpr_size, 0, true, &acr->wpr);
51 }
52
53 static void
gm20b_acr_load_bld(struct nvkm_acr * acr,struct nvkm_acr_hsf * hsf)54 gm20b_acr_load_bld(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
55 {
56 struct flcn_bl_dmem_desc hsdesc = {
57 .ctx_dma = FALCON_DMAIDX_VIRT,
58 .code_dma_base = hsf->vma->addr >> 8,
59 .non_sec_code_off = hsf->non_sec_addr,
60 .non_sec_code_size = hsf->non_sec_size,
61 .sec_code_off = hsf->sec_addr,
62 .sec_code_size = hsf->sec_size,
63 .code_entry_point = 0,
64 .data_dma_base = (hsf->vma->addr + hsf->data_addr) >> 8,
65 .data_size = hsf->data_size,
66 };
67
68 flcn_bl_dmem_desc_dump(&acr->subdev, &hsdesc);
69
70 nvkm_falcon_load_dmem(hsf->falcon, &hsdesc, 0, sizeof(hsdesc), 0);
71 }
72
73 static int
gm20b_acr_load_load(struct nvkm_acr * acr,struct nvkm_acr_hsfw * hsfw)74 gm20b_acr_load_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw)
75 {
76 struct flcn_acr_desc *desc = (void *)&hsfw->image[hsfw->data_addr];
77
78 desc->ucode_blob_base = nvkm_memory_addr(acr->wpr);
79 desc->ucode_blob_size = nvkm_memory_size(acr->wpr);
80 flcn_acr_desc_dump(&acr->subdev, desc);
81
82 return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->pmu->falcon);
83 }
84
85 const struct nvkm_acr_hsf_func
86 gm20b_acr_load_0 = {
87 .load = gm20b_acr_load_load,
88 .boot = gm200_acr_load_boot,
89 .bld = gm20b_acr_load_bld,
90 };
91
92 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
93 MODULE_FIRMWARE("nvidia/gm20b/acr/bl.bin");
94 MODULE_FIRMWARE("nvidia/gm20b/acr/ucode_load.bin");
95 #endif
96
97 static const struct nvkm_acr_hsf_fwif
98 gm20b_acr_load_fwif[] = {
99 { 0, nvkm_acr_hsfw_load, &gm20b_acr_load_0 },
100 {}
101 };
102
103 static const struct nvkm_acr_func
104 gm20b_acr = {
105 .load = gm20b_acr_load_fwif,
106 .wpr_parse = gm200_acr_wpr_parse,
107 .wpr_layout = gm200_acr_wpr_layout,
108 .wpr_alloc = gm20b_acr_wpr_alloc,
109 .wpr_build = gm200_acr_wpr_build,
110 .wpr_patch = gm200_acr_wpr_patch,
111 .wpr_check = gm200_acr_wpr_check,
112 .init = gm200_acr_init,
113 };
114
115 int
gm20b_acr_load(struct nvkm_acr * acr,int ver,const struct nvkm_acr_fwif * fwif)116 gm20b_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
117 {
118 struct nvkm_subdev *subdev = &acr->subdev;
119 const struct nvkm_acr_hsf_fwif *hsfwif;
120
121 hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad",
122 acr, "acr/bl", "acr/ucode_load", "load");
123 if (IS_ERR(hsfwif))
124 return PTR_ERR(hsfwif);
125
126 return 0;
127 }
128
129 static const struct nvkm_acr_fwif
130 gm20b_acr_fwif[] = {
131 { 0, gm20b_acr_load, &gm20b_acr },
132 {}
133 };
134
135 int
gm20b_acr_new(struct nvkm_device * device,int index,struct nvkm_acr ** pacr)136 gm20b_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr)
137 {
138 return nvkm_acr_new_(gm20b_acr_fwif, device, index, pacr);
139 }
140