1 /* $NetBSD: nouveau_nvkm_engine_fifo_gm107.c,v 1.2 2021/12/18 23:45:35 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_fifo_gm107.c,v 1.2 2021/12/18 23:45:35 riastradh Exp $");
28
29 #include "gk104.h"
30 #include "changk104.h"
31
32 #include <core/gpuobj.h>
33 #include <subdev/fault.h>
34
35 #include <nvif/class.h>
36
37 static void
gm107_fifo_runlist_chan(struct gk104_fifo_chan * chan,struct nvkm_memory * memory,u32 offset)38 gm107_fifo_runlist_chan(struct gk104_fifo_chan *chan,
39 struct nvkm_memory *memory, u32 offset)
40 {
41 nvkm_wo32(memory, offset + 0, chan->base.chid);
42 nvkm_wo32(memory, offset + 4, chan->base.inst->addr >> 12);
43 }
44
45 const struct gk104_fifo_runlist_func
46 gm107_fifo_runlist = {
47 .size = 8,
48 .cgrp = gk110_fifo_runlist_cgrp,
49 .chan = gm107_fifo_runlist_chan,
50 .commit = gk104_fifo_runlist_commit,
51 };
52
53 const struct nvkm_enum
54 gm107_fifo_fault_engine[] = {
55 { 0x01, "DISPLAY" },
56 { 0x02, "CAPTURE" },
57 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
58 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
59 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
60 { 0x06, "SCHED" },
61 { 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO },
62 { 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO },
63 { 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO },
64 { 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO },
65 { 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO },
66 { 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO },
67 { 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO },
68 { 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO },
69 { 0x0f, "HOSTSR" },
70 { 0x13, "PERF" },
71 { 0x17, "PMU" },
72 { 0x18, "PTP" },
73 {}
74 };
75
76 void
gm107_fifo_intr_fault(struct nvkm_fifo * fifo,int unit)77 gm107_fifo_intr_fault(struct nvkm_fifo *fifo, int unit)
78 {
79 struct nvkm_device *device = fifo->engine.subdev.device;
80 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
81 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
82 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
83 u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
84 struct nvkm_fault_data info;
85
86 info.inst = (u64)inst << 12;
87 info.addr = ((u64)vahi << 32) | valo;
88 info.time = 0;
89 info.engine = unit;
90 info.valid = 1;
91 info.gpc = (type & 0x1f000000) >> 24;
92 info.client = (type & 0x00003f00) >> 8;
93 info.access = (type & 0x00000080) >> 7;
94 info.hub = (type & 0x00000040) >> 6;
95 info.reason = (type & 0x0000000f);
96
97 nvkm_fifo_fault(fifo, &info);
98 }
99
100 static const struct gk104_fifo_func
101 gm107_fifo = {
102 .intr.fault = gm107_fifo_intr_fault,
103 .pbdma = &gk208_fifo_pbdma,
104 .fault.access = gk104_fifo_fault_access,
105 .fault.engine = gm107_fifo_fault_engine,
106 .fault.reason = gk104_fifo_fault_reason,
107 .fault.hubclient = gk104_fifo_fault_hubclient,
108 .fault.gpcclient = gk104_fifo_fault_gpcclient,
109 .runlist = &gm107_fifo_runlist,
110 .chan = {{0,0,KEPLER_CHANNEL_GPFIFO_B}, gk104_fifo_gpfifo_new },
111 };
112
113 int
gm107_fifo_new(struct nvkm_device * device,int index,struct nvkm_fifo ** pfifo)114 gm107_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
115 {
116 return gk104_fifo_new_(&gm107_fifo, device, index, 2048, pfifo);
117 }
118