1 /* $NetBSD: nouveau_nvkm_engine_fifo_gf100.c,v 1.4 2021/12/18 23:45:35 riastradh Exp $ */
2
3 /*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_fifo_gf100.c,v 1.4 2021/12/18 23:45:35 riastradh Exp $");
28
29 #include "gf100.h"
30 #include "changf100.h"
31
32 #include <core/client.h>
33 #include <core/enum.h>
34 #include <core/gpuobj.h>
35 #include <subdev/bar.h>
36 #include <subdev/fault.h>
37 #include <engine/sw.h>
38
39 #include <nvif/class.h>
40
41 static void
gf100_fifo_uevent_init(struct nvkm_fifo * fifo)42 gf100_fifo_uevent_init(struct nvkm_fifo *fifo)
43 {
44 struct nvkm_device *device = fifo->engine.subdev.device;
45 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
46 }
47
48 static void
gf100_fifo_uevent_fini(struct nvkm_fifo * fifo)49 gf100_fifo_uevent_fini(struct nvkm_fifo *fifo)
50 {
51 struct nvkm_device *device = fifo->engine.subdev.device;
52 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
53 }
54
55 void
gf100_fifo_runlist_commit(struct gf100_fifo * fifo)56 gf100_fifo_runlist_commit(struct gf100_fifo *fifo)
57 {
58 struct gf100_fifo_chan *chan;
59 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
60 struct nvkm_device *device = subdev->device;
61 struct nvkm_memory *cur;
62 int nr = 0;
63 int target;
64
65 mutex_lock(&subdev->mutex);
66 cur = fifo->runlist.mem[fifo->runlist.active];
67 fifo->runlist.active = !fifo->runlist.active;
68
69 nvkm_kmap(cur);
70 list_for_each_entry(chan, &fifo->chan, head) {
71 nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid);
72 nvkm_wo32(cur, (nr * 8) + 4, 0x00000004);
73 nr++;
74 }
75 nvkm_done(cur);
76
77 switch (nvkm_memory_target(cur)) {
78 case NVKM_MEM_TARGET_VRAM: target = 0; break;
79 case NVKM_MEM_TARGET_NCOH: target = 3; break;
80 default:
81 mutex_unlock(&subdev->mutex);
82 WARN_ON(1);
83 return;
84 }
85
86 nvkm_wr32(device, 0x002270, (nvkm_memory_addr(cur) >> 12) |
87 (target << 28));
88 nvkm_wr32(device, 0x002274, 0x01f00000 | nr);
89
90 #ifdef __NetBSD__
91 /* XXX it is wrong to wait under mutex */
92 if (cold) {
93 uint count = 2000;
94 while (count-- > 0) {
95 if (!(nvkm_rd32(device, 0x00227c) & 0x00100000))
96 break;
97 delay(1000);
98 }
99 if (count == 0)
100 nvkm_error(subdev, "runlist update timeout\n");
101 } else {
102 int ret;
103
104 spin_lock(&fifo->runlist.lock);
105 DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret, &fifo->runlist.wait,
106 &fifo->runlist.lock, msecs_to_jiffies(2000),
107 !(nvkm_rd32(device, 0x00227c) & 0x00100000));
108 if (ret == 0)
109 nvkm_error(subdev, "runlist update timeout\n");
110 spin_unlock(&fifo->runlist.lock);
111 }
112 #else
113 if (wait_event_timeout(fifo->runlist.wait,
114 !(nvkm_rd32(device, 0x00227c) & 0x00100000),
115 msecs_to_jiffies(2000)) == 0)
116 nvkm_error(subdev, "runlist update timeout\n");
117 #endif
118 mutex_unlock(&subdev->mutex);
119 }
120
121 void
gf100_fifo_runlist_remove(struct gf100_fifo * fifo,struct gf100_fifo_chan * chan)122 gf100_fifo_runlist_remove(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan)
123 {
124 mutex_lock(&fifo->base.engine.subdev.mutex);
125 list_del_init(&chan->head);
126 mutex_unlock(&fifo->base.engine.subdev.mutex);
127 }
128
129 void
gf100_fifo_runlist_insert(struct gf100_fifo * fifo,struct gf100_fifo_chan * chan)130 gf100_fifo_runlist_insert(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan)
131 {
132 mutex_lock(&fifo->base.engine.subdev.mutex);
133 list_add_tail(&chan->head, &fifo->chan);
134 mutex_unlock(&fifo->base.engine.subdev.mutex);
135 }
136
137 static inline int
gf100_fifo_engidx(struct gf100_fifo * fifo,u32 engn)138 gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn)
139 {
140 switch (engn) {
141 case NVKM_ENGINE_GR : engn = 0; break;
142 case NVKM_ENGINE_MSVLD : engn = 1; break;
143 case NVKM_ENGINE_MSPPP : engn = 2; break;
144 case NVKM_ENGINE_MSPDEC: engn = 3; break;
145 case NVKM_ENGINE_CE0 : engn = 4; break;
146 case NVKM_ENGINE_CE1 : engn = 5; break;
147 default:
148 return -1;
149 }
150
151 return engn;
152 }
153
154 static inline struct nvkm_engine *
gf100_fifo_engine(struct gf100_fifo * fifo,u32 engn)155 gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
156 {
157 struct nvkm_device *device = fifo->base.engine.subdev.device;
158
159 switch (engn) {
160 case 0: engn = NVKM_ENGINE_GR; break;
161 case 1: engn = NVKM_ENGINE_MSVLD; break;
162 case 2: engn = NVKM_ENGINE_MSPPP; break;
163 case 3: engn = NVKM_ENGINE_MSPDEC; break;
164 case 4: engn = NVKM_ENGINE_CE0; break;
165 case 5: engn = NVKM_ENGINE_CE1; break;
166 default:
167 return NULL;
168 }
169
170 return nvkm_device_engine(device, engn);
171 }
172
173 static void
gf100_fifo_recover_work(struct work_struct * w)174 gf100_fifo_recover_work(struct work_struct *w)
175 {
176 struct gf100_fifo *fifo = container_of(w, typeof(*fifo), recover.work);
177 struct nvkm_device *device = fifo->base.engine.subdev.device;
178 struct nvkm_engine *engine;
179 unsigned long flags;
180 u32 engn, engm = 0;
181 u64 mask, todo;
182
183 spin_lock_irqsave(&fifo->base.lock, flags);
184 mask = fifo->recover.mask;
185 fifo->recover.mask = 0ULL;
186 spin_unlock_irqrestore(&fifo->base.lock, flags);
187
188 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn))
189 engm |= 1 << gf100_fifo_engidx(fifo, engn);
190 nvkm_mask(device, 0x002630, engm, engm);
191
192 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) {
193 if ((engine = nvkm_device_engine(device, engn))) {
194 nvkm_subdev_fini(&engine->subdev, false);
195 WARN_ON(nvkm_subdev_init(&engine->subdev));
196 }
197 }
198
199 gf100_fifo_runlist_commit(fifo);
200 nvkm_wr32(device, 0x00262c, engm);
201 nvkm_mask(device, 0x002630, engm, 0x00000000);
202 }
203
204 static void
gf100_fifo_recover(struct gf100_fifo * fifo,struct nvkm_engine * engine,struct gf100_fifo_chan * chan)205 gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
206 struct gf100_fifo_chan *chan)
207 {
208 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
209 struct nvkm_device *device = subdev->device;
210 u32 chid = chan->base.chid;
211
212 nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n",
213 nvkm_subdev_name[engine->subdev.index], chid);
214 assert_spin_locked(&fifo->base.lock);
215
216 nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
217 list_del_init(&chan->head);
218 chan->killed = true;
219
220 if (engine != &fifo->base.engine)
221 fifo->recover.mask |= 1ULL << engine->subdev.index;
222 schedule_work(&fifo->recover.work);
223 nvkm_fifo_kevent(&fifo->base, chid);
224 }
225
226 static const struct nvkm_enum
227 gf100_fifo_fault_engine[] = {
228 { 0x00, "PGRAPH", NULL, NVKM_ENGINE_GR },
229 { 0x03, "PEEPHOLE", NULL, NVKM_ENGINE_IFB },
230 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
231 { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
232 { 0x07, "PFIFO", NULL, NVKM_ENGINE_FIFO },
233 { 0x10, "PMSVLD", NULL, NVKM_ENGINE_MSVLD },
234 { 0x11, "PMSPPP", NULL, NVKM_ENGINE_MSPPP },
235 { 0x13, "PCOUNTER" },
236 { 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC },
237 { 0x15, "PCE0", NULL, NVKM_ENGINE_CE0 },
238 { 0x16, "PCE1", NULL, NVKM_ENGINE_CE1 },
239 { 0x17, "PMU" },
240 {}
241 };
242
243 static const struct nvkm_enum
244 gf100_fifo_fault_reason[] = {
245 { 0x00, "PT_NOT_PRESENT" },
246 { 0x01, "PT_TOO_SHORT" },
247 { 0x02, "PAGE_NOT_PRESENT" },
248 { 0x03, "VM_LIMIT_EXCEEDED" },
249 { 0x04, "NO_CHANNEL" },
250 { 0x05, "PAGE_SYSTEM_ONLY" },
251 { 0x06, "PAGE_READ_ONLY" },
252 { 0x0a, "COMPRESSED_SYSRAM" },
253 { 0x0c, "INVALID_STORAGE_TYPE" },
254 {}
255 };
256
257 static const struct nvkm_enum
258 gf100_fifo_fault_hubclient[] = {
259 { 0x01, "PCOPY0" },
260 { 0x02, "PCOPY1" },
261 { 0x04, "DISPATCH" },
262 { 0x05, "CTXCTL" },
263 { 0x06, "PFIFO" },
264 { 0x07, "BAR_READ" },
265 { 0x08, "BAR_WRITE" },
266 { 0x0b, "PVP" },
267 { 0x0c, "PMSPPP" },
268 { 0x0d, "PMSVLD" },
269 { 0x11, "PCOUNTER" },
270 { 0x12, "PMU" },
271 { 0x14, "CCACHE" },
272 { 0x15, "CCACHE_POST" },
273 {}
274 };
275
276 static const struct nvkm_enum
277 gf100_fifo_fault_gpcclient[] = {
278 { 0x01, "TEX" },
279 { 0x0c, "ESETUP" },
280 { 0x0e, "CTXCTL" },
281 { 0x0f, "PROP" },
282 {}
283 };
284
285 static void
gf100_fifo_fault(struct nvkm_fifo * base,struct nvkm_fault_data * info)286 gf100_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info)
287 {
288 struct gf100_fifo *fifo = gf100_fifo(base);
289 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
290 struct nvkm_device *device = subdev->device;
291 const struct nvkm_enum *er, *eu, *ec;
292 struct nvkm_engine *engine = NULL;
293 struct nvkm_fifo_chan *chan;
294 unsigned long flags;
295 char gpcid[8] = "";
296
297 er = nvkm_enum_find(gf100_fifo_fault_reason, info->reason);
298 eu = nvkm_enum_find(gf100_fifo_fault_engine, info->engine);
299 if (info->hub) {
300 ec = nvkm_enum_find(gf100_fifo_fault_hubclient, info->client);
301 } else {
302 ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, info->client);
303 snprintf(gpcid, sizeof(gpcid), "GPC%d/", info->gpc);
304 }
305
306 if (eu && eu->data2) {
307 switch (eu->data2) {
308 case NVKM_SUBDEV_BAR:
309 nvkm_bar_bar1_reset(device);
310 break;
311 case NVKM_SUBDEV_INSTMEM:
312 nvkm_bar_bar2_reset(device);
313 break;
314 case NVKM_ENGINE_IFB:
315 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
316 break;
317 default:
318 engine = nvkm_device_engine(device, eu->data2);
319 break;
320 }
321 }
322
323 chan = nvkm_fifo_chan_inst(&fifo->base, info->inst, &flags);
324
325 nvkm_error(subdev,
326 "%s fault at %010"PRIx64" engine %02x [%s] client %02x [%s%s] "
327 "reason %02x [%s] on channel %d [%010"PRIx64" %s]\n",
328 info->access ? "write" : "read", info->addr,
329 info->engine, eu ? eu->name : "",
330 info->client, gpcid, ec ? ec->name : "",
331 info->reason, er ? er->name : "", chan ? chan->chid : -1,
332 info->inst, chan ? chan->object.client->name : "unknown");
333
334 if (engine && chan)
335 gf100_fifo_recover(fifo, engine, (void *)chan);
336 nvkm_fifo_chan_put(&fifo->base, flags, &chan);
337 }
338
339 static const struct nvkm_enum
340 gf100_fifo_sched_reason[] = {
341 { 0x0a, "CTXSW_TIMEOUT" },
342 {}
343 };
344
345 static void
gf100_fifo_intr_sched_ctxsw(struct gf100_fifo * fifo)346 gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo)
347 {
348 struct nvkm_device *device = fifo->base.engine.subdev.device;
349 struct nvkm_engine *engine;
350 struct gf100_fifo_chan *chan;
351 unsigned long flags;
352 u32 engn;
353
354 spin_lock_irqsave(&fifo->base.lock, flags);
355 for (engn = 0; engn < 6; engn++) {
356 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));
357 u32 busy = (stat & 0x80000000);
358 u32 save = (stat & 0x00100000); /* maybe? */
359 u32 unk0 = (stat & 0x00040000);
360 u32 unk1 = (stat & 0x00001000);
361 u32 chid = (stat & 0x0000007f);
362 (void)save;
363
364 if (busy && unk0 && unk1) {
365 list_for_each_entry(chan, &fifo->chan, head) {
366 if (chan->base.chid == chid) {
367 engine = gf100_fifo_engine(fifo, engn);
368 if (!engine)
369 break;
370 gf100_fifo_recover(fifo, engine, chan);
371 break;
372 }
373 }
374 }
375 }
376 spin_unlock_irqrestore(&fifo->base.lock, flags);
377 }
378
379 static void
gf100_fifo_intr_sched(struct gf100_fifo * fifo)380 gf100_fifo_intr_sched(struct gf100_fifo *fifo)
381 {
382 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
383 struct nvkm_device *device = subdev->device;
384 u32 intr = nvkm_rd32(device, 0x00254c);
385 u32 code = intr & 0x000000ff;
386 const struct nvkm_enum *en;
387
388 en = nvkm_enum_find(gf100_fifo_sched_reason, code);
389
390 nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : "");
391
392 switch (code) {
393 case 0x0a:
394 gf100_fifo_intr_sched_ctxsw(fifo);
395 break;
396 default:
397 break;
398 }
399 }
400
401 void
gf100_fifo_intr_fault(struct nvkm_fifo * fifo,int unit)402 gf100_fifo_intr_fault(struct nvkm_fifo *fifo, int unit)
403 {
404 struct nvkm_device *device = fifo->engine.subdev.device;
405 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
406 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
407 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
408 u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
409 struct nvkm_fault_data info;
410
411 info.inst = (u64)inst << 12;
412 info.addr = ((u64)vahi << 32) | valo;
413 info.time = 0;
414 info.engine = unit;
415 info.valid = 1;
416 info.gpc = (type & 0x1f000000) >> 24;
417 info.client = (type & 0x00001f00) >> 8;
418 info.access = (type & 0x00000080) >> 7;
419 info.hub = (type & 0x00000040) >> 6;
420 info.reason = (type & 0x0000000f);
421
422 nvkm_fifo_fault(fifo, &info);
423 }
424
425 static const struct nvkm_bitfield
426 gf100_fifo_pbdma_intr[] = {
427 /* { 0x00008000, "" } seen with null ib push */
428 { 0x00200000, "ILLEGAL_MTHD" },
429 { 0x00800000, "EMPTY_SUBC" },
430 {}
431 };
432
433 static void
gf100_fifo_intr_pbdma(struct gf100_fifo * fifo,int unit)434 gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit)
435 {
436 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
437 struct nvkm_device *device = subdev->device;
438 u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000));
439 u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000));
440 u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000));
441 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f;
442 u32 subc = (addr & 0x00070000) >> 16;
443 u32 mthd = (addr & 0x00003ffc);
444 struct nvkm_fifo_chan *chan;
445 unsigned long flags;
446 u32 show= stat;
447 char msg[128];
448
449 if (stat & 0x00800000) {
450 if (device->sw) {
451 if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data))
452 show &= ~0x00800000;
453 }
454 }
455
456 if (show) {
457 nvkm_snprintbf(msg, sizeof(msg), gf100_fifo_pbdma_intr, show);
458 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags);
459 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010"PRIx64" %s] "
460 "subc %d mthd %04x data %08x\n",
461 unit, show, msg, chid, chan ? chan->inst->addr : 0,
462 chan ? chan->object.client->name : "unknown",
463 subc, mthd, data);
464 nvkm_fifo_chan_put(&fifo->base, flags, &chan);
465 }
466
467 nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
468 nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);
469 }
470
471 static void
gf100_fifo_intr_runlist(struct gf100_fifo * fifo)472 gf100_fifo_intr_runlist(struct gf100_fifo *fifo)
473 {
474 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
475 struct nvkm_device *device = subdev->device;
476 u32 intr = nvkm_rd32(device, 0x002a00);
477
478 if (intr & 0x10000000) {
479 #ifdef __NetBSD__
480 spin_lock(&fifo->runlist.lock);
481 DRM_SPIN_WAKEUP_ONE(&fifo->runlist.wait, &fifo->runlist.lock);
482 spin_unlock(&fifo->runlist.lock);
483 #else
484 wake_up(&fifo->runlist.wait);
485 #endif
486 nvkm_wr32(device, 0x002a00, 0x10000000);
487 intr &= ~0x10000000;
488 }
489
490 if (intr) {
491 nvkm_error(subdev, "RUNLIST %08x\n", intr);
492 nvkm_wr32(device, 0x002a00, intr);
493 }
494 }
495
496 static void
gf100_fifo_intr_engine_unit(struct gf100_fifo * fifo,int engn)497 gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn)
498 {
499 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
500 struct nvkm_device *device = subdev->device;
501 u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04));
502 u32 inte = nvkm_rd32(device, 0x002628);
503 u32 unkn;
504
505 nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr);
506
507 for (unkn = 0; unkn < 8; unkn++) {
508 u32 ints = (intr >> (unkn * 0x04)) & inte;
509 if (ints & 0x1) {
510 nvkm_fifo_uevent(&fifo->base);
511 ints &= ~1;
512 }
513 if (ints) {
514 nvkm_error(subdev, "ENGINE %d %d %01x",
515 engn, unkn, ints);
516 nvkm_mask(device, 0x002628, ints, 0);
517 }
518 }
519 }
520
521 void
gf100_fifo_intr_engine(struct gf100_fifo * fifo)522 gf100_fifo_intr_engine(struct gf100_fifo *fifo)
523 {
524 struct nvkm_device *device = fifo->base.engine.subdev.device;
525 u32 mask = nvkm_rd32(device, 0x0025a4);
526 while (mask) {
527 u32 unit = __ffs(mask);
528 gf100_fifo_intr_engine_unit(fifo, unit);
529 mask &= ~(1 << unit);
530 }
531 }
532
533 static void
gf100_fifo_intr(struct nvkm_fifo * base)534 gf100_fifo_intr(struct nvkm_fifo *base)
535 {
536 struct gf100_fifo *fifo = gf100_fifo(base);
537 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
538 struct nvkm_device *device = subdev->device;
539 u32 mask = nvkm_rd32(device, 0x002140);
540 u32 stat = nvkm_rd32(device, 0x002100) & mask;
541
542 if (stat & 0x00000001) {
543 u32 intr = nvkm_rd32(device, 0x00252c);
544 nvkm_warn(subdev, "INTR 00000001: %08x\n", intr);
545 nvkm_wr32(device, 0x002100, 0x00000001);
546 stat &= ~0x00000001;
547 }
548
549 if (stat & 0x00000100) {
550 gf100_fifo_intr_sched(fifo);
551 nvkm_wr32(device, 0x002100, 0x00000100);
552 stat &= ~0x00000100;
553 }
554
555 if (stat & 0x00010000) {
556 u32 intr = nvkm_rd32(device, 0x00256c);
557 nvkm_warn(subdev, "INTR 00010000: %08x\n", intr);
558 nvkm_wr32(device, 0x002100, 0x00010000);
559 stat &= ~0x00010000;
560 }
561
562 if (stat & 0x01000000) {
563 u32 intr = nvkm_rd32(device, 0x00258c);
564 nvkm_warn(subdev, "INTR 01000000: %08x\n", intr);
565 nvkm_wr32(device, 0x002100, 0x01000000);
566 stat &= ~0x01000000;
567 }
568
569 if (stat & 0x10000000) {
570 u32 mask = nvkm_rd32(device, 0x00259c);
571 while (mask) {
572 u32 unit = __ffs(mask);
573 gf100_fifo_intr_fault(&fifo->base, unit);
574 nvkm_wr32(device, 0x00259c, (1 << unit));
575 mask &= ~(1 << unit);
576 }
577 stat &= ~0x10000000;
578 }
579
580 if (stat & 0x20000000) {
581 u32 mask = nvkm_rd32(device, 0x0025a0);
582 while (mask) {
583 u32 unit = __ffs(mask);
584 gf100_fifo_intr_pbdma(fifo, unit);
585 nvkm_wr32(device, 0x0025a0, (1 << unit));
586 mask &= ~(1 << unit);
587 }
588 stat &= ~0x20000000;
589 }
590
591 if (stat & 0x40000000) {
592 gf100_fifo_intr_runlist(fifo);
593 stat &= ~0x40000000;
594 }
595
596 if (stat & 0x80000000) {
597 gf100_fifo_intr_engine(fifo);
598 stat &= ~0x80000000;
599 }
600
601 if (stat) {
602 nvkm_error(subdev, "INTR %08x\n", stat);
603 nvkm_mask(device, 0x002140, stat, 0x00000000);
604 nvkm_wr32(device, 0x002100, stat);
605 }
606 }
607
608 static int
gf100_fifo_oneinit(struct nvkm_fifo * base)609 gf100_fifo_oneinit(struct nvkm_fifo *base)
610 {
611 struct gf100_fifo *fifo = gf100_fifo(base);
612 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
613 struct nvkm_device *device = subdev->device;
614 struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device);
615 int ret;
616
617 /* Determine number of PBDMAs by checking valid enable bits. */
618 nvkm_wr32(device, 0x002204, 0xffffffff);
619 fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x002204));
620 nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr);
621
622
623 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
624 false, &fifo->runlist.mem[0]);
625 if (ret)
626 return ret;
627
628 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
629 false, &fifo->runlist.mem[1]);
630 if (ret)
631 return ret;
632
633 #ifdef __NetBSD__
634 spin_lock_init(&fifo->runlist.lock);
635 DRM_INIT_WAITQUEUE(&fifo->runlist.wait, "gf100fifo");
636 #else
637 init_waitqueue_head(&fifo->runlist.wait);
638 #endif
639
640 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000,
641 0x1000, false, &fifo->user.mem);
642 if (ret)
643 return ret;
644
645 ret = nvkm_vmm_get(bar, 12, nvkm_memory_size(fifo->user.mem),
646 &fifo->user.bar);
647 if (ret)
648 return ret;
649
650 return nvkm_memory_map(fifo->user.mem, 0, bar, fifo->user.bar, NULL, 0);
651 }
652
653 static void
gf100_fifo_fini(struct nvkm_fifo * base)654 gf100_fifo_fini(struct nvkm_fifo *base)
655 {
656 struct gf100_fifo *fifo = gf100_fifo(base);
657 flush_work(&fifo->recover.work);
658 }
659
660 static void
gf100_fifo_init(struct nvkm_fifo * base)661 gf100_fifo_init(struct nvkm_fifo *base)
662 {
663 struct gf100_fifo *fifo = gf100_fifo(base);
664 struct nvkm_device *device = fifo->base.engine.subdev.device;
665 int i;
666
667 /* Enable PBDMAs. */
668 nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1);
669 nvkm_wr32(device, 0x002204, (1 << fifo->pbdma_nr) - 1);
670
671 /* Assign engines to PBDMAs. */
672 if (fifo->pbdma_nr >= 3) {
673 nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */
674 nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */
675 nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */
676 nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */
677 nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */
678 nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */
679 }
680
681 /* PBDMA[n] */
682 for (i = 0; i < fifo->pbdma_nr; i++) {
683 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
684 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
685 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
686 }
687
688 nvkm_mask(device, 0x002200, 0x00000001, 0x00000001);
689 nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar->addr >> 12);
690
691 nvkm_wr32(device, 0x002100, 0xffffffff);
692 nvkm_wr32(device, 0x002140, 0x7fffffff);
693 nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
694 }
695
696 static void *
gf100_fifo_dtor(struct nvkm_fifo * base)697 gf100_fifo_dtor(struct nvkm_fifo *base)
698 {
699 struct gf100_fifo *fifo = gf100_fifo(base);
700 struct nvkm_device *device = fifo->base.engine.subdev.device;
701 nvkm_vmm_put(nvkm_bar_bar1_vmm(device), &fifo->user.bar);
702 nvkm_memory_unref(&fifo->user.mem);
703 nvkm_memory_unref(&fifo->runlist.mem[0]);
704 nvkm_memory_unref(&fifo->runlist.mem[1]);
705 #ifdef __NetBSD__
706 DRM_DESTROY_WAITQUEUE(&fifo->runlist.wait);
707 spin_lock_destroy(&fifo->runlist.lock);
708 #endif
709 return fifo;
710 }
711
712 static const struct nvkm_fifo_func
713 gf100_fifo = {
714 .dtor = gf100_fifo_dtor,
715 .oneinit = gf100_fifo_oneinit,
716 .init = gf100_fifo_init,
717 .fini = gf100_fifo_fini,
718 .intr = gf100_fifo_intr,
719 .fault = gf100_fifo_fault,
720 .uevent_init = gf100_fifo_uevent_init,
721 .uevent_fini = gf100_fifo_uevent_fini,
722 .chan = {
723 &gf100_fifo_gpfifo_oclass,
724 NULL
725 },
726 };
727
728 int
gf100_fifo_new(struct nvkm_device * device,int index,struct nvkm_fifo ** pfifo)729 gf100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
730 {
731 struct gf100_fifo *fifo;
732
733 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
734 return -ENOMEM;
735 INIT_LIST_HEAD(&fifo->chan);
736 INIT_WORK(&fifo->recover.work, gf100_fifo_recover_work);
737 *pfifo = &fifo->base;
738
739 return nvkm_fifo_ctor(&gf100_fifo, device, index, 128, &fifo->base);
740 }
741