1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise X86 hardware features.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/Support/X86TargetParser.h"
14 #include "llvm/ADT/Triple.h"
15
16 using namespace llvm;
17 using namespace llvm::X86;
18
19 namespace {
20
21 /// Container class for CPU features.
22 /// This is a constexpr reimplementation of a subset of std::bitset. It would be
23 /// nice to use std::bitset directly, but it doesn't support constant
24 /// initialization.
25 class FeatureBitset {
26 static constexpr unsigned NUM_FEATURE_WORDS =
27 (X86::CPU_FEATURE_MAX + 31) / 32;
28
29 // This cannot be a std::array, operator[] is not constexpr until C++17.
30 uint32_t Bits[NUM_FEATURE_WORDS] = {};
31
32 public:
33 constexpr FeatureBitset() = default;
FeatureBitset(std::initializer_list<unsigned> Init)34 constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
35 for (auto I : Init)
36 set(I);
37 }
38
any() const39 bool any() const {
40 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
41 }
42
set(unsigned I)43 constexpr FeatureBitset &set(unsigned I) {
44 // GCC <6.2 crashes if this is written in a single statement.
45 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
46 Bits[I / 32] = NewBits;
47 return *this;
48 }
49
operator [](unsigned I) const50 constexpr bool operator[](unsigned I) const {
51 uint32_t Mask = uint32_t(1) << (I % 32);
52 return (Bits[I / 32] & Mask) != 0;
53 }
54
operator &=(const FeatureBitset & RHS)55 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
56 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
57 // GCC <6.2 crashes if this is written in a single statement.
58 uint32_t NewBits = Bits[I] & RHS.Bits[I];
59 Bits[I] = NewBits;
60 }
61 return *this;
62 }
63
operator |=(const FeatureBitset & RHS)64 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
65 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
66 // GCC <6.2 crashes if this is written in a single statement.
67 uint32_t NewBits = Bits[I] | RHS.Bits[I];
68 Bits[I] = NewBits;
69 }
70 return *this;
71 }
72
73 // gcc 5.3 miscompiles this if we try to write this using operator&=.
operator &(const FeatureBitset & RHS) const74 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
75 FeatureBitset Result;
76 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
77 Result.Bits[I] = Bits[I] & RHS.Bits[I];
78 return Result;
79 }
80
81 // gcc 5.3 miscompiles this if we try to write this using operator&=.
operator |(const FeatureBitset & RHS) const82 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
83 FeatureBitset Result;
84 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
85 Result.Bits[I] = Bits[I] | RHS.Bits[I];
86 return Result;
87 }
88
operator ~() const89 constexpr FeatureBitset operator~() const {
90 FeatureBitset Result;
91 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
92 Result.Bits[I] = ~Bits[I];
93 return Result;
94 }
95
operator !=(const FeatureBitset & RHS) const96 constexpr bool operator!=(const FeatureBitset &RHS) const {
97 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
98 if (Bits[I] != RHS.Bits[I])
99 return true;
100 return false;
101 }
102 };
103
104 struct ProcInfo {
105 StringLiteral Name;
106 X86::CPUKind Kind;
107 unsigned KeyFeature;
108 FeatureBitset Features;
109 };
110
111 struct FeatureInfo {
112 StringLiteral Name;
113 FeatureBitset ImpliedFeatures;
114 };
115
116 } // end anonymous namespace
117
118 #define X86_FEATURE(ENUM, STRING) \
119 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
120 #include "llvm/Support/X86TargetParser.def"
121
122 // Pentium with MMX.
123 constexpr FeatureBitset FeaturesPentiumMMX =
124 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
125
126 // Pentium 2 and 3.
127 constexpr FeatureBitset FeaturesPentium2 =
128 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
129 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
130
131 // Pentium 4 CPUs
132 constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
133 constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
134 constexpr FeatureBitset FeaturesNocona =
135 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
136
137 // Basic 64-bit capable CPU.
138 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
139 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
140 FeaturePOPCNT | FeatureSSE4_2 |
141 FeatureCMPXCHG16B;
142 constexpr FeatureBitset FeaturesX86_64_V3 =
143 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
144 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
145 constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 |
146 FeatureAVX512BW | FeatureAVX512CD |
147 FeatureAVX512DQ | FeatureAVX512VL;
148
149 // Intel Core CPUs
150 constexpr FeatureBitset FeaturesCore2 =
151 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
152 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
153 constexpr FeatureBitset FeaturesNehalem =
154 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
155 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
156 constexpr FeatureBitset FeaturesSandyBridge =
157 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
158 constexpr FeatureBitset FeaturesIvyBridge =
159 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
160 constexpr FeatureBitset FeaturesHaswell =
161 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
162 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
163 constexpr FeatureBitset FeaturesBroadwell =
164 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
165
166 // Intel Knights Landing and Knights Mill
167 // Knights Landing has feature parity with Broadwell.
168 constexpr FeatureBitset FeaturesKNL =
169 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
170 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
171 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
172
173 // Intel Skylake processors.
174 constexpr FeatureBitset FeaturesSkylakeClient =
175 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
176 FeatureXSAVES | FeatureSGX;
177 // SkylakeServer inherits all SkylakeClient features except SGX.
178 // FIXME: That doesn't match gcc.
179 constexpr FeatureBitset FeaturesSkylakeServer =
180 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
181 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
182 FeaturePKU;
183 constexpr FeatureBitset FeaturesCascadeLake =
184 FeaturesSkylakeServer | FeatureAVX512VNNI;
185 constexpr FeatureBitset FeaturesCooperLake =
186 FeaturesCascadeLake | FeatureAVX512BF16;
187
188 // Intel 10nm processors.
189 constexpr FeatureBitset FeaturesCannonlake =
190 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
191 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
192 FeaturePKU | FeatureSHA;
193 constexpr FeatureBitset FeaturesICLClient =
194 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
195 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
196 FeatureVAES | FeatureVPCLMULQDQ;
197 constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
198 constexpr FeatureBitset FeaturesICLServer =
199 FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
200 constexpr FeatureBitset FeaturesTigerlake =
201 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
202 FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
203 constexpr FeatureBitset FeaturesSapphireRapids =
204 FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
205 FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE |
206 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
207 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
208 FeatureWAITPKG | FeatureAVXVNNI;
209
210 // Intel Atom processors.
211 // Bonnell has feature parity with Core2 and adds MOVBE.
212 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
213 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
214 constexpr FeatureBitset FeaturesSilvermont =
215 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
216 constexpr FeatureBitset FeaturesGoldmont =
217 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
218 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
219 FeatureXSAVEOPT | FeatureXSAVES;
220 constexpr FeatureBitset FeaturesGoldmontPlus =
221 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
222 constexpr FeatureBitset FeaturesTremont =
223 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
224 constexpr FeatureBitset FeaturesAlderlake =
225 FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
226 FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
227 FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
228 FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
229 FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
230
231 // Geode Processor.
232 constexpr FeatureBitset FeaturesGeode =
233 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
234
235 // K6 processor.
236 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
237
238 // K7 and K8 architecture processors.
239 constexpr FeatureBitset FeaturesAthlon =
240 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
241 constexpr FeatureBitset FeaturesAthlonXP =
242 FeaturesAthlon | FeatureFXSR | FeatureSSE;
243 constexpr FeatureBitset FeaturesK8 =
244 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
245 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
246 constexpr FeatureBitset FeaturesAMDFAM10 =
247 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
248 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
249
250 // Bobcat architecture processors.
251 constexpr FeatureBitset FeaturesBTVER1 =
252 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
253 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
254 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
255 FeatureSAHF;
256 constexpr FeatureBitset FeaturesBTVER2 =
257 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
258 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
259
260 // AMD Bulldozer architecture processors.
261 constexpr FeatureBitset FeaturesBDVER1 =
262 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
263 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
264 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
265 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
266 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
267 constexpr FeatureBitset FeaturesBDVER2 =
268 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
269 constexpr FeatureBitset FeaturesBDVER3 =
270 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
271 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
272 FeatureBMI2 | FeatureMOVBE |
273 FeatureMWAITX | FeatureRDRND;
274
275 // AMD Zen architecture processors.
276 constexpr FeatureBitset FeaturesZNVER1 =
277 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
278 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
279 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
280 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
281 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
282 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
283 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
284 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
285 FeatureXSAVEOPT | FeatureXSAVES;
286 constexpr FeatureBitset FeaturesZNVER2 =
287 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
288 static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
289 FeatureINVPCID | FeaturePKU |
290 FeatureVAES | FeatureVPCLMULQDQ;
291
292 constexpr ProcInfo Processors[] = {
293 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
294 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
295 // i386-generation processors.
296 { {"i386"}, CK_i386, ~0U, FeatureX87 },
297 // i486-generation processors.
298 { {"i486"}, CK_i486, ~0U, FeatureX87 },
299 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
300 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
301 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
302 // i586-generation processors, P5 microarchitecture based.
303 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
304 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
305 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
306 // i686-generation processors, P6 / Pentium M microarchitecture based.
307 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
308 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
309 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
310 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
311 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
312 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
313 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
314 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
315 // Netburst microarchitecture based processors.
316 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
317 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
318 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
319 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
320 // Core microarchitecture based processors.
321 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
322 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
323 // Atom processors
324 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
325 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
326 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
327 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
328 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
329 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
330 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
331 // Nehalem microarchitecture based processors.
332 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
333 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
334 // Westmere microarchitecture based processors.
335 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
336 // Sandy Bridge microarchitecture based processors.
337 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
338 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
339 // Ivy Bridge microarchitecture based processors.
340 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
341 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
342 // Haswell microarchitecture based processors.
343 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
344 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
345 // Broadwell microarchitecture based processors.
346 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
347 // Skylake client microarchitecture based processors.
348 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
349 // Skylake server microarchitecture based processors.
350 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
351 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
352 // Cascadelake Server microarchitecture based processors.
353 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
354 // Cooperlake Server microarchitecture based processors.
355 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
356 // Cannonlake client microarchitecture based processors.
357 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
358 // Icelake client microarchitecture based processors.
359 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
360 // Rocketlake microarchitecture based processors.
361 { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake },
362 // Icelake server microarchitecture based processors.
363 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
364 // Tigerlake microarchitecture based processors.
365 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
366 // Sapphire Rapids microarchitecture based processors.
367 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
368 // Alderlake microarchitecture based processors.
369 { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
370 // Knights Landing processor.
371 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
372 // Knights Mill processor.
373 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
374 // Lakemont microarchitecture based processors.
375 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
376 // K6 architecture processors.
377 { {"k6"}, CK_K6, ~0U, FeaturesK6 },
378 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
379 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
380 // K7 architecture processors.
381 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
382 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
383 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
384 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
385 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
386 // K8 architecture processors.
387 { {"k8"}, CK_K8, ~0U, FeaturesK8 },
388 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
389 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
390 { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
391 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
392 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
393 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
394 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
395 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
396 // Bobcat architecture processors.
397 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
398 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
399 // Bulldozer architecture processors.
400 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
401 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
402 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
403 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
404 // Zen architecture processors.
405 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
406 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
407 { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 },
408 // Generic 64-bit processor.
409 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
410 { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
411 { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
412 { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
413 // Geode processors.
414 { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
415 };
416
417 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
418
parseArchX86(StringRef CPU,bool Only64Bit)419 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
420 for (const auto &P : Processors)
421 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
422 return P.Kind;
423
424 return CK_None;
425 }
426
parseTuneCPU(StringRef CPU,bool Only64Bit)427 X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
428 if (llvm::is_contained(NoTuneList, CPU))
429 return CK_None;
430 return parseArchX86(CPU, Only64Bit);
431 }
432
fillValidCPUArchList(SmallVectorImpl<StringRef> & Values,bool Only64Bit)433 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
434 bool Only64Bit) {
435 for (const auto &P : Processors)
436 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
437 Values.emplace_back(P.Name);
438 }
439
fillValidTuneCPUList(SmallVectorImpl<StringRef> & Values,bool Only64Bit)440 void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
441 bool Only64Bit) {
442 for (const ProcInfo &P : Processors)
443 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) &&
444 !llvm::is_contained(NoTuneList, P.Name))
445 Values.emplace_back(P.Name);
446 }
447
getKeyFeature(X86::CPUKind Kind)448 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
449 // FIXME: Can we avoid a linear search here? The table might be sorted by
450 // CPUKind so we could binary search?
451 for (const auto &P : Processors) {
452 if (P.Kind == Kind) {
453 assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
454 return static_cast<ProcessorFeatures>(P.KeyFeature);
455 }
456 }
457
458 llvm_unreachable("Unable to find CPU kind!");
459 }
460
461 // Features with no dependencies.
462 constexpr FeatureBitset ImpliedFeatures64BIT = {};
463 constexpr FeatureBitset ImpliedFeaturesADX = {};
464 constexpr FeatureBitset ImpliedFeaturesBMI = {};
465 constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
466 constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
467 constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
468 constexpr FeatureBitset ImpliedFeaturesCLWB = {};
469 constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
470 constexpr FeatureBitset ImpliedFeaturesCMOV = {};
471 constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
472 constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
473 constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
474 constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
475 constexpr FeatureBitset ImpliedFeaturesFXSR = {};
476 constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
477 constexpr FeatureBitset ImpliedFeaturesLWP = {};
478 constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
479 constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
480 constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
481 constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
482 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
483 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
484 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
485 constexpr FeatureBitset ImpliedFeaturesPKU = {};
486 constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
487 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
488 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
489 constexpr FeatureBitset ImpliedFeaturesRDPID = {};
490 constexpr FeatureBitset ImpliedFeaturesRDRND = {};
491 constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
492 constexpr FeatureBitset ImpliedFeaturesRTM = {};
493 constexpr FeatureBitset ImpliedFeaturesSAHF = {};
494 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
495 constexpr FeatureBitset ImpliedFeaturesSGX = {};
496 constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
497 constexpr FeatureBitset ImpliedFeaturesTBM = {};
498 constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
499 constexpr FeatureBitset ImpliedFeaturesUINTR = {};
500 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
501 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
502 constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
503 constexpr FeatureBitset ImpliedFeaturesX87 = {};
504 constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
505
506 // Not really CPU features, but need to be in the table because clang uses
507 // target features to communicate them to the backend.
508 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
509 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
510 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
511 constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
512 constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
513
514 // XSAVE features are dependent on basic XSAVE.
515 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
516 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
517 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
518
519 // MMX->3DNOW->3DNOWA chain.
520 constexpr FeatureBitset ImpliedFeaturesMMX = {};
521 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
522 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
523
524 // SSE/AVX/AVX512F chain.
525 constexpr FeatureBitset ImpliedFeaturesSSE = {};
526 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
527 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
528 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
529 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
530 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
531 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
532 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
533 constexpr FeatureBitset ImpliedFeaturesAVX512F =
534 FeatureAVX2 | FeatureF16C | FeatureFMA;
535
536 // Vector extensions that build on SSE or AVX.
537 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
538 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
539 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
540 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
541 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
542 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
543 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
544 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
545
546 // AVX512 features.
547 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
548 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
549 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
550 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
551 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
552 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
553
554 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
555 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
556 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
557 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
558 constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
559 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
560 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
561 constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
562
563 // FIXME: These two aren't really implemented and just exist in the feature
564 // list for __builtin_cpu_supports. So omit their dependencies.
565 constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
566 constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
567
568 // SSE4_A->FMA4->XOP chain.
569 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
570 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
571 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
572
573 // AMX Features
574 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
575 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
576 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
577 constexpr FeatureBitset ImpliedFeaturesHRESET = {};
578
579 // Key Locker Features
580 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
581 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
582
583 // AVXVNNI Features
584 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
585
586 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
587 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
588 #include "llvm/Support/X86TargetParser.def"
589 };
590
getFeaturesForCPU(StringRef CPU,SmallVectorImpl<StringRef> & EnabledFeatures)591 void llvm::X86::getFeaturesForCPU(StringRef CPU,
592 SmallVectorImpl<StringRef> &EnabledFeatures) {
593 auto I = llvm::find_if(Processors,
594 [&](const ProcInfo &P) { return P.Name == CPU; });
595 assert(I != std::end(Processors) && "Processor not found!");
596
597 FeatureBitset Bits = I->Features;
598
599 // Remove the 64-bit feature which we only use to validate if a CPU can
600 // be used with 64-bit mode.
601 Bits &= ~Feature64BIT;
602
603 // Add the string version of all set bits.
604 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
605 if (Bits[i] && !FeatureInfos[i].Name.empty())
606 EnabledFeatures.push_back(FeatureInfos[i].Name);
607 }
608
609 // For each feature that is (transitively) implied by this feature, set it.
getImpliedEnabledFeatures(FeatureBitset & Bits,const FeatureBitset & Implies)610 static void getImpliedEnabledFeatures(FeatureBitset &Bits,
611 const FeatureBitset &Implies) {
612 // Fast path: Implies is often empty.
613 if (!Implies.any())
614 return;
615 FeatureBitset Prev;
616 Bits |= Implies;
617 do {
618 Prev = Bits;
619 for (unsigned i = CPU_FEATURE_MAX; i;)
620 if (Bits[--i])
621 Bits |= FeatureInfos[i].ImpliedFeatures;
622 } while (Prev != Bits);
623 }
624
625 /// Create bit vector of features that are implied disabled if the feature
626 /// passed in Value is disabled.
getImpliedDisabledFeatures(FeatureBitset & Bits,unsigned Value)627 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
628 // Check all features looking for any dependent on this feature. If we find
629 // one, mark it and recursively find any feature that depend on it.
630 FeatureBitset Prev;
631 Bits.set(Value);
632 do {
633 Prev = Bits;
634 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
635 if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
636 Bits.set(i);
637 } while (Prev != Bits);
638 }
639
updateImpliedFeatures(StringRef Feature,bool Enabled,StringMap<bool> & Features)640 void llvm::X86::updateImpliedFeatures(
641 StringRef Feature, bool Enabled,
642 StringMap<bool> &Features) {
643 auto I = llvm::find_if(
644 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
645 if (I == std::end(FeatureInfos)) {
646 // FIXME: This shouldn't happen, but may not have all features in the table
647 // yet.
648 return;
649 }
650
651 FeatureBitset ImpliedBits;
652 if (Enabled)
653 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
654 else
655 getImpliedDisabledFeatures(ImpliedBits,
656 std::distance(std::begin(FeatureInfos), I));
657
658 // Update the map entry for all implied features.
659 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
660 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
661 Features[FeatureInfos[i].Name] = Enabled;
662 }
663