1 /* $NetBSD: amdgpu_bios_parser2.c,v 1.2 2021/12/18 23:45:00 riastradh Exp $ */
2
3 /*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_bios_parser2.c,v 1.2 2021/12/18 23:45:00 riastradh Exp $");
30
31 #include <linux/slab.h>
32
33 #include "dm_services.h"
34
35 #include "ObjectID.h"
36 #include "atomfirmware.h"
37
38 #include "dc_bios_types.h"
39 #include "include/grph_object_ctrl_defs.h"
40 #include "include/bios_parser_interface.h"
41 #include "include/i2caux_interface.h"
42 #include "include/logger_interface.h"
43
44 #include "command_table2.h"
45
46 #include "bios_parser_helper.h"
47 #include "command_table_helper2.h"
48 #include "bios_parser2.h"
49 #include "bios_parser_types_internal2.h"
50 #include "bios_parser_interface.h"
51
52 #include "bios_parser_common.h"
53
54 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */
55 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT
56 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05
57 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */
58
59 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1
60 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \
61 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
62 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
63 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
64 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */
65
66 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2
67 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \
68 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
69 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
70 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
71 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */
72
73 #define DC_LOGGER \
74 bp->base.ctx->logger
75
76 #define LAST_RECORD_TYPE 0xff
77 #define SMU9_SYSPLL0_ID 0
78
79 struct i2c_id_config_access {
80 uint8_t bfI2C_LineMux:4;
81 uint8_t bfHW_EngineID:3;
82 uint8_t bfHW_Capable:1;
83 uint8_t ucAccess;
84 };
85
86 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
87 struct atom_i2c_record *record,
88 struct graphics_object_i2c_info *info);
89
90 static enum bp_result bios_parser_get_firmware_info(
91 struct dc_bios *dcb,
92 struct dc_firmware_info *info);
93
94 static enum bp_result bios_parser_get_encoder_cap_info(
95 struct dc_bios *dcb,
96 struct graphics_object_id object_id,
97 struct bp_encoder_cap_info *info);
98
99 static enum bp_result get_firmware_info_v3_1(
100 struct bios_parser *bp,
101 struct dc_firmware_info *info);
102
103 static enum bp_result get_firmware_info_v3_2(
104 struct bios_parser *bp,
105 struct dc_firmware_info *info);
106
107 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
108 struct atom_display_object_path_v2 *object);
109
110 static struct atom_encoder_caps_record *get_encoder_cap_record(
111 struct bios_parser *bp,
112 struct atom_display_object_path_v2 *object);
113
114 #define BIOS_IMAGE_SIZE_OFFSET 2
115 #define BIOS_IMAGE_SIZE_UNIT 512
116
117 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
118
bios_parser2_destruct(struct bios_parser * bp)119 static void bios_parser2_destruct(struct bios_parser *bp)
120 {
121 kfree(bp->base.bios_local_image);
122 kfree(bp->base.integrated_info);
123 }
124
firmware_parser_destroy(struct dc_bios ** dcb)125 static void firmware_parser_destroy(struct dc_bios **dcb)
126 {
127 struct bios_parser *bp = BP_FROM_DCB(*dcb);
128
129 if (!bp) {
130 BREAK_TO_DEBUGGER();
131 return;
132 }
133
134 bios_parser2_destruct(bp);
135
136 kfree(bp);
137 *dcb = NULL;
138 }
139
get_atom_data_table_revision(struct atom_common_table_header * atom_data_tbl,struct atom_data_revision * tbl_revision)140 static void get_atom_data_table_revision(
141 struct atom_common_table_header *atom_data_tbl,
142 struct atom_data_revision *tbl_revision)
143 {
144 if (!tbl_revision)
145 return;
146
147 /* initialize the revision to 0 which is invalid revision */
148 tbl_revision->major = 0;
149 tbl_revision->minor = 0;
150
151 if (!atom_data_tbl)
152 return;
153
154 tbl_revision->major =
155 (uint32_t) atom_data_tbl->format_revision & 0x3f;
156 tbl_revision->minor =
157 (uint32_t) atom_data_tbl->content_revision & 0x3f;
158 }
159
160 /* BIOS oject table displaypath is per connector.
161 * There is extra path not for connector. BIOS fill its encoderid as 0
162 */
bios_parser_get_connectors_number(struct dc_bios * dcb)163 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
164 {
165 struct bios_parser *bp = BP_FROM_DCB(dcb);
166 unsigned int count = 0;
167 unsigned int i;
168
169 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
170 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
171 count++;
172 }
173 return count;
174 }
175
bios_parser_get_connector_id(struct dc_bios * dcb,uint8_t i)176 static struct graphics_object_id bios_parser_get_connector_id(
177 struct dc_bios *dcb,
178 uint8_t i)
179 {
180 struct bios_parser *bp = BP_FROM_DCB(dcb);
181 struct graphics_object_id object_id = dal_graphics_object_id_init(
182 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
183 struct object_info_table *tbl = &bp->object_info_tbl;
184 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
185
186 if (v1_4->number_of_path > i) {
187 /* If display_objid is generic object id, the encoderObj
188 * /extencoderobjId should be 0
189 */
190 if (v1_4->display_path[i].encoderobjid != 0 &&
191 v1_4->display_path[i].display_objid != 0)
192 object_id = object_id_from_bios_object_id(
193 v1_4->display_path[i].display_objid);
194 }
195
196 return object_id;
197 }
198
bios_parser_get_src_obj(struct dc_bios * dcb,struct graphics_object_id object_id,uint32_t index,struct graphics_object_id * src_object_id)199 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
200 struct graphics_object_id object_id, uint32_t index,
201 struct graphics_object_id *src_object_id)
202 {
203 struct bios_parser *bp = BP_FROM_DCB(dcb);
204 unsigned int i;
205 enum bp_result bp_result = BP_RESULT_BADINPUT;
206 struct graphics_object_id obj_id = {0};
207 struct object_info_table *tbl = &bp->object_info_tbl;
208
209 if (!src_object_id)
210 return bp_result;
211
212 switch (object_id.type) {
213 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
214 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
215 */
216 case OBJECT_TYPE_ENCODER:
217 /* TODO: since num of src must be less than 2.
218 * If found in for loop, should break.
219 * DAL2 implementation may be changed too
220 */
221 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
222 obj_id = object_id_from_bios_object_id(
223 tbl->v1_4->display_path[i].encoderobjid);
224 if (object_id.type == obj_id.type &&
225 object_id.id == obj_id.id &&
226 object_id.enum_id ==
227 obj_id.enum_id) {
228 *src_object_id =
229 object_id_from_bios_object_id(0x1100);
230 /* break; */
231 }
232 }
233 bp_result = BP_RESULT_OK;
234 break;
235 case OBJECT_TYPE_CONNECTOR:
236 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
237 obj_id = object_id_from_bios_object_id(
238 tbl->v1_4->display_path[i].display_objid);
239
240 if (object_id.type == obj_id.type &&
241 object_id.id == obj_id.id &&
242 object_id.enum_id == obj_id.enum_id) {
243 *src_object_id =
244 object_id_from_bios_object_id(
245 tbl->v1_4->display_path[i].encoderobjid);
246 /* break; */
247 }
248 }
249 bp_result = BP_RESULT_OK;
250 break;
251 default:
252 break;
253 }
254
255 return bp_result;
256 }
257
258 /* from graphics_object_id, find display path which includes the object_id */
get_bios_object(struct bios_parser * bp,struct graphics_object_id id)259 static struct atom_display_object_path_v2 *get_bios_object(
260 struct bios_parser *bp,
261 struct graphics_object_id id)
262 {
263 unsigned int i;
264 struct graphics_object_id obj_id = {0};
265
266 switch (id.type) {
267 case OBJECT_TYPE_ENCODER:
268 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
269 obj_id = object_id_from_bios_object_id(
270 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
271 if (id.type == obj_id.type && id.id == obj_id.id
272 && id.enum_id == obj_id.enum_id)
273 return &bp->object_info_tbl.v1_4->display_path[i];
274 }
275 /* fall through */
276 case OBJECT_TYPE_CONNECTOR:
277 case OBJECT_TYPE_GENERIC:
278 /* Both Generic and Connector Object ID
279 * will be stored on display_objid
280 */
281 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
282 obj_id = object_id_from_bios_object_id(
283 bp->object_info_tbl.v1_4->display_path[i].display_objid);
284 if (id.type == obj_id.type && id.id == obj_id.id
285 && id.enum_id == obj_id.enum_id)
286 return &bp->object_info_tbl.v1_4->display_path[i];
287 }
288 /* fall through */
289 default:
290 return NULL;
291 }
292 }
293
bios_parser_get_i2c_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_i2c_info * info)294 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
295 struct graphics_object_id id,
296 struct graphics_object_i2c_info *info)
297 {
298 uint32_t offset;
299 struct atom_display_object_path_v2 *object;
300 struct atom_common_record_header *header;
301 struct atom_i2c_record *record;
302 struct atom_i2c_record dummy_record = {0};
303 struct bios_parser *bp = BP_FROM_DCB(dcb);
304
305 if (!info)
306 return BP_RESULT_BADINPUT;
307
308 if (id.type == OBJECT_TYPE_GENERIC) {
309 dummy_record.i2c_id = id.id;
310
311 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
312 return BP_RESULT_OK;
313 else
314 return BP_RESULT_NORECORD;
315 }
316
317 object = get_bios_object(bp, id);
318
319 if (!object)
320 return BP_RESULT_BADINPUT;
321
322 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
323
324 for (;;) {
325 header = GET_IMAGE(struct atom_common_record_header, offset);
326
327 if (!header)
328 return BP_RESULT_BADBIOSTABLE;
329
330 if (header->record_type == LAST_RECORD_TYPE ||
331 !header->record_size)
332 break;
333
334 if (header->record_type == ATOM_I2C_RECORD_TYPE
335 && sizeof(struct atom_i2c_record) <=
336 header->record_size) {
337 /* get the I2C info */
338 record = (struct atom_i2c_record *) header;
339
340 if (get_gpio_i2c_info(bp, record, info) ==
341 BP_RESULT_OK)
342 return BP_RESULT_OK;
343 }
344
345 offset += header->record_size;
346 }
347
348 return BP_RESULT_NORECORD;
349 }
350
get_gpio_i2c_info(struct bios_parser * bp,struct atom_i2c_record * record,struct graphics_object_i2c_info * info)351 static enum bp_result get_gpio_i2c_info(
352 struct bios_parser *bp,
353 struct atom_i2c_record *record,
354 struct graphics_object_i2c_info *info)
355 {
356 struct atom_gpio_pin_lut_v2_1 *header;
357 uint32_t count = 0;
358 unsigned int table_index = 0;
359 bool find_valid = false;
360
361 if (!info)
362 return BP_RESULT_BADINPUT;
363
364 /* get the GPIO_I2C info */
365 if (!DATA_TABLES(gpio_pin_lut))
366 return BP_RESULT_BADBIOSTABLE;
367
368 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
369 DATA_TABLES(gpio_pin_lut));
370 if (!header)
371 return BP_RESULT_BADBIOSTABLE;
372
373 if (sizeof(struct atom_common_table_header) +
374 sizeof(struct atom_gpio_pin_assignment) >
375 le16_to_cpu(header->table_header.structuresize))
376 return BP_RESULT_BADBIOSTABLE;
377
378 /* TODO: is version change? */
379 if (header->table_header.content_revision != 1)
380 return BP_RESULT_UNSUPPORTED;
381
382 /* get data count */
383 count = (le16_to_cpu(header->table_header.structuresize)
384 - sizeof(struct atom_common_table_header))
385 / sizeof(struct atom_gpio_pin_assignment);
386
387 for (table_index = 0; table_index < count; table_index++) {
388 if (((record->i2c_id & I2C_HW_CAP) == (
389 header->gpio_pin[table_index].gpio_id &
390 I2C_HW_CAP)) &&
391 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) ==
392 (header->gpio_pin[table_index].gpio_id &
393 I2C_HW_ENGINE_ID_MASK)) &&
394 ((record->i2c_id & I2C_HW_LANE_MUX) ==
395 (header->gpio_pin[table_index].gpio_id &
396 I2C_HW_LANE_MUX))) {
397 /* still valid */
398 find_valid = true;
399 break;
400 }
401 }
402
403 /* If we don't find the entry that we are looking for then
404 * we will return BP_Result_BadBiosTable.
405 */
406 if (find_valid == false)
407 return BP_RESULT_BADBIOSTABLE;
408
409 /* get the GPIO_I2C_INFO */
410 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
411 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
412 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
413 info->i2c_slave_address = record->i2c_slave_addr;
414
415 /* TODO: check how to get register offset for en, Y, etc. */
416 info->gpio_info.clk_a_register_index =
417 le16_to_cpu(
418 header->gpio_pin[table_index].data_a_reg_index);
419 info->gpio_info.clk_a_shift =
420 header->gpio_pin[table_index].gpio_bitshift;
421
422 return BP_RESULT_OK;
423 }
424
bios_parser_get_hpd_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_hpd_info * info)425 static enum bp_result bios_parser_get_hpd_info(
426 struct dc_bios *dcb,
427 struct graphics_object_id id,
428 struct graphics_object_hpd_info *info)
429 {
430 struct bios_parser *bp = BP_FROM_DCB(dcb);
431 struct atom_display_object_path_v2 *object;
432 struct atom_hpd_int_record *record = NULL;
433
434 if (!info)
435 return BP_RESULT_BADINPUT;
436
437 object = get_bios_object(bp, id);
438
439 if (!object)
440 return BP_RESULT_BADINPUT;
441
442 record = get_hpd_record(bp, object);
443
444 if (record != NULL) {
445 info->hpd_int_gpio_uid = record->pin_id;
446 info->hpd_active = record->plugin_pin_state;
447 return BP_RESULT_OK;
448 }
449
450 return BP_RESULT_NORECORD;
451 }
452
get_hpd_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)453 static struct atom_hpd_int_record *get_hpd_record(
454 struct bios_parser *bp,
455 struct atom_display_object_path_v2 *object)
456 {
457 struct atom_common_record_header *header;
458 uint32_t offset;
459
460 if (!object) {
461 BREAK_TO_DEBUGGER(); /* Invalid object */
462 return NULL;
463 }
464
465 offset = le16_to_cpu(object->disp_recordoffset)
466 + bp->object_info_tbl_offset;
467
468 for (;;) {
469 header = GET_IMAGE(struct atom_common_record_header, offset);
470
471 if (!header)
472 return NULL;
473
474 if (header->record_type == LAST_RECORD_TYPE ||
475 !header->record_size)
476 break;
477
478 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
479 && sizeof(struct atom_hpd_int_record) <=
480 header->record_size)
481 return (struct atom_hpd_int_record *) header;
482
483 offset += header->record_size;
484 }
485
486 return NULL;
487 }
488
489 /**
490 * bios_parser_get_gpio_pin_info
491 * Get GpioPin information of input gpio id
492 *
493 * @param gpio_id, GPIO ID
494 * @param info, GpioPin information structure
495 * @return Bios parser result code
496 * @note
497 * to get the GPIO PIN INFO, we need:
498 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
499 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
500 * to get the registerA offset/mask
501 */
bios_parser_get_gpio_pin_info(struct dc_bios * dcb,uint32_t gpio_id,struct gpio_pin_info * info)502 static enum bp_result bios_parser_get_gpio_pin_info(
503 struct dc_bios *dcb,
504 uint32_t gpio_id,
505 struct gpio_pin_info *info)
506 {
507 struct bios_parser *bp = BP_FROM_DCB(dcb);
508 struct atom_gpio_pin_lut_v2_1 *header;
509 uint32_t count = 0;
510 uint32_t i = 0;
511
512 if (!DATA_TABLES(gpio_pin_lut))
513 return BP_RESULT_BADBIOSTABLE;
514
515 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
516 DATA_TABLES(gpio_pin_lut));
517 if (!header)
518 return BP_RESULT_BADBIOSTABLE;
519
520 if (sizeof(struct atom_common_table_header) +
521 sizeof(struct atom_gpio_pin_assignment)
522 > le16_to_cpu(header->table_header.structuresize))
523 return BP_RESULT_BADBIOSTABLE;
524
525 if (header->table_header.content_revision != 1)
526 return BP_RESULT_UNSUPPORTED;
527
528 /* Temporary hard code gpio pin info */
529 #if defined(FOR_SIMNOW_BOOT)
530 {
531 struct atom_gpio_pin_assignment gpio_pin[8] = {
532 {0x5db5, 0, 0, 1, 0},
533 {0x5db5, 8, 8, 2, 0},
534 {0x5db5, 0x10, 0x10, 3, 0},
535 {0x5db5, 0x18, 0x14, 4, 0},
536 {0x5db5, 0x1A, 0x18, 5, 0},
537 {0x5db5, 0x1C, 0x1C, 6, 0},
538 };
539
540 count = 6;
541 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin));
542 }
543 #else
544 count = (le16_to_cpu(header->table_header.structuresize)
545 - sizeof(struct atom_common_table_header))
546 / sizeof(struct atom_gpio_pin_assignment);
547 #endif
548 for (i = 0; i < count; ++i) {
549 if (header->gpio_pin[i].gpio_id != gpio_id)
550 continue;
551
552 info->offset =
553 (uint32_t) le16_to_cpu(
554 header->gpio_pin[i].data_a_reg_index);
555 info->offset_y = info->offset + 2;
556 info->offset_en = info->offset + 1;
557 info->offset_mask = info->offset - 1;
558
559 info->mask = (uint32_t) (1 <<
560 header->gpio_pin[i].gpio_bitshift);
561 info->mask_y = info->mask + 2;
562 info->mask_en = info->mask + 1;
563 info->mask_mask = info->mask - 1;
564
565 return BP_RESULT_OK;
566 }
567
568 return BP_RESULT_NORECORD;
569 }
570
device_type_from_device_id(uint16_t device_id)571 static struct device_id device_type_from_device_id(uint16_t device_id)
572 {
573
574 struct device_id result_device_id;
575
576 result_device_id.raw_device_tag = device_id;
577
578 switch (device_id) {
579 case ATOM_DISPLAY_LCD1_SUPPORT:
580 result_device_id.device_type = DEVICE_TYPE_LCD;
581 result_device_id.enum_id = 1;
582 break;
583
584 case ATOM_DISPLAY_DFP1_SUPPORT:
585 result_device_id.device_type = DEVICE_TYPE_DFP;
586 result_device_id.enum_id = 1;
587 break;
588
589 case ATOM_DISPLAY_DFP2_SUPPORT:
590 result_device_id.device_type = DEVICE_TYPE_DFP;
591 result_device_id.enum_id = 2;
592 break;
593
594 case ATOM_DISPLAY_DFP3_SUPPORT:
595 result_device_id.device_type = DEVICE_TYPE_DFP;
596 result_device_id.enum_id = 3;
597 break;
598
599 case ATOM_DISPLAY_DFP4_SUPPORT:
600 result_device_id.device_type = DEVICE_TYPE_DFP;
601 result_device_id.enum_id = 4;
602 break;
603
604 case ATOM_DISPLAY_DFP5_SUPPORT:
605 result_device_id.device_type = DEVICE_TYPE_DFP;
606 result_device_id.enum_id = 5;
607 break;
608
609 case ATOM_DISPLAY_DFP6_SUPPORT:
610 result_device_id.device_type = DEVICE_TYPE_DFP;
611 result_device_id.enum_id = 6;
612 break;
613
614 default:
615 BREAK_TO_DEBUGGER(); /* Invalid device Id */
616 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
617 result_device_id.enum_id = 0;
618 }
619 return result_device_id;
620 }
621
bios_parser_get_device_tag(struct dc_bios * dcb,struct graphics_object_id connector_object_id,uint32_t device_tag_index,struct connector_device_tag_info * info)622 static enum bp_result bios_parser_get_device_tag(
623 struct dc_bios *dcb,
624 struct graphics_object_id connector_object_id,
625 uint32_t device_tag_index,
626 struct connector_device_tag_info *info)
627 {
628 struct bios_parser *bp = BP_FROM_DCB(dcb);
629 struct atom_display_object_path_v2 *object;
630
631 if (!info)
632 return BP_RESULT_BADINPUT;
633
634 /* getBiosObject will return MXM object */
635 object = get_bios_object(bp, connector_object_id);
636
637 if (!object) {
638 BREAK_TO_DEBUGGER(); /* Invalid object id */
639 return BP_RESULT_BADINPUT;
640 }
641
642 info->acpi_device = 0; /* BIOS no longer provides this */
643 info->dev_id = device_type_from_device_id(object->device_tag);
644
645 return BP_RESULT_OK;
646 }
647
get_ss_info_v4_1(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)648 static enum bp_result get_ss_info_v4_1(
649 struct bios_parser *bp,
650 uint32_t id,
651 uint32_t index,
652 struct spread_spectrum_info *ss_info)
653 {
654 enum bp_result result = BP_RESULT_OK;
655 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
656 struct atom_smu_info_v3_3 *smu_info = NULL;
657
658 if (!ss_info)
659 return BP_RESULT_BADINPUT;
660
661 if (!DATA_TABLES(dce_info))
662 return BP_RESULT_BADBIOSTABLE;
663
664 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
665 DATA_TABLES(dce_info));
666 if (!disp_cntl_tbl)
667 return BP_RESULT_BADBIOSTABLE;
668
669
670 ss_info->type.STEP_AND_DELAY_INFO = false;
671 ss_info->spread_percentage_divider = 1000;
672 /* BIOS no longer uses target clock. Always enable for now */
673 ss_info->target_clock_range = 0xffffffff;
674
675 switch (id) {
676 case AS_SIGNAL_TYPE_DVI:
677 ss_info->spread_spectrum_percentage =
678 disp_cntl_tbl->dvi_ss_percentage;
679 ss_info->spread_spectrum_range =
680 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
681 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
682 ss_info->type.CENTER_MODE = true;
683 break;
684 case AS_SIGNAL_TYPE_HDMI:
685 ss_info->spread_spectrum_percentage =
686 disp_cntl_tbl->hdmi_ss_percentage;
687 ss_info->spread_spectrum_range =
688 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
689 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
690 ss_info->type.CENTER_MODE = true;
691 break;
692 /* TODO LVDS not support anymore? */
693 case AS_SIGNAL_TYPE_DISPLAY_PORT:
694 ss_info->spread_spectrum_percentage =
695 disp_cntl_tbl->dp_ss_percentage;
696 ss_info->spread_spectrum_range =
697 disp_cntl_tbl->dp_ss_rate_10hz * 10;
698 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
699 ss_info->type.CENTER_MODE = true;
700 break;
701 case AS_SIGNAL_TYPE_GPU_PLL:
702 /* atom_firmware: DAL only get data from dce_info table.
703 * if data within smu_info is needed for DAL, VBIOS should
704 * copy it into dce_info
705 */
706 result = BP_RESULT_UNSUPPORTED;
707 break;
708 case AS_SIGNAL_TYPE_XGMI:
709 smu_info = GET_IMAGE(struct atom_smu_info_v3_3,
710 DATA_TABLES(smu_info));
711 if (!smu_info)
712 return BP_RESULT_BADBIOSTABLE;
713
714 ss_info->spread_spectrum_percentage =
715 smu_info->waflclk_ss_percentage;
716 ss_info->spread_spectrum_range =
717 smu_info->gpuclk_ss_rate_10hz * 10;
718 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
719 ss_info->type.CENTER_MODE = true;
720 break;
721 default:
722 result = BP_RESULT_UNSUPPORTED;
723 }
724
725 return result;
726 }
727
get_ss_info_v4_2(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)728 static enum bp_result get_ss_info_v4_2(
729 struct bios_parser *bp,
730 uint32_t id,
731 uint32_t index,
732 struct spread_spectrum_info *ss_info)
733 {
734 enum bp_result result = BP_RESULT_OK;
735 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
736 struct atom_smu_info_v3_1 *smu_info = NULL;
737
738 if (!ss_info)
739 return BP_RESULT_BADINPUT;
740
741 if (!DATA_TABLES(dce_info))
742 return BP_RESULT_BADBIOSTABLE;
743
744 if (!DATA_TABLES(smu_info))
745 return BP_RESULT_BADBIOSTABLE;
746
747 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
748 DATA_TABLES(dce_info));
749 if (!disp_cntl_tbl)
750 return BP_RESULT_BADBIOSTABLE;
751
752 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
753 if (!smu_info)
754 return BP_RESULT_BADBIOSTABLE;
755
756 ss_info->type.STEP_AND_DELAY_INFO = false;
757 ss_info->spread_percentage_divider = 1000;
758 /* BIOS no longer uses target clock. Always enable for now */
759 ss_info->target_clock_range = 0xffffffff;
760
761 switch (id) {
762 case AS_SIGNAL_TYPE_DVI:
763 ss_info->spread_spectrum_percentage =
764 disp_cntl_tbl->dvi_ss_percentage;
765 ss_info->spread_spectrum_range =
766 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
767 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
768 ss_info->type.CENTER_MODE = true;
769 break;
770 case AS_SIGNAL_TYPE_HDMI:
771 ss_info->spread_spectrum_percentage =
772 disp_cntl_tbl->hdmi_ss_percentage;
773 ss_info->spread_spectrum_range =
774 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
775 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
776 ss_info->type.CENTER_MODE = true;
777 break;
778 /* TODO LVDS not support anymore? */
779 case AS_SIGNAL_TYPE_DISPLAY_PORT:
780 ss_info->spread_spectrum_percentage =
781 smu_info->gpuclk_ss_percentage;
782 ss_info->spread_spectrum_range =
783 smu_info->gpuclk_ss_rate_10hz * 10;
784 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
785 ss_info->type.CENTER_MODE = true;
786 break;
787 case AS_SIGNAL_TYPE_GPU_PLL:
788 /* atom_firmware: DAL only get data from dce_info table.
789 * if data within smu_info is needed for DAL, VBIOS should
790 * copy it into dce_info
791 */
792 result = BP_RESULT_UNSUPPORTED;
793 break;
794 default:
795 result = BP_RESULT_UNSUPPORTED;
796 }
797
798 return result;
799 }
800
801 /**
802 * bios_parser_get_spread_spectrum_info
803 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
804 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
805 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
806 * ver 3.1,
807 * there is only one entry for each signal /ss id. However, there is
808 * no planning of supporting multiple spread Sprectum entry for EverGreen
809 * @param [in] this
810 * @param [in] signal, ASSignalType to be converted to info index
811 * @param [in] index, number of entries that match the converted info index
812 * @param [out] ss_info, sprectrum information structure,
813 * @return Bios parser result code
814 */
bios_parser_get_spread_spectrum_info(struct dc_bios * dcb,enum as_signal_type signal,uint32_t index,struct spread_spectrum_info * ss_info)815 static enum bp_result bios_parser_get_spread_spectrum_info(
816 struct dc_bios *dcb,
817 enum as_signal_type signal,
818 uint32_t index,
819 struct spread_spectrum_info *ss_info)
820 {
821 struct bios_parser *bp = BP_FROM_DCB(dcb);
822 enum bp_result result = BP_RESULT_UNSUPPORTED;
823 struct atom_common_table_header *header;
824 struct atom_data_revision tbl_revision;
825
826 if (!ss_info) /* check for bad input */
827 return BP_RESULT_BADINPUT;
828
829 if (!DATA_TABLES(dce_info))
830 return BP_RESULT_UNSUPPORTED;
831
832 header = GET_IMAGE(struct atom_common_table_header,
833 DATA_TABLES(dce_info));
834 get_atom_data_table_revision(header, &tbl_revision);
835
836 switch (tbl_revision.major) {
837 case 4:
838 switch (tbl_revision.minor) {
839 case 1:
840 return get_ss_info_v4_1(bp, signal, index, ss_info);
841 case 2:
842 case 3:
843 return get_ss_info_v4_2(bp, signal, index, ss_info);
844 default:
845 break;
846 }
847 break;
848 default:
849 break;
850 }
851 /* there can not be more then one entry for SS Info table */
852 return result;
853 }
854
get_embedded_panel_info_v2_1(struct bios_parser * bp,struct embedded_panel_info * info)855 static enum bp_result get_embedded_panel_info_v2_1(
856 struct bios_parser *bp,
857 struct embedded_panel_info *info)
858 {
859 struct lcd_info_v2_1 *lvds;
860
861 if (!info)
862 return BP_RESULT_BADINPUT;
863
864 if (!DATA_TABLES(lcd_info))
865 return BP_RESULT_UNSUPPORTED;
866
867 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
868
869 if (!lvds)
870 return BP_RESULT_BADBIOSTABLE;
871
872 /* TODO: previous vv1_3, should v2_1 */
873 if (!((lvds->table_header.format_revision == 2)
874 && (lvds->table_header.content_revision >= 1)))
875 return BP_RESULT_UNSUPPORTED;
876
877 memset(info, 0, sizeof(struct embedded_panel_info));
878
879 /* We need to convert from 10KHz units into KHz units */
880 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
881 /* usHActive does not include borders, according to VBIOS team */
882 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
883 /* usHBlanking_Time includes borders, so we should really be
884 * subtractingborders duing this translation, but LVDS generally
885 * doesn't have borders, so we should be okay leaving this as is for
886 * now. May need to revisit if we ever have LVDS with borders
887 */
888 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
889 /* usVActive does not include borders, according to VBIOS team*/
890 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
891 /* usVBlanking_Time includes borders, so we should really be
892 * subtracting borders duing this translation, but LVDS generally
893 * doesn't have borders, so we should be okay leaving this as is for
894 * now. May need to revisit if we ever have LVDS with borders
895 */
896 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
897 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
898 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
899 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
900 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
901 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
902 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
903
904 /* not provided by VBIOS */
905 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
906
907 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
908 & ATOM_HSYNC_POLARITY);
909 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
910 & ATOM_VSYNC_POLARITY);
911
912 /* not provided by VBIOS */
913 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
914
915 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
916 & ATOM_H_REPLICATIONBY2);
917 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
918 & ATOM_V_REPLICATIONBY2);
919 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
920 & ATOM_COMPOSITESYNC);
921 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
922
923 /* not provided by VBIOS*/
924 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
925 /* not provided by VBIOS*/
926 info->ss_id = 0;
927
928 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
929
930 return BP_RESULT_OK;
931 }
932
bios_parser_get_embedded_panel_info(struct dc_bios * dcb,struct embedded_panel_info * info)933 static enum bp_result bios_parser_get_embedded_panel_info(
934 struct dc_bios *dcb,
935 struct embedded_panel_info *info)
936 {
937 struct bios_parser
938 *bp = BP_FROM_DCB(dcb);
939 struct atom_common_table_header *header;
940 struct atom_data_revision tbl_revision;
941
942 if (!DATA_TABLES(lcd_info))
943 return BP_RESULT_FAILURE;
944
945 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
946
947 if (!header)
948 return BP_RESULT_BADBIOSTABLE;
949
950 get_atom_data_table_revision(header, &tbl_revision);
951
952 switch (tbl_revision.major) {
953 case 2:
954 switch (tbl_revision.minor) {
955 case 1:
956 return get_embedded_panel_info_v2_1(bp, info);
957 default:
958 break;
959 }
960 default:
961 break;
962 }
963
964 return BP_RESULT_FAILURE;
965 }
966
get_support_mask_for_device_id(struct device_id device_id)967 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
968 {
969 enum dal_device_type device_type = device_id.device_type;
970 uint32_t enum_id = device_id.enum_id;
971
972 switch (device_type) {
973 case DEVICE_TYPE_LCD:
974 switch (enum_id) {
975 case 1:
976 return ATOM_DISPLAY_LCD1_SUPPORT;
977 default:
978 break;
979 }
980 break;
981 case DEVICE_TYPE_DFP:
982 switch (enum_id) {
983 case 1:
984 return ATOM_DISPLAY_DFP1_SUPPORT;
985 case 2:
986 return ATOM_DISPLAY_DFP2_SUPPORT;
987 case 3:
988 return ATOM_DISPLAY_DFP3_SUPPORT;
989 case 4:
990 return ATOM_DISPLAY_DFP4_SUPPORT;
991 case 5:
992 return ATOM_DISPLAY_DFP5_SUPPORT;
993 case 6:
994 return ATOM_DISPLAY_DFP6_SUPPORT;
995 default:
996 break;
997 }
998 break;
999 default:
1000 break;
1001 }
1002
1003 /* Unidentified device ID, return empty support mask. */
1004 return 0;
1005 }
1006
bios_parser_is_device_id_supported(struct dc_bios * dcb,struct device_id id)1007 static bool bios_parser_is_device_id_supported(
1008 struct dc_bios *dcb,
1009 struct device_id id)
1010 {
1011 struct bios_parser *bp = BP_FROM_DCB(dcb);
1012
1013 uint32_t mask = get_support_mask_for_device_id(id);
1014
1015 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) &
1016 mask) != 0;
1017 }
1018
bios_parser_get_ss_entry_number(struct dc_bios * dcb,enum as_signal_type signal)1019 static uint32_t bios_parser_get_ss_entry_number(
1020 struct dc_bios *dcb,
1021 enum as_signal_type signal)
1022 {
1023 /* TODO: DAL2 atomfirmware implementation does not need this.
1024 * why DAL3 need this?
1025 */
1026 return 1;
1027 }
1028
bios_parser_transmitter_control(struct dc_bios * dcb,struct bp_transmitter_control * cntl)1029 static enum bp_result bios_parser_transmitter_control(
1030 struct dc_bios *dcb,
1031 struct bp_transmitter_control *cntl)
1032 {
1033 struct bios_parser *bp = BP_FROM_DCB(dcb);
1034
1035 if (!bp->cmd_tbl.transmitter_control)
1036 return BP_RESULT_FAILURE;
1037
1038 return bp->cmd_tbl.transmitter_control(bp, cntl);
1039 }
1040
bios_parser_encoder_control(struct dc_bios * dcb,struct bp_encoder_control * cntl)1041 static enum bp_result bios_parser_encoder_control(
1042 struct dc_bios *dcb,
1043 struct bp_encoder_control *cntl)
1044 {
1045 struct bios_parser *bp = BP_FROM_DCB(dcb);
1046
1047 if (!bp->cmd_tbl.dig_encoder_control)
1048 return BP_RESULT_FAILURE;
1049
1050 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1051 }
1052
bios_parser_set_pixel_clock(struct dc_bios * dcb,struct bp_pixel_clock_parameters * bp_params)1053 static enum bp_result bios_parser_set_pixel_clock(
1054 struct dc_bios *dcb,
1055 struct bp_pixel_clock_parameters *bp_params)
1056 {
1057 struct bios_parser *bp = BP_FROM_DCB(dcb);
1058
1059 if (!bp->cmd_tbl.set_pixel_clock)
1060 return BP_RESULT_FAILURE;
1061
1062 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1063 }
1064
bios_parser_set_dce_clock(struct dc_bios * dcb,struct bp_set_dce_clock_parameters * bp_params)1065 static enum bp_result bios_parser_set_dce_clock(
1066 struct dc_bios *dcb,
1067 struct bp_set_dce_clock_parameters *bp_params)
1068 {
1069 struct bios_parser *bp = BP_FROM_DCB(dcb);
1070
1071 if (!bp->cmd_tbl.set_dce_clock)
1072 return BP_RESULT_FAILURE;
1073
1074 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1075 }
1076
bios_parser_program_crtc_timing(struct dc_bios * dcb,struct bp_hw_crtc_timing_parameters * bp_params)1077 static enum bp_result bios_parser_program_crtc_timing(
1078 struct dc_bios *dcb,
1079 struct bp_hw_crtc_timing_parameters *bp_params)
1080 {
1081 struct bios_parser *bp = BP_FROM_DCB(dcb);
1082
1083 if (!bp->cmd_tbl.set_crtc_timing)
1084 return BP_RESULT_FAILURE;
1085
1086 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1087 }
1088
bios_parser_enable_crtc(struct dc_bios * dcb,enum controller_id id,bool enable)1089 static enum bp_result bios_parser_enable_crtc(
1090 struct dc_bios *dcb,
1091 enum controller_id id,
1092 bool enable)
1093 {
1094 struct bios_parser *bp = BP_FROM_DCB(dcb);
1095
1096 if (!bp->cmd_tbl.enable_crtc)
1097 return BP_RESULT_FAILURE;
1098
1099 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1100 }
1101
bios_parser_enable_disp_power_gating(struct dc_bios * dcb,enum controller_id controller_id,enum bp_pipe_control_action action)1102 static enum bp_result bios_parser_enable_disp_power_gating(
1103 struct dc_bios *dcb,
1104 enum controller_id controller_id,
1105 enum bp_pipe_control_action action)
1106 {
1107 struct bios_parser *bp = BP_FROM_DCB(dcb);
1108
1109 if (!bp->cmd_tbl.enable_disp_power_gating)
1110 return BP_RESULT_FAILURE;
1111
1112 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1113 action);
1114 }
1115
bios_parser_is_accelerated_mode(struct dc_bios * dcb)1116 static bool bios_parser_is_accelerated_mode(
1117 struct dc_bios *dcb)
1118 {
1119 return bios_is_accelerated_mode(dcb);
1120 }
1121
1122 /**
1123 * bios_parser_set_scratch_critical_state
1124 *
1125 * @brief
1126 * update critical state bit in VBIOS scratch register
1127 *
1128 * @param
1129 * bool - to set or reset state
1130 */
bios_parser_set_scratch_critical_state(struct dc_bios * dcb,bool state)1131 static void bios_parser_set_scratch_critical_state(
1132 struct dc_bios *dcb,
1133 bool state)
1134 {
1135 bios_set_scratch_critical_state(dcb, state);
1136 }
1137
bios_parser_get_firmware_info(struct dc_bios * dcb,struct dc_firmware_info * info)1138 static enum bp_result bios_parser_get_firmware_info(
1139 struct dc_bios *dcb,
1140 struct dc_firmware_info *info)
1141 {
1142 struct bios_parser *bp = BP_FROM_DCB(dcb);
1143 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1144 struct atom_common_table_header *header;
1145
1146 struct atom_data_revision revision;
1147
1148 if (info && DATA_TABLES(firmwareinfo)) {
1149 header = GET_IMAGE(struct atom_common_table_header,
1150 DATA_TABLES(firmwareinfo));
1151 get_atom_data_table_revision(header, &revision);
1152 switch (revision.major) {
1153 case 3:
1154 switch (revision.minor) {
1155 case 1:
1156 result = get_firmware_info_v3_1(bp, info);
1157 break;
1158 case 2:
1159 result = get_firmware_info_v3_2(bp, info);
1160 break;
1161 case 3:
1162 result = get_firmware_info_v3_2(bp, info);
1163 break;
1164 default:
1165 break;
1166 }
1167 break;
1168 default:
1169 break;
1170 }
1171 }
1172
1173 return result;
1174 }
1175
get_firmware_info_v3_1(struct bios_parser * bp,struct dc_firmware_info * info)1176 static enum bp_result get_firmware_info_v3_1(
1177 struct bios_parser *bp,
1178 struct dc_firmware_info *info)
1179 {
1180 struct atom_firmware_info_v3_1 *firmware_info;
1181 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1182
1183 if (!info)
1184 return BP_RESULT_BADINPUT;
1185
1186 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1187 DATA_TABLES(firmwareinfo));
1188
1189 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1190 DATA_TABLES(dce_info));
1191
1192 if (!firmware_info || !dce_info)
1193 return BP_RESULT_BADBIOSTABLE;
1194
1195 memset(info, 0, sizeof(*info));
1196
1197 /* Pixel clock pll information. */
1198 /* We need to convert from 10KHz units into KHz units */
1199 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1200 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1201
1202 /* 27MHz for Vega10: */
1203 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1204
1205 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1206 if (info->pll_info.crystal_frequency == 0)
1207 info->pll_info.crystal_frequency = 27000;
1208 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1209 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1210 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1211
1212 /* Get GPU PLL VCO Clock */
1213
1214 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1215 /* VBIOS gives in 10KHz */
1216 info->smu_gpu_pll_output_freq =
1217 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1218 }
1219
1220 info->oem_i2c_present = false;
1221
1222 return BP_RESULT_OK;
1223 }
1224
get_firmware_info_v3_2(struct bios_parser * bp,struct dc_firmware_info * info)1225 static enum bp_result get_firmware_info_v3_2(
1226 struct bios_parser *bp,
1227 struct dc_firmware_info *info)
1228 {
1229 struct atom_firmware_info_v3_2 *firmware_info;
1230 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1231 struct atom_common_table_header *header;
1232 struct atom_data_revision revision;
1233 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1234 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1235
1236 if (!info)
1237 return BP_RESULT_BADINPUT;
1238
1239 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1240 DATA_TABLES(firmwareinfo));
1241
1242 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1243 DATA_TABLES(dce_info));
1244
1245 if (!firmware_info || !dce_info)
1246 return BP_RESULT_BADBIOSTABLE;
1247
1248 memset(info, 0, sizeof(*info));
1249
1250 header = GET_IMAGE(struct atom_common_table_header,
1251 DATA_TABLES(smu_info));
1252 get_atom_data_table_revision(header, &revision);
1253
1254 if (revision.minor == 2) {
1255 /* Vega12 */
1256 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1257 DATA_TABLES(smu_info));
1258
1259 if (!smu_info_v3_2)
1260 return BP_RESULT_BADBIOSTABLE;
1261
1262 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1263 } else if (revision.minor == 3) {
1264 /* Vega20 */
1265 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1266 DATA_TABLES(smu_info));
1267
1268 if (!smu_info_v3_3)
1269 return BP_RESULT_BADBIOSTABLE;
1270
1271 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1272 }
1273
1274 // We need to convert from 10KHz units into KHz units.
1275 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1276
1277 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1278 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1279 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1280 if (info->pll_info.crystal_frequency == 0) {
1281 if (revision.minor == 2)
1282 info->pll_info.crystal_frequency = 27000;
1283 else if (revision.minor == 3)
1284 info->pll_info.crystal_frequency = 100000;
1285 }
1286 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1287 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1288 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1289
1290 /* Get GPU PLL VCO Clock */
1291 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1292 if (revision.minor == 2)
1293 info->smu_gpu_pll_output_freq =
1294 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1295 else if (revision.minor == 3)
1296 info->smu_gpu_pll_output_freq =
1297 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1298 }
1299
1300 if (firmware_info->board_i2c_feature_id == 0x2) {
1301 info->oem_i2c_present = true;
1302 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1303 } else {
1304 info->oem_i2c_present = false;
1305 }
1306
1307 return BP_RESULT_OK;
1308 }
1309
bios_parser_get_encoder_cap_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_encoder_cap_info * info)1310 static enum bp_result bios_parser_get_encoder_cap_info(
1311 struct dc_bios *dcb,
1312 struct graphics_object_id object_id,
1313 struct bp_encoder_cap_info *info)
1314 {
1315 struct bios_parser *bp = BP_FROM_DCB(dcb);
1316 struct atom_display_object_path_v2 *object;
1317 struct atom_encoder_caps_record *record = NULL;
1318
1319 if (!info)
1320 return BP_RESULT_BADINPUT;
1321
1322 object = get_bios_object(bp, object_id);
1323
1324 if (!object)
1325 return BP_RESULT_BADINPUT;
1326
1327 record = get_encoder_cap_record(bp, object);
1328 if (!record)
1329 return BP_RESULT_NORECORD;
1330
1331 info->DP_HBR2_CAP = (record->encodercaps &
1332 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
1333 info->DP_HBR2_EN = (record->encodercaps &
1334 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
1335 info->DP_HBR3_EN = (record->encodercaps &
1336 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
1337 info->HDMI_6GB_EN = (record->encodercaps &
1338 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
1339 info->DP_IS_USB_C = (record->encodercaps &
1340 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
1341
1342 return BP_RESULT_OK;
1343 }
1344
1345
get_encoder_cap_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)1346 static struct atom_encoder_caps_record *get_encoder_cap_record(
1347 struct bios_parser *bp,
1348 struct atom_display_object_path_v2 *object)
1349 {
1350 struct atom_common_record_header *header;
1351 uint32_t offset;
1352
1353 if (!object) {
1354 BREAK_TO_DEBUGGER(); /* Invalid object */
1355 return NULL;
1356 }
1357
1358 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
1359
1360 for (;;) {
1361 header = GET_IMAGE(struct atom_common_record_header, offset);
1362
1363 if (!header)
1364 return NULL;
1365
1366 offset += header->record_size;
1367
1368 if (header->record_type == LAST_RECORD_TYPE ||
1369 !header->record_size)
1370 break;
1371
1372 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
1373 continue;
1374
1375 if (sizeof(struct atom_encoder_caps_record) <=
1376 header->record_size)
1377 return (struct atom_encoder_caps_record *)header;
1378 }
1379
1380 return NULL;
1381 }
1382
1383 /*
1384 * get_integrated_info_v11
1385 *
1386 * @brief
1387 * Get V8 integrated BIOS information
1388 *
1389 * @param
1390 * bios_parser *bp - [in]BIOS parser handler to get master data table
1391 * integrated_info *info - [out] store and output integrated info
1392 *
1393 * @return
1394 * enum bp_result - BP_RESULT_OK if information is available,
1395 * BP_RESULT_BADBIOSTABLE otherwise.
1396 */
get_integrated_info_v11(struct bios_parser * bp,struct integrated_info * info)1397 static enum bp_result get_integrated_info_v11(
1398 struct bios_parser *bp,
1399 struct integrated_info *info)
1400 {
1401 struct atom_integrated_system_info_v1_11 *info_v11;
1402 uint32_t i;
1403
1404 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
1405 DATA_TABLES(integratedsysteminfo));
1406
1407 if (info_v11 == NULL)
1408 return BP_RESULT_BADBIOSTABLE;
1409
1410 info->gpu_cap_info =
1411 le32_to_cpu(info_v11->gpucapinfo);
1412 /*
1413 * system_config: Bit[0] = 0 : PCIE power gating disabled
1414 * = 1 : PCIE power gating enabled
1415 * Bit[1] = 0 : DDR-PLL shut down disabled
1416 * = 1 : DDR-PLL shut down enabled
1417 * Bit[2] = 0 : DDR-PLL power down disabled
1418 * = 1 : DDR-PLL power down enabled
1419 */
1420 info->system_config = le32_to_cpu(info_v11->system_config);
1421 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
1422 info->memory_type = info_v11->memorytype;
1423 info->ma_channel_number = info_v11->umachannelnumber;
1424 info->lvds_ss_percentage =
1425 le16_to_cpu(info_v11->lvds_ss_percentage);
1426 info->dp_ss_control =
1427 le16_to_cpu(info_v11->reserved1);
1428 info->lvds_sspread_rate_in_10hz =
1429 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
1430 info->hdmi_ss_percentage =
1431 le16_to_cpu(info_v11->hdmi_ss_percentage);
1432 info->hdmi_sspread_rate_in_10hz =
1433 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
1434 info->dvi_ss_percentage =
1435 le16_to_cpu(info_v11->dvi_ss_percentage);
1436 info->dvi_sspread_rate_in_10_hz =
1437 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
1438 info->lvds_misc = info_v11->lvds_misc;
1439 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
1440 info->ext_disp_conn_info.gu_id[i] =
1441 info_v11->extdispconninfo.guid[i];
1442 }
1443
1444 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
1445 info->ext_disp_conn_info.path[i].device_connector_id =
1446 object_id_from_bios_object_id(
1447 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
1448
1449 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
1450 object_id_from_bios_object_id(
1451 le16_to_cpu(
1452 info_v11->extdispconninfo.path[i].ext_encoder_objid));
1453
1454 info->ext_disp_conn_info.path[i].device_tag =
1455 le16_to_cpu(
1456 info_v11->extdispconninfo.path[i].device_tag);
1457 info->ext_disp_conn_info.path[i].device_acpi_enum =
1458 le16_to_cpu(
1459 info_v11->extdispconninfo.path[i].device_acpi_enum);
1460 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
1461 info_v11->extdispconninfo.path[i].auxddclut_index;
1462 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
1463 info_v11->extdispconninfo.path[i].hpdlut_index;
1464 info->ext_disp_conn_info.path[i].channel_mapping.raw =
1465 info_v11->extdispconninfo.path[i].channelmapping;
1466 info->ext_disp_conn_info.path[i].caps =
1467 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
1468 }
1469 info->ext_disp_conn_info.checksum =
1470 info_v11->extdispconninfo.checksum;
1471
1472 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
1473 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
1474 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
1475 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
1476 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1477 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
1478 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1479 }
1480 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
1481 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
1482 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1483 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1484 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1485 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1486 }
1487
1488 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
1489 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
1490 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
1491 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
1492 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1493 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
1494 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1495 }
1496 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
1497 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
1498 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1499 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1500 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1501 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1502 }
1503
1504 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
1505 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
1506 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
1507 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
1508 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1509 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
1510 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1511 }
1512 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
1513 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
1514 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1515 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1516 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1517 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1518 }
1519
1520 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
1521 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
1522 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
1523 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
1524 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1525 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
1526 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1527 }
1528 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
1529 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
1530 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1531 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1532 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1533 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1534 }
1535
1536
1537 /** TODO - review **/
1538 #if 0
1539 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
1540 * 10;
1541 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
1542 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
1543
1544 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1545 /* Convert [10KHz] into [KHz] */
1546 info->disp_clk_voltage[i].max_supported_clk =
1547 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
1548 ulMaximumSupportedCLK) * 10;
1549 info->disp_clk_voltage[i].voltage_index =
1550 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
1551 }
1552
1553 info->boot_up_req_display_vector =
1554 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
1555 info->boot_up_nb_voltage =
1556 le16_to_cpu(info_v11->usBootUpNBVoltage);
1557 info->ext_disp_conn_info_offset =
1558 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
1559 info->gmc_restore_reset_time =
1560 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
1561 info->minimum_n_clk =
1562 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
1563 for (i = 1; i < 4; ++i)
1564 info->minimum_n_clk =
1565 info->minimum_n_clk <
1566 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
1567 info->minimum_n_clk : le32_to_cpu(
1568 info_v11->ulNbpStateNClkFreq[i]);
1569
1570 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
1571 info->ddr_dll_power_up_time =
1572 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
1573 info->ddr_pll_power_up_time =
1574 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
1575 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
1576 info->max_lvds_pclk_freq_in_single_link =
1577 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1578 info->max_lvds_pclk_freq_in_single_link =
1579 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1580 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
1581 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
1582 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
1583 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
1584 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
1585 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
1586 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
1587 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
1588 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
1589 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
1590 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
1591 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
1592 info->lvds_off_to_on_delay_in_4ms =
1593 info_v11->ucLVDSOffToOnDelay_in4Ms;
1594 info->lvds_bit_depth_control_val =
1595 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
1596
1597 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
1598 /* Convert [10KHz] into [KHz] */
1599 info->avail_s_clk[i].supported_s_clk =
1600 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
1601 * 10;
1602 info->avail_s_clk[i].voltage_index =
1603 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
1604 info->avail_s_clk[i].voltage_id =
1605 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
1606 }
1607 #endif /* TODO*/
1608
1609 return BP_RESULT_OK;
1610 }
1611
1612
1613 /*
1614 * construct_integrated_info
1615 *
1616 * @brief
1617 * Get integrated BIOS information based on table revision
1618 *
1619 * @param
1620 * bios_parser *bp - [in]BIOS parser handler to get master data table
1621 * integrated_info *info - [out] store and output integrated info
1622 *
1623 * @return
1624 * enum bp_result - BP_RESULT_OK if information is available,
1625 * BP_RESULT_BADBIOSTABLE otherwise.
1626 */
construct_integrated_info(struct bios_parser * bp,struct integrated_info * info)1627 static enum bp_result construct_integrated_info(
1628 struct bios_parser *bp,
1629 struct integrated_info *info)
1630 {
1631 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1632
1633 struct atom_common_table_header *header;
1634 struct atom_data_revision revision;
1635 uint32_t i;
1636 uint32_t j;
1637
1638 if (info && DATA_TABLES(integratedsysteminfo)) {
1639 header = GET_IMAGE(struct atom_common_table_header,
1640 DATA_TABLES(integratedsysteminfo));
1641
1642 get_atom_data_table_revision(header, &revision);
1643
1644 /* Don't need to check major revision as they are all 1 */
1645 switch (revision.minor) {
1646 case 11:
1647 case 12:
1648 result = get_integrated_info_v11(bp, info);
1649 break;
1650 default:
1651 return result;
1652 }
1653 }
1654
1655 if (result != BP_RESULT_OK)
1656 return result;
1657
1658 /* Sort voltage table from low to high*/
1659 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1660 for (j = i; j > 0; --j) {
1661 if (info->disp_clk_voltage[j].max_supported_clk <
1662 info->disp_clk_voltage[j-1].max_supported_clk
1663 ) {
1664 /* swap j and j - 1*/
1665 swap(info->disp_clk_voltage[j - 1],
1666 info->disp_clk_voltage[j]);
1667 }
1668 }
1669 }
1670
1671 return result;
1672 }
1673
bios_parser_create_integrated_info(struct dc_bios * dcb)1674 static struct integrated_info *bios_parser_create_integrated_info(
1675 struct dc_bios *dcb)
1676 {
1677 struct bios_parser *bp = BP_FROM_DCB(dcb);
1678 struct integrated_info *info = NULL;
1679
1680 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
1681
1682 if (info == NULL) {
1683 ASSERT_CRITICAL(0);
1684 return NULL;
1685 }
1686
1687 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
1688 return info;
1689
1690 kfree(info);
1691
1692 return NULL;
1693 }
1694
update_slot_layout_info(struct dc_bios * dcb,unsigned int i,struct slot_layout_info * slot_layout_info)1695 static enum bp_result update_slot_layout_info(
1696 struct dc_bios *dcb,
1697 unsigned int i,
1698 struct slot_layout_info *slot_layout_info)
1699 {
1700 unsigned int record_offset;
1701 unsigned int j;
1702 struct atom_display_object_path_v2 *object;
1703 struct atom_bracket_layout_record *record;
1704 struct atom_common_record_header *record_header;
1705 enum bp_result result;
1706 struct bios_parser *bp;
1707 struct object_info_table *tbl;
1708 struct display_object_info_table_v1_4 *v1_4;
1709
1710 record = NULL;
1711 record_header = NULL;
1712 result = BP_RESULT_NORECORD;
1713
1714 bp = BP_FROM_DCB(dcb);
1715 tbl = &bp->object_info_tbl;
1716 v1_4 = tbl->v1_4;
1717
1718 object = &v1_4->display_path[i];
1719 record_offset = (unsigned int)
1720 (object->disp_recordoffset) +
1721 (unsigned int)(bp->object_info_tbl_offset);
1722
1723 for (;;) {
1724
1725 record_header = (struct atom_common_record_header *)
1726 GET_IMAGE(struct atom_common_record_header,
1727 record_offset);
1728 if (record_header == NULL) {
1729 result = BP_RESULT_BADBIOSTABLE;
1730 break;
1731 }
1732
1733 /* the end of the list */
1734 if (record_header->record_type == 0xff ||
1735 record_header->record_size == 0) {
1736 break;
1737 }
1738
1739 if (record_header->record_type ==
1740 ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
1741 sizeof(struct atom_bracket_layout_record)
1742 <= record_header->record_size) {
1743 record = (struct atom_bracket_layout_record *)
1744 (record_header);
1745 result = BP_RESULT_OK;
1746 break;
1747 }
1748
1749 record_offset += record_header->record_size;
1750 }
1751
1752 /* return if the record not found */
1753 if (result != BP_RESULT_OK)
1754 return result;
1755
1756 /* get slot sizes */
1757 slot_layout_info->length = record->bracketlen;
1758 slot_layout_info->width = record->bracketwidth;
1759
1760 /* get info for each connector in the slot */
1761 slot_layout_info->num_of_connectors = record->conn_num;
1762 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
1763 slot_layout_info->connectors[j].connector_type =
1764 (enum connector_layout_type)
1765 (record->conn_info[j].connector_type);
1766 switch (record->conn_info[j].connector_type) {
1767 case CONNECTOR_TYPE_DVI_D:
1768 slot_layout_info->connectors[j].connector_type =
1769 CONNECTOR_LAYOUT_TYPE_DVI_D;
1770 slot_layout_info->connectors[j].length =
1771 CONNECTOR_SIZE_DVI;
1772 break;
1773
1774 case CONNECTOR_TYPE_HDMI:
1775 slot_layout_info->connectors[j].connector_type =
1776 CONNECTOR_LAYOUT_TYPE_HDMI;
1777 slot_layout_info->connectors[j].length =
1778 CONNECTOR_SIZE_HDMI;
1779 break;
1780
1781 case CONNECTOR_TYPE_DISPLAY_PORT:
1782 slot_layout_info->connectors[j].connector_type =
1783 CONNECTOR_LAYOUT_TYPE_DP;
1784 slot_layout_info->connectors[j].length =
1785 CONNECTOR_SIZE_DP;
1786 break;
1787
1788 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
1789 slot_layout_info->connectors[j].connector_type =
1790 CONNECTOR_LAYOUT_TYPE_MINI_DP;
1791 slot_layout_info->connectors[j].length =
1792 CONNECTOR_SIZE_MINI_DP;
1793 break;
1794
1795 default:
1796 slot_layout_info->connectors[j].connector_type =
1797 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
1798 slot_layout_info->connectors[j].length =
1799 CONNECTOR_SIZE_UNKNOWN;
1800 }
1801
1802 slot_layout_info->connectors[j].position =
1803 record->conn_info[j].position;
1804 slot_layout_info->connectors[j].connector_id =
1805 object_id_from_bios_object_id(
1806 record->conn_info[j].connectorobjid);
1807 }
1808 return result;
1809 }
1810
1811
get_bracket_layout_record(struct dc_bios * dcb,unsigned int bracket_layout_id,struct slot_layout_info * slot_layout_info)1812 static enum bp_result get_bracket_layout_record(
1813 struct dc_bios *dcb,
1814 unsigned int bracket_layout_id,
1815 struct slot_layout_info *slot_layout_info)
1816 {
1817 unsigned int i;
1818 struct bios_parser *bp = BP_FROM_DCB(dcb);
1819 enum bp_result result;
1820 struct object_info_table *tbl;
1821 struct display_object_info_table_v1_4 *v1_4;
1822
1823 if (slot_layout_info == NULL) {
1824 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
1825 return BP_RESULT_BADINPUT;
1826 }
1827 tbl = &bp->object_info_tbl;
1828 v1_4 = tbl->v1_4;
1829
1830 result = BP_RESULT_NORECORD;
1831 for (i = 0; i < v1_4->number_of_path; ++i) {
1832
1833 if (bracket_layout_id ==
1834 v1_4->display_path[i].display_objid) {
1835 result = update_slot_layout_info(dcb, i,
1836 slot_layout_info);
1837 break;
1838 }
1839 }
1840 return result;
1841 }
1842
bios_get_board_layout_info(struct dc_bios * dcb,struct board_layout_info * board_layout_info)1843 static enum bp_result bios_get_board_layout_info(
1844 struct dc_bios *dcb,
1845 struct board_layout_info *board_layout_info)
1846 {
1847 unsigned int i;
1848 enum bp_result record_result;
1849
1850 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
1851 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
1852 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
1853 0, 0
1854 };
1855
1856 if (board_layout_info == NULL) {
1857 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
1858 return BP_RESULT_BADINPUT;
1859 }
1860
1861 board_layout_info->num_of_slots = 0;
1862
1863 for (i = 0; i < MAX_BOARD_SLOTS; ++i) {
1864 record_result = get_bracket_layout_record(dcb,
1865 slot_index_to_vbios_id[i],
1866 &board_layout_info->slots[i]);
1867
1868 if (record_result == BP_RESULT_NORECORD && i > 0)
1869 break; /* no more slots present in bios */
1870 else if (record_result != BP_RESULT_OK)
1871 return record_result; /* fail */
1872
1873 ++board_layout_info->num_of_slots;
1874 }
1875
1876 /* all data is valid */
1877 board_layout_info->is_number_of_slots_valid = 1;
1878 board_layout_info->is_slots_size_valid = 1;
1879 board_layout_info->is_connector_offsets_valid = 1;
1880 board_layout_info->is_connector_lengths_valid = 1;
1881
1882 return BP_RESULT_OK;
1883 }
1884
1885 static const struct dc_vbios_funcs vbios_funcs = {
1886 .get_connectors_number = bios_parser_get_connectors_number,
1887
1888 .get_connector_id = bios_parser_get_connector_id,
1889
1890 .get_src_obj = bios_parser_get_src_obj,
1891
1892 .get_i2c_info = bios_parser_get_i2c_info,
1893
1894 .get_hpd_info = bios_parser_get_hpd_info,
1895
1896 .get_device_tag = bios_parser_get_device_tag,
1897
1898 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
1899
1900 .get_ss_entry_number = bios_parser_get_ss_entry_number,
1901
1902 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
1903
1904 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
1905
1906 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
1907
1908 .is_device_id_supported = bios_parser_is_device_id_supported,
1909
1910 .is_accelerated_mode = bios_parser_is_accelerated_mode,
1911
1912 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
1913
1914
1915 /* COMMANDS */
1916 .encoder_control = bios_parser_encoder_control,
1917
1918 .transmitter_control = bios_parser_transmitter_control,
1919
1920 .enable_crtc = bios_parser_enable_crtc,
1921
1922 .set_pixel_clock = bios_parser_set_pixel_clock,
1923
1924 .set_dce_clock = bios_parser_set_dce_clock,
1925
1926 .program_crtc_timing = bios_parser_program_crtc_timing,
1927
1928 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
1929
1930 .bios_parser_destroy = firmware_parser_destroy,
1931
1932 .get_board_layout_info = bios_get_board_layout_info,
1933 };
1934
bios_parser2_construct(struct bios_parser * bp,struct bp_init_data * init,enum dce_version dce_version)1935 static bool bios_parser2_construct(
1936 struct bios_parser *bp,
1937 struct bp_init_data *init,
1938 enum dce_version dce_version)
1939 {
1940 uint16_t *rom_header_offset = NULL;
1941 struct atom_rom_header_v2_2 *rom_header = NULL;
1942 struct display_object_info_table_v1_4 *object_info_tbl;
1943 struct atom_data_revision tbl_rev = {0};
1944
1945 if (!init)
1946 return false;
1947
1948 if (!init->bios)
1949 return false;
1950
1951 bp->base.funcs = &vbios_funcs;
1952 bp->base.bios = init->bios;
1953 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
1954
1955 bp->base.ctx = init->ctx;
1956
1957 bp->base.bios_local_image = NULL;
1958
1959 rom_header_offset =
1960 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
1961
1962 if (!rom_header_offset)
1963 return false;
1964
1965 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
1966
1967 if (!rom_header)
1968 return false;
1969
1970 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
1971 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
1972 return false;
1973
1974 bp->master_data_tbl =
1975 GET_IMAGE(struct atom_master_data_table_v2_1,
1976 rom_header->masterdatatable_offset);
1977
1978 if (!bp->master_data_tbl)
1979 return false;
1980
1981 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
1982
1983 if (!bp->object_info_tbl_offset)
1984 return false;
1985
1986 object_info_tbl =
1987 GET_IMAGE(struct display_object_info_table_v1_4,
1988 bp->object_info_tbl_offset);
1989
1990 if (!object_info_tbl)
1991 return false;
1992
1993 get_atom_data_table_revision(&object_info_tbl->table_header,
1994 &bp->object_info_tbl.revision);
1995
1996 if (bp->object_info_tbl.revision.major == 1
1997 && bp->object_info_tbl.revision.minor >= 4) {
1998 struct display_object_info_table_v1_4 *tbl_v1_4;
1999
2000 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
2001 bp->object_info_tbl_offset);
2002 if (!tbl_v1_4)
2003 return false;
2004
2005 bp->object_info_tbl.v1_4 = tbl_v1_4;
2006 } else
2007 return false;
2008
2009 dal_firmware_parser_init_cmd_tbl(bp);
2010 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
2011
2012 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
2013 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
2014
2015 return true;
2016 }
2017
firmware_parser_create(struct bp_init_data * init,enum dce_version dce_version)2018 struct dc_bios *firmware_parser_create(
2019 struct bp_init_data *init,
2020 enum dce_version dce_version)
2021 {
2022 struct bios_parser *bp = NULL;
2023
2024 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
2025 if (!bp)
2026 return NULL;
2027
2028 if (bios_parser2_construct(bp, init, dce_version))
2029 return &bp->base;
2030
2031 kfree(bp);
2032 return NULL;
2033 }
2034
2035
2036