xref: /llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp (revision bded8890149e55b9abc9c32cb4a9c883c3daad91) 
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -emit-llvm -o - %s | FileCheck %s
3 
4 // CHECK-LABEL: define dso_local void @_Z11test_localsv
5 // CHECK-SAME: () #[[ATTR0:[0-9]+]] {
6 // CHECK-NEXT:  entry:
7 // CHECK-NEXT:    [[S8:%.*]] = alloca <vscale x 16 x i8>, align 16
8 // CHECK-NEXT:    [[S16:%.*]] = alloca <vscale x 8 x i16>, align 16
9 // CHECK-NEXT:    [[S32:%.*]] = alloca <vscale x 4 x i32>, align 16
10 // CHECK-NEXT:    [[S64:%.*]] = alloca <vscale x 2 x i64>, align 16
11 // CHECK-NEXT:    [[U8:%.*]] = alloca <vscale x 16 x i8>, align 16
12 // CHECK-NEXT:    [[U16:%.*]] = alloca <vscale x 8 x i16>, align 16
13 // CHECK-NEXT:    [[U32:%.*]] = alloca <vscale x 4 x i32>, align 16
14 // CHECK-NEXT:    [[U64:%.*]] = alloca <vscale x 2 x i64>, align 16
15 // CHECK-NEXT:    [[MF8:%.*]] = alloca <vscale x 16 x i8>, align 16
16 // CHECK-NEXT:    [[F16:%.*]] = alloca <vscale x 8 x half>, align 16
17 // CHECK-NEXT:    [[F32:%.*]] = alloca <vscale x 4 x float>, align 16
18 // CHECK-NEXT:    [[F64:%.*]] = alloca <vscale x 2 x double>, align 16
19 // CHECK-NEXT:    [[BF16:%.*]] = alloca <vscale x 8 x bfloat>, align 16
20 // CHECK-NEXT:    [[S8X2:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
21 // CHECK-NEXT:    [[S16X2:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
22 // CHECK-NEXT:    [[S32X2:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
23 // CHECK-NEXT:    [[X64X2:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
24 // CHECK-NEXT:    [[U8X2:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
25 // CHECK-NEXT:    [[U16X2:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
26 // CHECK-NEXT:    [[U32X2:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
27 // CHECK-NEXT:    [[U64X2:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
28 // CHECK-NEXT:    [[F16X2:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
29 // CHECK-NEXT:    [[F32X2:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
30 // CHECK-NEXT:    [[F64X2:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
31 // CHECK-NEXT:    [[BF16X2:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
32 // CHECK-NEXT:    [[S8X3:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
33 // CHECK-NEXT:    [[S16X3:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
34 // CHECK-NEXT:    [[S32X3:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
35 // CHECK-NEXT:    [[X64X3:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
36 // CHECK-NEXT:    [[U8X3:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
37 // CHECK-NEXT:    [[U16X3:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
38 // CHECK-NEXT:    [[U32X3:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
39 // CHECK-NEXT:    [[U64X3:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
40 // CHECK-NEXT:    [[F16X3:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
41 // CHECK-NEXT:    [[F32X3:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
42 // CHECK-NEXT:    [[F64X3:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 16
43 // CHECK-NEXT:    [[BF16X3:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
44 // CHECK-NEXT:    [[S8X4:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
45 // CHECK-NEXT:    [[S16X4:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
46 // CHECK-NEXT:    [[S32X4:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
47 // CHECK-NEXT:    [[X64X4:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
48 // CHECK-NEXT:    [[U8X4:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
49 // CHECK-NEXT:    [[U16X4:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
50 // CHECK-NEXT:    [[U32X4:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
51 // CHECK-NEXT:    [[U64X4:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
52 // CHECK-NEXT:    [[F16X4:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
53 // CHECK-NEXT:    [[F32X4:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
54 // CHECK-NEXT:    [[F64X4:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 16
55 // CHECK-NEXT:    [[BF16X4:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
56 // CHECK-NEXT:    [[B8:%.*]] = alloca <vscale x 16 x i1>, align 2
57 // CHECK-NEXT:    [[B8X2:%.*]] = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
58 // CHECK-NEXT:    [[B8X4:%.*]] = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
59 // CHECK-NEXT:    [[CNT:%.*]] = alloca target("aarch64.svcount"), align 2
60 // CHECK-NEXT:    [[MF8X2:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
61 // CHECK-NEXT:    [[MF8X3:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
62 // CHECK-NEXT:    [[MF8X4:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
63 // CHECK-NEXT:    store <vscale x 16 x i8> zeroinitializer, ptr [[S8]], align 16
64 // CHECK-NEXT:    store <vscale x 8 x i16> zeroinitializer, ptr [[S16]], align 16
65 // CHECK-NEXT:    store <vscale x 4 x i32> zeroinitializer, ptr [[S32]], align 16
66 // CHECK-NEXT:    store <vscale x 2 x i64> zeroinitializer, ptr [[S64]], align 16
67 // CHECK-NEXT:    store <vscale x 16 x i8> zeroinitializer, ptr [[U8]], align 16
68 // CHECK-NEXT:    store <vscale x 8 x i16> zeroinitializer, ptr [[U16]], align 16
69 // CHECK-NEXT:    store <vscale x 4 x i32> zeroinitializer, ptr [[U32]], align 16
70 // CHECK-NEXT:    store <vscale x 2 x i64> zeroinitializer, ptr [[U64]], align 16
71 // CHECK-NEXT:    store <vscale x 16 x i8> zeroinitializer, ptr [[MF8]], align 16
72 // CHECK-NEXT:    store <vscale x 8 x half> zeroinitializer, ptr [[F16]], align 16
73 // CHECK-NEXT:    store <vscale x 4 x float> zeroinitializer, ptr [[F32]], align 16
74 // CHECK-NEXT:    store <vscale x 2 x double> zeroinitializer, ptr [[F64]], align 16
75 // CHECK-NEXT:    store <vscale x 8 x bfloat> zeroinitializer, ptr [[BF16]], align 16
76 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } zeroinitializer, ptr [[S8X2]], align 16
77 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16> } zeroinitializer, ptr [[S16X2]], align 16
78 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32> } zeroinitializer, ptr [[S32X2]], align 16
79 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64> } zeroinitializer, ptr [[X64X2]], align 16
80 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } zeroinitializer, ptr [[U8X2]], align 16
81 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16> } zeroinitializer, ptr [[U16X2]], align 16
82 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32> } zeroinitializer, ptr [[U32X2]], align 16
83 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64> } zeroinitializer, ptr [[U64X2]], align 16
84 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half> } zeroinitializer, ptr [[F16X2]], align 16
85 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float> } zeroinitializer, ptr [[F32X2]], align 16
86 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double> } zeroinitializer, ptr [[F64X2]], align 16
87 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } zeroinitializer, ptr [[BF16X2]], align 16
88 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } zeroinitializer, ptr [[S8X3]], align 16
89 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } zeroinitializer, ptr [[S16X3]], align 16
90 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } zeroinitializer, ptr [[S32X3]], align 16
91 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } zeroinitializer, ptr [[X64X3]], align 16
92 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } zeroinitializer, ptr [[U8X3]], align 16
93 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } zeroinitializer, ptr [[U16X3]], align 16
94 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } zeroinitializer, ptr [[U32X3]], align 16
95 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } zeroinitializer, ptr [[U64X3]], align 16
96 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } zeroinitializer, ptr [[F16X3]], align 16
97 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } zeroinitializer, ptr [[F32X3]], align 16
98 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } zeroinitializer, ptr [[F64X3]], align 16
99 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } zeroinitializer, ptr [[BF16X3]], align 16
100 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } zeroinitializer, ptr [[S8X4]], align 16
101 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } zeroinitializer, ptr [[S16X4]], align 16
102 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } zeroinitializer, ptr [[S32X4]], align 16
103 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } zeroinitializer, ptr [[X64X4]], align 16
104 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } zeroinitializer, ptr [[U8X4]], align 16
105 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } zeroinitializer, ptr [[U16X4]], align 16
106 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } zeroinitializer, ptr [[U32X4]], align 16
107 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } zeroinitializer, ptr [[U64X4]], align 16
108 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } zeroinitializer, ptr [[F16X4]], align 16
109 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } zeroinitializer, ptr [[F32X4]], align 16
110 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } zeroinitializer, ptr [[F64X4]], align 16
111 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } zeroinitializer, ptr [[BF16X4]], align 16
112 // CHECK-NEXT:    store <vscale x 16 x i1> zeroinitializer, ptr [[B8]], align 2
113 // CHECK-NEXT:    store { <vscale x 16 x i1>, <vscale x 16 x i1> } zeroinitializer, ptr [[B8X2]], align 2
114 // CHECK-NEXT:    store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } zeroinitializer, ptr [[B8X4]], align 2
115 // CHECK-NEXT:    store target("aarch64.svcount") zeroinitializer, ptr [[CNT]], align 2
116 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } zeroinitializer, ptr [[MF8X2]], align 16
117 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } zeroinitializer, ptr [[MF8X3]], align 16
118 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } zeroinitializer, ptr [[MF8X4]], align 16
119 // CHECK-NEXT:    ret void
120 //
121 void test_locals(void) {
122   __SVInt8_t s8{};
123   __SVInt16_t s16{};
124   __SVInt32_t s32{};
125   __SVInt64_t s64{};
126   __SVUint8_t u8{};
127   __SVUint16_t u16{};
128   __SVUint32_t u32{};
129   __SVUint64_t u64{};
130   __SVMfloat8_t mf8{};
131   __SVFloat16_t f16{};
132   __SVFloat32_t f32{};
133   __SVFloat64_t f64{};
134   __SVBfloat16_t bf16{};
135 
136   __clang_svint8x2_t s8x2{};
137   __clang_svint16x2_t s16x2{};
138   __clang_svint32x2_t s32x2{};
139   __clang_svint64x2_t x64x2{};
140   __clang_svuint8x2_t u8x2{};
141   __clang_svuint16x2_t u16x2{};
142   __clang_svuint32x2_t u32x2{};
143   __clang_svuint64x2_t u64x2{};
144   __clang_svfloat16x2_t f16x2{};
145   __clang_svfloat32x2_t f32x2{};
146   __clang_svfloat64x2_t f64x2{};
147   __clang_svbfloat16x2_t bf16x2{};
148 
149   __clang_svint8x3_t s8x3{};
150   __clang_svint16x3_t s16x3{};
151   __clang_svint32x3_t s32x3{};
152   __clang_svint64x3_t x64x3{};
153   __clang_svuint8x3_t u8x3{};
154   __clang_svuint16x3_t u16x3{};
155   __clang_svuint32x3_t u32x3{};
156   __clang_svuint64x3_t u64x3{};
157   __clang_svfloat16x3_t f16x3{};
158   __clang_svfloat32x3_t f32x3{};
159   __clang_svfloat64x3_t f64x3{};
160   __clang_svbfloat16x3_t bf16x3{};
161 
162   __clang_svint8x4_t s8x4{};
163   __clang_svint16x4_t s16x4{};
164   __clang_svint32x4_t s32x4{};
165   __clang_svint64x4_t x64x4{};
166   __clang_svuint8x4_t u8x4{};
167   __clang_svuint16x4_t u16x4{};
168   __clang_svuint32x4_t u32x4{};
169   __clang_svuint64x4_t u64x4{};
170   __clang_svfloat16x4_t f16x4{};
171   __clang_svfloat32x4_t f32x4{};
172   __clang_svfloat64x4_t f64x4{};
173   __clang_svbfloat16x4_t bf16x4{};
174 
175   __SVBool_t b8{};
176   __clang_svboolx2_t b8x2{};
177   __clang_svboolx4_t b8x4{};
178 
179   __SVCount_t cnt{};
180 
181   __clang_svmfloat8x2_t mf8x2{};
182   __clang_svmfloat8x3_t mf8x3{};
183   __clang_svmfloat8x4_t mf8x4{};
184 }
185 
186 // CHECK-LABEL: define dso_local void @_Z12test_copy_s8u10__SVInt8_t
187 // CHECK-SAME: (<vscale x 16 x i8> [[A:%.*]]) #[[ATTR0]] {
188 // CHECK-NEXT:  entry:
189 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 16 x i8>, align 16
190 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 16 x i8>, align 16
191 // CHECK-NEXT:    store <vscale x 16 x i8> [[A]], ptr [[A_ADDR]], align 16
192 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 16 x i8>, ptr [[A_ADDR]], align 16
193 // CHECK-NEXT:    store <vscale x 16 x i8> [[TMP0]], ptr [[B]], align 16
194 // CHECK-NEXT:    ret void
195 //
196 void test_copy_s8(__SVInt8_t a) {
197   __SVInt8_t b{a};
198 }
199 
200 // CHECK-LABEL: define dso_local void @_Z13test_copy_s16u11__SVInt16_t
201 // CHECK-SAME: (<vscale x 8 x i16> [[A:%.*]]) #[[ATTR0]] {
202 // CHECK-NEXT:  entry:
203 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 8 x i16>, align 16
204 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 8 x i16>, align 16
205 // CHECK-NEXT:    store <vscale x 8 x i16> [[A]], ptr [[A_ADDR]], align 16
206 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 8 x i16>, ptr [[A_ADDR]], align 16
207 // CHECK-NEXT:    store <vscale x 8 x i16> [[TMP0]], ptr [[B]], align 16
208 // CHECK-NEXT:    ret void
209 //
210 void test_copy_s16(__SVInt16_t a) {
211   __SVInt16_t b{a};
212 }
213 
214 // CHECK-LABEL: define dso_local void @_Z13test_copy_s32u11__SVInt32_t
215 // CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {
216 // CHECK-NEXT:  entry:
217 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 4 x i32>, align 16
218 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 4 x i32>, align 16
219 // CHECK-NEXT:    store <vscale x 4 x i32> [[A]], ptr [[A_ADDR]], align 16
220 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 4 x i32>, ptr [[A_ADDR]], align 16
221 // CHECK-NEXT:    store <vscale x 4 x i32> [[TMP0]], ptr [[B]], align 16
222 // CHECK-NEXT:    ret void
223 //
224 void test_copy_s32(__SVInt32_t a) {
225   __SVInt32_t b{a};
226 }
227 
228 // CHECK-LABEL: define dso_local void @_Z13test_copy_s64u11__SVInt64_t
229 // CHECK-SAME: (<vscale x 2 x i64> [[A:%.*]]) #[[ATTR0]] {
230 // CHECK-NEXT:  entry:
231 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 2 x i64>, align 16
232 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 2 x i64>, align 16
233 // CHECK-NEXT:    store <vscale x 2 x i64> [[A]], ptr [[A_ADDR]], align 16
234 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 2 x i64>, ptr [[A_ADDR]], align 16
235 // CHECK-NEXT:    store <vscale x 2 x i64> [[TMP0]], ptr [[B]], align 16
236 // CHECK-NEXT:    ret void
237 //
238 void test_copy_s64(__SVInt64_t a) {
239   __SVInt64_t b{a};
240 }
241 
242 // CHECK-LABEL: define dso_local void @_Z12test_copy_u8u11__SVUint8_t
243 // CHECK-SAME: (<vscale x 16 x i8> [[A:%.*]]) #[[ATTR0]] {
244 // CHECK-NEXT:  entry:
245 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 16 x i8>, align 16
246 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 16 x i8>, align 16
247 // CHECK-NEXT:    store <vscale x 16 x i8> [[A]], ptr [[A_ADDR]], align 16
248 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 16 x i8>, ptr [[A_ADDR]], align 16
249 // CHECK-NEXT:    store <vscale x 16 x i8> [[TMP0]], ptr [[B]], align 16
250 // CHECK-NEXT:    ret void
251 //
252 void test_copy_u8(__SVUint8_t a) {
253   __SVUint8_t b{a};
254 }
255 
256 // CHECK-LABEL: define dso_local void @_Z13test_copy_u16u12__SVUint16_t
257 // CHECK-SAME: (<vscale x 8 x i16> [[A:%.*]]) #[[ATTR0]] {
258 // CHECK-NEXT:  entry:
259 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 8 x i16>, align 16
260 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 8 x i16>, align 16
261 // CHECK-NEXT:    store <vscale x 8 x i16> [[A]], ptr [[A_ADDR]], align 16
262 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 8 x i16>, ptr [[A_ADDR]], align 16
263 // CHECK-NEXT:    store <vscale x 8 x i16> [[TMP0]], ptr [[B]], align 16
264 // CHECK-NEXT:    ret void
265 //
266 void test_copy_u16(__SVUint16_t a) {
267   __SVUint16_t b{a};
268 }
269 
270 // CHECK-LABEL: define dso_local void @_Z13test_copy_u32u12__SVUint32_t
271 // CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {
272 // CHECK-NEXT:  entry:
273 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 4 x i32>, align 16
274 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 4 x i32>, align 16
275 // CHECK-NEXT:    store <vscale x 4 x i32> [[A]], ptr [[A_ADDR]], align 16
276 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 4 x i32>, ptr [[A_ADDR]], align 16
277 // CHECK-NEXT:    store <vscale x 4 x i32> [[TMP0]], ptr [[B]], align 16
278 // CHECK-NEXT:    ret void
279 //
280 void test_copy_u32(__SVUint32_t a) {
281   __SVUint32_t b{a};
282 }
283 
284 // CHECK-LABEL: define dso_local void @_Z13test_copy_u64u12__SVUint64_t
285 // CHECK-SAME: (<vscale x 2 x i64> [[A:%.*]]) #[[ATTR0]] {
286 // CHECK-NEXT:  entry:
287 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 2 x i64>, align 16
288 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 2 x i64>, align 16
289 // CHECK-NEXT:    store <vscale x 2 x i64> [[A]], ptr [[A_ADDR]], align 16
290 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 2 x i64>, ptr [[A_ADDR]], align 16
291 // CHECK-NEXT:    store <vscale x 2 x i64> [[TMP0]], ptr [[B]], align 16
292 // CHECK-NEXT:    ret void
293 //
294 void test_copy_u64(__SVUint64_t a) {
295   __SVUint64_t b{a};
296 }
297 
298 // CHECK-LABEL: define dso_local void @_Z13test_copy_mf8u13__SVMfloat8_t
299 // CHECK-SAME: (<vscale x 16 x i8> [[A:%.*]]) #[[ATTR0]] {
300 // CHECK-NEXT:  entry:
301 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 16 x i8>, align 16
302 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 16 x i8>, align 16
303 // CHECK-NEXT:    store <vscale x 16 x i8> [[A]], ptr [[A_ADDR]], align 16
304 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 16 x i8>, ptr [[A_ADDR]], align 16
305 // CHECK-NEXT:    store <vscale x 16 x i8> [[TMP0]], ptr [[B]], align 16
306 // CHECK-NEXT:    ret void
307 //
308 void test_copy_mf8(__SVMfloat8_t a) {
309   __SVMfloat8_t b{a};
310 }
311 
312 // CHECK-LABEL: define dso_local void @_Z13test_copy_f16u13__SVFloat16_t
313 // CHECK-SAME: (<vscale x 8 x half> [[A:%.*]]) #[[ATTR0]] {
314 // CHECK-NEXT:  entry:
315 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 8 x half>, align 16
316 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 8 x half>, align 16
317 // CHECK-NEXT:    store <vscale x 8 x half> [[A]], ptr [[A_ADDR]], align 16
318 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 8 x half>, ptr [[A_ADDR]], align 16
319 // CHECK-NEXT:    store <vscale x 8 x half> [[TMP0]], ptr [[B]], align 16
320 // CHECK-NEXT:    ret void
321 //
322 void test_copy_f16(__SVFloat16_t a) {
323   __SVFloat16_t b{a};
324 }
325 
326 // CHECK-LABEL: define dso_local void @_Z13test_copy_f32u13__SVFloat32_t
327 // CHECK-SAME: (<vscale x 4 x float> [[A:%.*]]) #[[ATTR0]] {
328 // CHECK-NEXT:  entry:
329 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 4 x float>, align 16
330 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 4 x float>, align 16
331 // CHECK-NEXT:    store <vscale x 4 x float> [[A]], ptr [[A_ADDR]], align 16
332 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 4 x float>, ptr [[A_ADDR]], align 16
333 // CHECK-NEXT:    store <vscale x 4 x float> [[TMP0]], ptr [[B]], align 16
334 // CHECK-NEXT:    ret void
335 //
336 void test_copy_f32(__SVFloat32_t a) {
337   __SVFloat32_t b{a};
338 }
339 
340 // CHECK-LABEL: define dso_local void @_Z13test_copy_f64u13__SVFloat64_t
341 // CHECK-SAME: (<vscale x 2 x double> [[A:%.*]]) #[[ATTR0]] {
342 // CHECK-NEXT:  entry:
343 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 2 x double>, align 16
344 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 2 x double>, align 16
345 // CHECK-NEXT:    store <vscale x 2 x double> [[A]], ptr [[A_ADDR]], align 16
346 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 2 x double>, ptr [[A_ADDR]], align 16
347 // CHECK-NEXT:    store <vscale x 2 x double> [[TMP0]], ptr [[B]], align 16
348 // CHECK-NEXT:    ret void
349 //
350 void test_copy_f64(__SVFloat64_t a) {
351   __SVFloat64_t b{a};
352 }
353 
354 // CHECK-LABEL: define dso_local void @_Z14test_copy_bf16u14__SVBfloat16_t
355 // CHECK-SAME: (<vscale x 8 x bfloat> [[A:%.*]]) #[[ATTR0]] {
356 // CHECK-NEXT:  entry:
357 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 8 x bfloat>, align 16
358 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 8 x bfloat>, align 16
359 // CHECK-NEXT:    store <vscale x 8 x bfloat> [[A]], ptr [[A_ADDR]], align 16
360 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 8 x bfloat>, ptr [[A_ADDR]], align 16
361 // CHECK-NEXT:    store <vscale x 8 x bfloat> [[TMP0]], ptr [[B]], align 16
362 // CHECK-NEXT:    ret void
363 //
364 void test_copy_bf16(__SVBfloat16_t a) {
365   __SVBfloat16_t b{a};
366 }
367 
368 // CHECK-LABEL: define dso_local void @_Z14test_copy_s8x210svint8x2_t
369 // CHECK-SAME: (<vscale x 16 x i8> [[A_COERCE0:%.*]], <vscale x 16 x i8> [[A_COERCE1:%.*]]) #[[ATTR0]] {
370 // CHECK-NEXT:  entry:
371 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
372 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
373 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
374 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[A_COERCE0]], 0
375 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[A_COERCE1]], 1
376 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], ptr [[A]], align 16
377 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A]], align 16
378 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A1]], ptr [[A_ADDR]], align 16
379 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A_ADDR]], align 16
380 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP2]], ptr [[B]], align 16
381 // CHECK-NEXT:    ret void
382 //
383 void test_copy_s8x2(__clang_svint8x2_t a) {
384   __clang_svint8x2_t b{a};
385 }
386 
387 // CHECK-LABEL: define dso_local void @_Z15test_copy_s16x211svint16x2_t
388 // CHECK-SAME: (<vscale x 8 x i16> [[A_COERCE0:%.*]], <vscale x 8 x i16> [[A_COERCE1:%.*]]) #[[ATTR0]] {
389 // CHECK-NEXT:  entry:
390 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
391 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
392 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
393 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> [[A_COERCE0]], 0
394 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], <vscale x 8 x i16> [[A_COERCE1]], 1
395 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP1]], ptr [[A]], align 16
396 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A]], align 16
397 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A1]], ptr [[A_ADDR]], align 16
398 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A_ADDR]], align 16
399 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], ptr [[B]], align 16
400 // CHECK-NEXT:    ret void
401 //
402 void test_copy_s16x2(__clang_svint16x2_t a) {
403   __clang_svint16x2_t b{a};
404 }
405 
406 // CHECK-LABEL: define dso_local void @_Z15test_copy_s32x211svint32x2_t
407 // CHECK-SAME: (<vscale x 4 x i32> [[A_COERCE0:%.*]], <vscale x 4 x i32> [[A_COERCE1:%.*]]) #[[ATTR0]] {
408 // CHECK-NEXT:  entry:
409 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
410 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
411 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
412 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> [[A_COERCE0]], 0
413 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], <vscale x 4 x i32> [[A_COERCE1]], 1
414 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP1]], ptr [[A]], align 16
415 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A]], align 16
416 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32> } [[A1]], ptr [[A_ADDR]], align 16
417 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A_ADDR]], align 16
418 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], ptr [[B]], align 16
419 // CHECK-NEXT:    ret void
420 //
421 void test_copy_s32x2(__clang_svint32x2_t a) {
422   __clang_svint32x2_t b{a};
423 }
424 
425 // CHECK-LABEL: define dso_local void @_Z15test_copy_s64x211svint64x2_t
426 // CHECK-SAME: (<vscale x 2 x i64> [[A_COERCE0:%.*]], <vscale x 2 x i64> [[A_COERCE1:%.*]]) #[[ATTR0]] {
427 // CHECK-NEXT:  entry:
428 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
429 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
430 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
431 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> [[A_COERCE0]], 0
432 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], <vscale x 2 x i64> [[A_COERCE1]], 1
433 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP1]], ptr [[A]], align 16
434 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A]], align 16
435 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64> } [[A1]], ptr [[A_ADDR]], align 16
436 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A_ADDR]], align 16
437 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], ptr [[B]], align 16
438 // CHECK-NEXT:    ret void
439 //
440 void test_copy_s64x2(__clang_svint64x2_t a) {
441   __clang_svint64x2_t b{a};
442 }
443 
444 // CHECK-LABEL: define dso_local void @_Z14test_copy_u8x211svuint8x2_t
445 // CHECK-SAME: (<vscale x 16 x i8> [[A_COERCE0:%.*]], <vscale x 16 x i8> [[A_COERCE1:%.*]]) #[[ATTR0]] {
446 // CHECK-NEXT:  entry:
447 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
448 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
449 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
450 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[A_COERCE0]], 0
451 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[A_COERCE1]], 1
452 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], ptr [[A]], align 16
453 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A]], align 16
454 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A1]], ptr [[A_ADDR]], align 16
455 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A_ADDR]], align 16
456 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP2]], ptr [[B]], align 16
457 // CHECK-NEXT:    ret void
458 //
459 void test_copy_u8x2(__clang_svuint8x2_t a) {
460   __clang_svuint8x2_t b{a};
461 }
462 
463 // CHECK-LABEL: define dso_local void @_Z15test_copy_u16x212svuint16x2_t
464 // CHECK-SAME: (<vscale x 8 x i16> [[A_COERCE0:%.*]], <vscale x 8 x i16> [[A_COERCE1:%.*]]) #[[ATTR0]] {
465 // CHECK-NEXT:  entry:
466 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
467 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
468 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
469 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> [[A_COERCE0]], 0
470 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], <vscale x 8 x i16> [[A_COERCE1]], 1
471 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP1]], ptr [[A]], align 16
472 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A]], align 16
473 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A1]], ptr [[A_ADDR]], align 16
474 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A_ADDR]], align 16
475 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], ptr [[B]], align 16
476 // CHECK-NEXT:    ret void
477 //
478 void test_copy_u16x2(__clang_svuint16x2_t a) {
479   __clang_svuint16x2_t b{a};
480 }
481 
482 // CHECK-LABEL: define dso_local void @_Z15test_copy_u32x212svuint32x2_t
483 // CHECK-SAME: (<vscale x 4 x i32> [[A_COERCE0:%.*]], <vscale x 4 x i32> [[A_COERCE1:%.*]]) #[[ATTR0]] {
484 // CHECK-NEXT:  entry:
485 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
486 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
487 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
488 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> [[A_COERCE0]], 0
489 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], <vscale x 4 x i32> [[A_COERCE1]], 1
490 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP1]], ptr [[A]], align 16
491 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A]], align 16
492 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32> } [[A1]], ptr [[A_ADDR]], align 16
493 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A_ADDR]], align 16
494 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], ptr [[B]], align 16
495 // CHECK-NEXT:    ret void
496 //
497 void test_copy_u32x2(__clang_svuint32x2_t a) {
498   __clang_svuint32x2_t b{a};
499 }
500 
501 // CHECK-LABEL: define dso_local void @_Z15test_copy_u64x212svuint64x2_t
502 // CHECK-SAME: (<vscale x 2 x i64> [[A_COERCE0:%.*]], <vscale x 2 x i64> [[A_COERCE1:%.*]]) #[[ATTR0]] {
503 // CHECK-NEXT:  entry:
504 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
505 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
506 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
507 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> [[A_COERCE0]], 0
508 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], <vscale x 2 x i64> [[A_COERCE1]], 1
509 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP1]], ptr [[A]], align 16
510 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A]], align 16
511 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64> } [[A1]], ptr [[A_ADDR]], align 16
512 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A_ADDR]], align 16
513 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], ptr [[B]], align 16
514 // CHECK-NEXT:    ret void
515 //
516 void test_copy_u64x2(__clang_svuint64x2_t a) {
517   __clang_svuint64x2_t b{a};
518 }
519 
520 // CHECK-LABEL: define dso_local void @_Z15test_copy_f16x213svfloat16x2_t
521 // CHECK-SAME: (<vscale x 8 x half> [[A_COERCE0:%.*]], <vscale x 8 x half> [[A_COERCE1:%.*]]) #[[ATTR0]] {
522 // CHECK-NEXT:  entry:
523 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
524 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
525 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
526 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> [[A_COERCE0]], 0
527 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } [[TMP0]], <vscale x 8 x half> [[A_COERCE1]], 1
528 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half> } [[TMP1]], ptr [[A]], align 16
529 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr [[A]], align 16
530 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half> } [[A1]], ptr [[A_ADDR]], align 16
531 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr [[A_ADDR]], align 16
532 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half> } [[TMP2]], ptr [[B]], align 16
533 // CHECK-NEXT:    ret void
534 //
535 void test_copy_f16x2(__clang_svfloat16x2_t a) {
536   __clang_svfloat16x2_t b{a};
537 }
538 
539 // CHECK-LABEL: define dso_local void @_Z15test_copy_f32x213svfloat32x2_t
540 // CHECK-SAME: (<vscale x 4 x float> [[A_COERCE0:%.*]], <vscale x 4 x float> [[A_COERCE1:%.*]]) #[[ATTR0]] {
541 // CHECK-NEXT:  entry:
542 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
543 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
544 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
545 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> [[A_COERCE0]], 0
546 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], <vscale x 4 x float> [[A_COERCE1]], 1
547 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP1]], ptr [[A]], align 16
548 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr [[A]], align 16
549 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float> } [[A1]], ptr [[A_ADDR]], align 16
550 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr [[A_ADDR]], align 16
551 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP2]], ptr [[B]], align 16
552 // CHECK-NEXT:    ret void
553 //
554 void test_copy_f32x2(__clang_svfloat32x2_t a) {
555   __clang_svfloat32x2_t b{a};
556 }
557 
558 // CHECK-LABEL: define dso_local void @_Z15test_copy_f64x213svfloat64x2_t
559 // CHECK-SAME: (<vscale x 2 x double> [[A_COERCE0:%.*]], <vscale x 2 x double> [[A_COERCE1:%.*]]) #[[ATTR0]] {
560 // CHECK-NEXT:  entry:
561 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
562 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
563 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
564 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> [[A_COERCE0]], 0
565 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], <vscale x 2 x double> [[A_COERCE1]], 1
566 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP1]], ptr [[A]], align 16
567 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr [[A]], align 16
568 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double> } [[A1]], ptr [[A_ADDR]], align 16
569 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr [[A_ADDR]], align 16
570 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP2]], ptr [[B]], align 16
571 // CHECK-NEXT:    ret void
572 //
573 void test_copy_f64x2(__clang_svfloat64x2_t a) {
574   __clang_svfloat64x2_t b{a};
575 }
576 
577 // CHECK-LABEL: define dso_local void @_Z16test_copy_bf16x214svbfloat16x2_t
578 // CHECK-SAME: (<vscale x 8 x bfloat> [[A_COERCE0:%.*]], <vscale x 8 x bfloat> [[A_COERCE1:%.*]]) #[[ATTR0]] {
579 // CHECK-NEXT:  entry:
580 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
581 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
582 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
583 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> [[A_COERCE0]], 0
584 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP0]], <vscale x 8 x bfloat> [[A_COERCE1]], 1
585 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP1]], ptr [[A]], align 16
586 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr [[A]], align 16
587 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[A1]], ptr [[A_ADDR]], align 16
588 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr [[A_ADDR]], align 16
589 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP2]], ptr [[B]], align 16
590 // CHECK-NEXT:    ret void
591 //
592 void test_copy_bf16x2(__clang_svbfloat16x2_t a) {
593   __clang_svbfloat16x2_t b{a};
594 }
595 
596 // CHECK-LABEL: define dso_local void @_Z14test_copy_s8x310svint8x3_t
597 // CHECK-SAME: (<vscale x 16 x i8> [[A_COERCE0:%.*]], <vscale x 16 x i8> [[A_COERCE1:%.*]], <vscale x 16 x i8> [[A_COERCE2:%.*]]) #[[ATTR0]] {
598 // CHECK-NEXT:  entry:
599 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
600 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
601 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
602 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[A_COERCE0]], 0
603 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[A_COERCE1]], 1
604 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], <vscale x 16 x i8> [[A_COERCE2]], 2
605 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP2]], ptr [[A]], align 16
606 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A]], align 16
607 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[A1]], ptr [[A_ADDR]], align 16
608 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A_ADDR]], align 16
609 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP3]], ptr [[B]], align 16
610 // CHECK-NEXT:    ret void
611 //
612 void test_copy_s8x3(__clang_svint8x3_t a) {
613   __clang_svint8x3_t b{a};
614 }
615 
616 // CHECK-LABEL: define dso_local void @_Z15test_copy_s16x311svint16x3_t
617 // CHECK-SAME: (<vscale x 8 x i16> [[A_COERCE0:%.*]], <vscale x 8 x i16> [[A_COERCE1:%.*]], <vscale x 8 x i16> [[A_COERCE2:%.*]]) #[[ATTR0]] {
618 // CHECK-NEXT:  entry:
619 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
620 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
621 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
622 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> [[A_COERCE0]], 0
623 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], <vscale x 8 x i16> [[A_COERCE1]], 1
624 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP1]], <vscale x 8 x i16> [[A_COERCE2]], 2
625 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], ptr [[A]], align 16
626 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A]], align 16
627 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[A1]], ptr [[A_ADDR]], align 16
628 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A_ADDR]], align 16
629 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP3]], ptr [[B]], align 16
630 // CHECK-NEXT:    ret void
631 //
632 void test_copy_s16x3(__clang_svint16x3_t a) {
633   __clang_svint16x3_t b{a};
634 }
635 
636 // CHECK-LABEL: define dso_local void @_Z15test_copy_s32x311svint32x3_t
637 // CHECK-SAME: (<vscale x 4 x i32> [[A_COERCE0:%.*]], <vscale x 4 x i32> [[A_COERCE1:%.*]], <vscale x 4 x i32> [[A_COERCE2:%.*]]) #[[ATTR0]] {
638 // CHECK-NEXT:  entry:
639 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
640 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
641 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
642 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> [[A_COERCE0]], 0
643 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], <vscale x 4 x i32> [[A_COERCE1]], 1
644 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP1]], <vscale x 4 x i32> [[A_COERCE2]], 2
645 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], ptr [[A]], align 16
646 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A]], align 16
647 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[A1]], ptr [[A_ADDR]], align 16
648 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A_ADDR]], align 16
649 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP3]], ptr [[B]], align 16
650 // CHECK-NEXT:    ret void
651 //
652 void test_copy_s32x3(__clang_svint32x3_t a) {
653   __clang_svint32x3_t b{a};
654 }
655 
656 // CHECK-LABEL: define dso_local void @_Z15test_copy_s64x311svint64x3_t
657 // CHECK-SAME: (<vscale x 2 x i64> [[A_COERCE0:%.*]], <vscale x 2 x i64> [[A_COERCE1:%.*]], <vscale x 2 x i64> [[A_COERCE2:%.*]]) #[[ATTR0]] {
658 // CHECK-NEXT:  entry:
659 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
660 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
661 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
662 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> [[A_COERCE0]], 0
663 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], <vscale x 2 x i64> [[A_COERCE1]], 1
664 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP1]], <vscale x 2 x i64> [[A_COERCE2]], 2
665 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], ptr [[A]], align 16
666 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A]], align 16
667 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[A1]], ptr [[A_ADDR]], align 16
668 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A_ADDR]], align 16
669 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP3]], ptr [[B]], align 16
670 // CHECK-NEXT:    ret void
671 //
672 void test_copy_s64x3(__clang_svint64x3_t a) {
673   __clang_svint64x3_t b{a};
674 }
675 
676 // CHECK-LABEL: define dso_local void @_Z14test_copy_u8x311svuint8x3_t
677 // CHECK-SAME: (<vscale x 16 x i8> [[A_COERCE0:%.*]], <vscale x 16 x i8> [[A_COERCE1:%.*]], <vscale x 16 x i8> [[A_COERCE2:%.*]]) #[[ATTR0]] {
678 // CHECK-NEXT:  entry:
679 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
680 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
681 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
682 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[A_COERCE0]], 0
683 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[A_COERCE1]], 1
684 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], <vscale x 16 x i8> [[A_COERCE2]], 2
685 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP2]], ptr [[A]], align 16
686 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A]], align 16
687 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[A1]], ptr [[A_ADDR]], align 16
688 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A_ADDR]], align 16
689 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP3]], ptr [[B]], align 16
690 // CHECK-NEXT:    ret void
691 //
692 void test_copy_u8x3(__clang_svuint8x3_t a) {
693   __clang_svuint8x3_t b{a};
694 }
695 
696 // CHECK-LABEL: define dso_local void @_Z15test_copy_u16x312svuint16x3_t
697 // CHECK-SAME: (<vscale x 8 x i16> [[A_COERCE0:%.*]], <vscale x 8 x i16> [[A_COERCE1:%.*]], <vscale x 8 x i16> [[A_COERCE2:%.*]]) #[[ATTR0]] {
698 // CHECK-NEXT:  entry:
699 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
700 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
701 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
702 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> [[A_COERCE0]], 0
703 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], <vscale x 8 x i16> [[A_COERCE1]], 1
704 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP1]], <vscale x 8 x i16> [[A_COERCE2]], 2
705 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], ptr [[A]], align 16
706 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A]], align 16
707 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[A1]], ptr [[A_ADDR]], align 16
708 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A_ADDR]], align 16
709 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP3]], ptr [[B]], align 16
710 // CHECK-NEXT:    ret void
711 //
712 void test_copy_u16x3(__clang_svuint16x3_t a) {
713   __clang_svuint16x3_t b{a};
714 }
715 
716 // CHECK-LABEL: define dso_local void @_Z15test_copy_u32x312svuint32x3_t
717 // CHECK-SAME: (<vscale x 4 x i32> [[A_COERCE0:%.*]], <vscale x 4 x i32> [[A_COERCE1:%.*]], <vscale x 4 x i32> [[A_COERCE2:%.*]]) #[[ATTR0]] {
718 // CHECK-NEXT:  entry:
719 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
720 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
721 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
722 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> [[A_COERCE0]], 0
723 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], <vscale x 4 x i32> [[A_COERCE1]], 1
724 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP1]], <vscale x 4 x i32> [[A_COERCE2]], 2
725 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], ptr [[A]], align 16
726 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A]], align 16
727 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[A1]], ptr [[A_ADDR]], align 16
728 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A_ADDR]], align 16
729 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP3]], ptr [[B]], align 16
730 // CHECK-NEXT:    ret void
731 //
732 void test_copy_u32x3(__clang_svuint32x3_t a) {
733   __clang_svuint32x3_t b{a};
734 }
735 
736 // CHECK-LABEL: define dso_local void @_Z15test_copy_u64x312svuint64x3_t
737 // CHECK-SAME: (<vscale x 2 x i64> [[A_COERCE0:%.*]], <vscale x 2 x i64> [[A_COERCE1:%.*]], <vscale x 2 x i64> [[A_COERCE2:%.*]]) #[[ATTR0]] {
738 // CHECK-NEXT:  entry:
739 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
740 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
741 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
742 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> [[A_COERCE0]], 0
743 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], <vscale x 2 x i64> [[A_COERCE1]], 1
744 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP1]], <vscale x 2 x i64> [[A_COERCE2]], 2
745 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], ptr [[A]], align 16
746 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A]], align 16
747 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[A1]], ptr [[A_ADDR]], align 16
748 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A_ADDR]], align 16
749 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP3]], ptr [[B]], align 16
750 // CHECK-NEXT:    ret void
751 //
752 void test_copy_u64x3(__clang_svuint64x3_t a) {
753   __clang_svuint64x3_t b{a};
754 }
755 
756 // CHECK-LABEL: define dso_local void @_Z15test_copy_f16x313svfloat16x3_t
757 // CHECK-SAME: (<vscale x 8 x half> [[A_COERCE0:%.*]], <vscale x 8 x half> [[A_COERCE1:%.*]], <vscale x 8 x half> [[A_COERCE2:%.*]]) #[[ATTR0]] {
758 // CHECK-NEXT:  entry:
759 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
760 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
761 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
762 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> [[A_COERCE0]], 0
763 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } [[TMP0]], <vscale x 8 x half> [[A_COERCE1]], 1
764 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } [[TMP1]], <vscale x 8 x half> [[A_COERCE2]], 2
765 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } [[TMP2]], ptr [[A]], align 16
766 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr [[A]], align 16
767 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } [[A1]], ptr [[A_ADDR]], align 16
768 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr [[A_ADDR]], align 16
769 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } [[TMP3]], ptr [[B]], align 16
770 // CHECK-NEXT:    ret void
771 //
772 void test_copy_f16x3(__clang_svfloat16x3_t a) {
773   __clang_svfloat16x3_t b{a};
774 }
775 
776 // CHECK-LABEL: define dso_local void @_Z15test_copy_f32x313svfloat32x3_t
777 // CHECK-SAME: (<vscale x 4 x float> [[A_COERCE0:%.*]], <vscale x 4 x float> [[A_COERCE1:%.*]], <vscale x 4 x float> [[A_COERCE2:%.*]]) #[[ATTR0]] {
778 // CHECK-NEXT:  entry:
779 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
780 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
781 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
782 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> [[A_COERCE0]], 0
783 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], <vscale x 4 x float> [[A_COERCE1]], 1
784 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP1]], <vscale x 4 x float> [[A_COERCE2]], 2
785 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP2]], ptr [[A]], align 16
786 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr [[A]], align 16
787 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[A1]], ptr [[A_ADDR]], align 16
788 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr [[A_ADDR]], align 16
789 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP3]], ptr [[B]], align 16
790 // CHECK-NEXT:    ret void
791 //
792 void test_copy_f32x3(__clang_svfloat32x3_t a) {
793   __clang_svfloat32x3_t b{a};
794 }
795 
796 // CHECK-LABEL: define dso_local void @_Z15test_copy_f64x313svfloat64x3_t
797 // CHECK-SAME: (<vscale x 2 x double> [[A_COERCE0:%.*]], <vscale x 2 x double> [[A_COERCE1:%.*]], <vscale x 2 x double> [[A_COERCE2:%.*]]) #[[ATTR0]] {
798 // CHECK-NEXT:  entry:
799 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 16
800 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 16
801 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 16
802 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> [[A_COERCE0]], 0
803 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], <vscale x 2 x double> [[A_COERCE1]], 1
804 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP1]], <vscale x 2 x double> [[A_COERCE2]], 2
805 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP2]], ptr [[A]], align 16
806 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, ptr [[A]], align 16
807 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[A1]], ptr [[A_ADDR]], align 16
808 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, ptr [[A_ADDR]], align 16
809 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP3]], ptr [[B]], align 16
810 // CHECK-NEXT:    ret void
811 //
812 void test_copy_f64x3(__clang_svfloat64x3_t a) {
813   __clang_svfloat64x3_t b{a};
814 }
815 
816 // CHECK-LABEL: define dso_local void @_Z16test_copy_bf16x314svbfloat16x3_t
817 // CHECK-SAME: (<vscale x 8 x bfloat> [[A_COERCE0:%.*]], <vscale x 8 x bfloat> [[A_COERCE1:%.*]], <vscale x 8 x bfloat> [[A_COERCE2:%.*]]) #[[ATTR0]] {
818 // CHECK-NEXT:  entry:
819 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
820 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
821 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
822 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> [[A_COERCE0]], 0
823 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP0]], <vscale x 8 x bfloat> [[A_COERCE1]], 1
824 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP1]], <vscale x 8 x bfloat> [[A_COERCE2]], 2
825 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP2]], ptr [[A]], align 16
826 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr [[A]], align 16
827 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[A1]], ptr [[A_ADDR]], align 16
828 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr [[A_ADDR]], align 16
829 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP3]], ptr [[B]], align 16
830 // CHECK-NEXT:    ret void
831 //
832 void test_copy_bf16x3(__clang_svbfloat16x3_t a) {
833   __clang_svbfloat16x3_t b{a};
834 }
835 
836 // CHECK-LABEL: define dso_local void @_Z14test_copy_s8x410svint8x4_t
837 // CHECK-SAME: (<vscale x 16 x i8> [[A_COERCE0:%.*]], <vscale x 16 x i8> [[A_COERCE1:%.*]], <vscale x 16 x i8> [[A_COERCE2:%.*]], <vscale x 16 x i8> [[A_COERCE3:%.*]]) #[[ATTR0]] {
838 // CHECK-NEXT:  entry:
839 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
840 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
841 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
842 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[A_COERCE0]], 0
843 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[A_COERCE1]], 1
844 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], <vscale x 16 x i8> [[A_COERCE2]], 2
845 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP2]], <vscale x 16 x i8> [[A_COERCE3]], 3
846 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP3]], ptr [[A]], align 16
847 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A]], align 16
848 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[A1]], ptr [[A_ADDR]], align 16
849 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A_ADDR]], align 16
850 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP4]], ptr [[B]], align 16
851 // CHECK-NEXT:    ret void
852 //
853 void test_copy_s8x4(__clang_svint8x4_t a) {
854   __clang_svint8x4_t b{a};
855 }
856 
857 // CHECK-LABEL: define dso_local void @_Z15test_copy_s16x411svint16x4_t
858 // CHECK-SAME: (<vscale x 8 x i16> [[A_COERCE0:%.*]], <vscale x 8 x i16> [[A_COERCE1:%.*]], <vscale x 8 x i16> [[A_COERCE2:%.*]], <vscale x 8 x i16> [[A_COERCE3:%.*]]) #[[ATTR0]] {
859 // CHECK-NEXT:  entry:
860 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
861 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
862 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
863 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> [[A_COERCE0]], 0
864 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], <vscale x 8 x i16> [[A_COERCE1]], 1
865 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP1]], <vscale x 8 x i16> [[A_COERCE2]], 2
866 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], <vscale x 8 x i16> [[A_COERCE3]], 3
867 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP3]], ptr [[A]], align 16
868 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A]], align 16
869 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[A1]], ptr [[A_ADDR]], align 16
870 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A_ADDR]], align 16
871 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP4]], ptr [[B]], align 16
872 // CHECK-NEXT:    ret void
873 //
874 void test_copy_s16x4(__clang_svint16x4_t a) {
875   __clang_svint16x4_t b{a};
876 }
877 
878 // CHECK-LABEL: define dso_local void @_Z15test_copy_s32x411svint32x4_t
879 // CHECK-SAME: (<vscale x 4 x i32> [[A_COERCE0:%.*]], <vscale x 4 x i32> [[A_COERCE1:%.*]], <vscale x 4 x i32> [[A_COERCE2:%.*]], <vscale x 4 x i32> [[A_COERCE3:%.*]]) #[[ATTR0]] {
880 // CHECK-NEXT:  entry:
881 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
882 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
883 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
884 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> [[A_COERCE0]], 0
885 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], <vscale x 4 x i32> [[A_COERCE1]], 1
886 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP1]], <vscale x 4 x i32> [[A_COERCE2]], 2
887 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], <vscale x 4 x i32> [[A_COERCE3]], 3
888 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP3]], ptr [[A]], align 16
889 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A]], align 16
890 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[A1]], ptr [[A_ADDR]], align 16
891 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A_ADDR]], align 16
892 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP4]], ptr [[B]], align 16
893 // CHECK-NEXT:    ret void
894 //
895 void test_copy_s32x4(__clang_svint32x4_t a) {
896   __clang_svint32x4_t b{a};
897 }
898 
899 // CHECK-LABEL: define dso_local void @_Z15test_copy_s64x411svint64x4_t
900 // CHECK-SAME: (<vscale x 2 x i64> [[A_COERCE0:%.*]], <vscale x 2 x i64> [[A_COERCE1:%.*]], <vscale x 2 x i64> [[A_COERCE2:%.*]], <vscale x 2 x i64> [[A_COERCE3:%.*]]) #[[ATTR0]] {
901 // CHECK-NEXT:  entry:
902 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
903 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
904 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
905 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> [[A_COERCE0]], 0
906 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], <vscale x 2 x i64> [[A_COERCE1]], 1
907 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP1]], <vscale x 2 x i64> [[A_COERCE2]], 2
908 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], <vscale x 2 x i64> [[A_COERCE3]], 3
909 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP3]], ptr [[A]], align 16
910 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A]], align 16
911 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[A1]], ptr [[A_ADDR]], align 16
912 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A_ADDR]], align 16
913 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP4]], ptr [[B]], align 16
914 // CHECK-NEXT:    ret void
915 //
916 void test_copy_s64x4(__clang_svint64x4_t a) {
917   __clang_svint64x4_t b{a};
918 }
919 
920 // CHECK-LABEL: define dso_local void @_Z14test_copy_u8x411svuint8x4_t
921 // CHECK-SAME: (<vscale x 16 x i8> [[A_COERCE0:%.*]], <vscale x 16 x i8> [[A_COERCE1:%.*]], <vscale x 16 x i8> [[A_COERCE2:%.*]], <vscale x 16 x i8> [[A_COERCE3:%.*]]) #[[ATTR0]] {
922 // CHECK-NEXT:  entry:
923 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
924 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
925 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
926 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[A_COERCE0]], 0
927 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[A_COERCE1]], 1
928 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], <vscale x 16 x i8> [[A_COERCE2]], 2
929 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP2]], <vscale x 16 x i8> [[A_COERCE3]], 3
930 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP3]], ptr [[A]], align 16
931 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A]], align 16
932 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[A1]], ptr [[A_ADDR]], align 16
933 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A_ADDR]], align 16
934 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP4]], ptr [[B]], align 16
935 // CHECK-NEXT:    ret void
936 //
937 void test_copy_u8x4(__clang_svuint8x4_t a) {
938   __clang_svuint8x4_t b{a};
939 }
940 
941 // CHECK-LABEL: define dso_local void @_Z15test_copy_u16x412svuint16x4_t
942 // CHECK-SAME: (<vscale x 8 x i16> [[A_COERCE0:%.*]], <vscale x 8 x i16> [[A_COERCE1:%.*]], <vscale x 8 x i16> [[A_COERCE2:%.*]], <vscale x 8 x i16> [[A_COERCE3:%.*]]) #[[ATTR0]] {
943 // CHECK-NEXT:  entry:
944 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
945 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
946 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
947 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> [[A_COERCE0]], 0
948 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], <vscale x 8 x i16> [[A_COERCE1]], 1
949 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP1]], <vscale x 8 x i16> [[A_COERCE2]], 2
950 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], <vscale x 8 x i16> [[A_COERCE3]], 3
951 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP3]], ptr [[A]], align 16
952 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A]], align 16
953 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[A1]], ptr [[A_ADDR]], align 16
954 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr [[A_ADDR]], align 16
955 // CHECK-NEXT:    store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP4]], ptr [[B]], align 16
956 // CHECK-NEXT:    ret void
957 //
958 void test_copy_u16x4(__clang_svuint16x4_t a) {
959   __clang_svuint16x4_t b{a};
960 }
961 
962 // CHECK-LABEL: define dso_local void @_Z15test_copy_u32x412svuint32x4_t
963 // CHECK-SAME: (<vscale x 4 x i32> [[A_COERCE0:%.*]], <vscale x 4 x i32> [[A_COERCE1:%.*]], <vscale x 4 x i32> [[A_COERCE2:%.*]], <vscale x 4 x i32> [[A_COERCE3:%.*]]) #[[ATTR0]] {
964 // CHECK-NEXT:  entry:
965 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
966 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
967 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
968 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> [[A_COERCE0]], 0
969 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], <vscale x 4 x i32> [[A_COERCE1]], 1
970 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP1]], <vscale x 4 x i32> [[A_COERCE2]], 2
971 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], <vscale x 4 x i32> [[A_COERCE3]], 3
972 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP3]], ptr [[A]], align 16
973 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A]], align 16
974 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[A1]], ptr [[A_ADDR]], align 16
975 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr [[A_ADDR]], align 16
976 // CHECK-NEXT:    store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP4]], ptr [[B]], align 16
977 // CHECK-NEXT:    ret void
978 //
979 void test_copy_u32x4(__clang_svuint32x4_t a) {
980   __clang_svuint32x4_t b{a};
981 }
982 
983 // CHECK-LABEL: define dso_local void @_Z15test_copy_u64x412svuint64x4_t
984 // CHECK-SAME: (<vscale x 2 x i64> [[A_COERCE0:%.*]], <vscale x 2 x i64> [[A_COERCE1:%.*]], <vscale x 2 x i64> [[A_COERCE2:%.*]], <vscale x 2 x i64> [[A_COERCE3:%.*]]) #[[ATTR0]] {
985 // CHECK-NEXT:  entry:
986 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
987 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
988 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
989 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> [[A_COERCE0]], 0
990 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], <vscale x 2 x i64> [[A_COERCE1]], 1
991 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP1]], <vscale x 2 x i64> [[A_COERCE2]], 2
992 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], <vscale x 2 x i64> [[A_COERCE3]], 3
993 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP3]], ptr [[A]], align 16
994 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A]], align 16
995 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[A1]], ptr [[A_ADDR]], align 16
996 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr [[A_ADDR]], align 16
997 // CHECK-NEXT:    store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP4]], ptr [[B]], align 16
998 // CHECK-NEXT:    ret void
999 //
1000 void test_copy_u64x4(__clang_svuint64x4_t a) {
1001   __clang_svuint64x4_t b{a};
1002 }
1003 
1004 // CHECK-LABEL: define dso_local void @_Z15test_copy_f16x413svfloat16x4_t
1005 // CHECK-SAME: (<vscale x 8 x half> [[A_COERCE0:%.*]], <vscale x 8 x half> [[A_COERCE1:%.*]], <vscale x 8 x half> [[A_COERCE2:%.*]], <vscale x 8 x half> [[A_COERCE3:%.*]]) #[[ATTR0]] {
1006 // CHECK-NEXT:  entry:
1007 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
1008 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
1009 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
1010 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> [[A_COERCE0]], 0
1011 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } [[TMP0]], <vscale x 8 x half> [[A_COERCE1]], 1
1012 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } [[TMP1]], <vscale x 8 x half> [[A_COERCE2]], 2
1013 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } [[TMP2]], <vscale x 8 x half> [[A_COERCE3]], 3
1014 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } [[TMP3]], ptr [[A]], align 16
1015 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr [[A]], align 16
1016 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } [[A1]], ptr [[A_ADDR]], align 16
1017 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr [[A_ADDR]], align 16
1018 // CHECK-NEXT:    store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } [[TMP4]], ptr [[B]], align 16
1019 // CHECK-NEXT:    ret void
1020 //
1021 void test_copy_f16x4(__clang_svfloat16x4_t a) {
1022   __clang_svfloat16x4_t b{a};
1023 }
1024 
1025 // CHECK-LABEL: define dso_local void @_Z15test_copy_f32x413svfloat32x4_t
1026 // CHECK-SAME: (<vscale x 4 x float> [[A_COERCE0:%.*]], <vscale x 4 x float> [[A_COERCE1:%.*]], <vscale x 4 x float> [[A_COERCE2:%.*]], <vscale x 4 x float> [[A_COERCE3:%.*]]) #[[ATTR0]] {
1027 // CHECK-NEXT:  entry:
1028 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
1029 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
1030 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
1031 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> [[A_COERCE0]], 0
1032 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], <vscale x 4 x float> [[A_COERCE1]], 1
1033 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP1]], <vscale x 4 x float> [[A_COERCE2]], 2
1034 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP2]], <vscale x 4 x float> [[A_COERCE3]], 3
1035 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP3]], ptr [[A]], align 16
1036 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr [[A]], align 16
1037 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[A1]], ptr [[A_ADDR]], align 16
1038 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr [[A_ADDR]], align 16
1039 // CHECK-NEXT:    store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP4]], ptr [[B]], align 16
1040 // CHECK-NEXT:    ret void
1041 //
1042 void test_copy_f32x4(__clang_svfloat32x4_t a) {
1043   __clang_svfloat32x4_t b{a};
1044 }
1045 
1046 // CHECK-LABEL: define dso_local void @_Z15test_copy_f64x413svfloat64x4_t
1047 // CHECK-SAME: (<vscale x 2 x double> [[A_COERCE0:%.*]], <vscale x 2 x double> [[A_COERCE1:%.*]], <vscale x 2 x double> [[A_COERCE2:%.*]], <vscale x 2 x double> [[A_COERCE3:%.*]]) #[[ATTR0]] {
1048 // CHECK-NEXT:  entry:
1049 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 16
1050 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 16
1051 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, align 16
1052 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> [[A_COERCE0]], 0
1053 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], <vscale x 2 x double> [[A_COERCE1]], 1
1054 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP1]], <vscale x 2 x double> [[A_COERCE2]], 2
1055 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP2]], <vscale x 2 x double> [[A_COERCE3]], 3
1056 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP3]], ptr [[A]], align 16
1057 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, ptr [[A]], align 16
1058 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[A1]], ptr [[A_ADDR]], align 16
1059 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }, ptr [[A_ADDR]], align 16
1060 // CHECK-NEXT:    store { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP4]], ptr [[B]], align 16
1061 // CHECK-NEXT:    ret void
1062 //
1063 void test_copy_f64x4(__clang_svfloat64x4_t a) {
1064   __clang_svfloat64x4_t b{a};
1065 }
1066 
1067 // CHECK-LABEL: define dso_local void @_Z16test_copy_bf16x414svbfloat16x4_t
1068 // CHECK-SAME: (<vscale x 8 x bfloat> [[A_COERCE0:%.*]], <vscale x 8 x bfloat> [[A_COERCE1:%.*]], <vscale x 8 x bfloat> [[A_COERCE2:%.*]], <vscale x 8 x bfloat> [[A_COERCE3:%.*]]) #[[ATTR0]] {
1069 // CHECK-NEXT:  entry:
1070 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
1071 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
1072 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
1073 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> [[A_COERCE0]], 0
1074 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP0]], <vscale x 8 x bfloat> [[A_COERCE1]], 1
1075 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP1]], <vscale x 8 x bfloat> [[A_COERCE2]], 2
1076 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP2]], <vscale x 8 x bfloat> [[A_COERCE3]], 3
1077 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP3]], ptr [[A]], align 16
1078 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr [[A]], align 16
1079 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[A1]], ptr [[A_ADDR]], align 16
1080 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr [[A_ADDR]], align 16
1081 // CHECK-NEXT:    store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP4]], ptr [[B]], align 16
1082 // CHECK-NEXT:    ret void
1083 //
1084 void test_copy_bf16x4(__clang_svbfloat16x4_t a) {
1085   __clang_svbfloat16x4_t b{a};
1086 }
1087 
1088 // CHECK-LABEL: define dso_local void @_Z12test_copy_b8u10__SVBool_t
1089 // CHECK-SAME: (<vscale x 16 x i1> [[A:%.*]]) #[[ATTR0]] {
1090 // CHECK-NEXT:  entry:
1091 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 16 x i1>, align 2
1092 // CHECK-NEXT:    [[B:%.*]] = alloca <vscale x 16 x i1>, align 2
1093 // CHECK-NEXT:    store <vscale x 16 x i1> [[A]], ptr [[A_ADDR]], align 2
1094 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 16 x i1>, ptr [[A_ADDR]], align 2
1095 // CHECK-NEXT:    store <vscale x 16 x i1> [[TMP0]], ptr [[B]], align 2
1096 // CHECK-NEXT:    ret void
1097 //
1098 void test_copy_b8(__SVBool_t a) {
1099   __SVBool_t b{a};
1100 }
1101 
1102 // CHECK-LABEL: define dso_local void @_Z14test_copy_b8x210svboolx2_t
1103 // CHECK-SAME: (<vscale x 16 x i1> [[A_COERCE0:%.*]], <vscale x 16 x i1> [[A_COERCE1:%.*]]) #[[ATTR0]] {
1104 // CHECK-NEXT:  entry:
1105 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
1106 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
1107 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
1108 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> [[A_COERCE0]], 0
1109 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP0]], <vscale x 16 x i1> [[A_COERCE1]], 1
1110 // CHECK-NEXT:    store { <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP1]], ptr [[A]], align 2
1111 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr [[A]], align 2
1112 // CHECK-NEXT:    store { <vscale x 16 x i1>, <vscale x 16 x i1> } [[A1]], ptr [[A_ADDR]], align 2
1113 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr [[A_ADDR]], align 2
1114 // CHECK-NEXT:    store { <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP2]], ptr [[B]], align 2
1115 // CHECK-NEXT:    ret void
1116 //
1117 void test_copy_b8x2(__clang_svboolx2_t a) {
1118   __clang_svboolx2_t b{a};
1119 }
1120 
1121 // CHECK-LABEL: define dso_local void @_Z14test_copy_b8x410svboolx4_t
1122 // CHECK-SAME: (<vscale x 16 x i1> [[A_COERCE0:%.*]], <vscale x 16 x i1> [[A_COERCE1:%.*]], <vscale x 16 x i1> [[A_COERCE2:%.*]], <vscale x 16 x i1> [[A_COERCE3:%.*]]) #[[ATTR0]] {
1123 // CHECK-NEXT:  entry:
1124 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
1125 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
1126 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
1127 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> [[A_COERCE0]], 0
1128 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP0]], <vscale x 16 x i1> [[A_COERCE1]], 1
1129 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP1]], <vscale x 16 x i1> [[A_COERCE2]], 2
1130 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP2]], <vscale x 16 x i1> [[A_COERCE3]], 3
1131 // CHECK-NEXT:    store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP3]], ptr [[A]], align 2
1132 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr [[A]], align 2
1133 // CHECK-NEXT:    store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } [[A1]], ptr [[A_ADDR]], align 2
1134 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr [[A_ADDR]], align 2
1135 // CHECK-NEXT:    store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP4]], ptr [[B]], align 2
1136 // CHECK-NEXT:    ret void
1137 //
1138 void test_copy_b8x4(__clang_svboolx4_t a) {
1139   __clang_svboolx4_t b{a};
1140 }
1141 
1142 // CHECK-LABEL: define dso_local void @_Z13test_copy_cntu11__SVCount_t
1143 // CHECK-SAME: (target("aarch64.svcount") [[A:%.*]]) #[[ATTR0]] {
1144 // CHECK-NEXT:  entry:
1145 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca target("aarch64.svcount"), align 2
1146 // CHECK-NEXT:    [[B:%.*]] = alloca target("aarch64.svcount"), align 2
1147 // CHECK-NEXT:    store target("aarch64.svcount") [[A]], ptr [[A_ADDR]], align 2
1148 // CHECK-NEXT:    [[TMP0:%.*]] = load target("aarch64.svcount"), ptr [[A_ADDR]], align 2
1149 // CHECK-NEXT:    store target("aarch64.svcount") [[TMP0]], ptr [[B]], align 2
1150 // CHECK-NEXT:    ret void
1151 //
1152 void test_copy_cnt(__SVCount_t a) {
1153   __SVCount_t b{a};
1154 }
1155 
1156 // CHECK-LABEL: define dso_local void @_Z15test_copy_mf8x213svmfloat8x2_t
1157 // CHECK-SAME: (<vscale x 16 x i8> [[A_COERCE0:%.*]], <vscale x 16 x i8> [[A_COERCE1:%.*]]) #[[ATTR0]] {
1158 // CHECK-NEXT:  entry:
1159 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
1160 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
1161 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
1162 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[A_COERCE0]], 0
1163 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[A_COERCE1]], 1
1164 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], ptr [[A]], align 16
1165 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A]], align 16
1166 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A1]], ptr [[A_ADDR]], align 16
1167 // CHECK-NEXT:    [[TMP2:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A_ADDR]], align 16
1168 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP2]], ptr [[B]], align 16
1169 // CHECK-NEXT:    ret void
1170 //
1171 void test_copy_mf8x2(__clang_svmfloat8x2_t a) {
1172   __clang_svmfloat8x2_t b{a};
1173 }
1174 
1175 // CHECK-LABEL: define dso_local void @_Z15test_copy_mf8x313svmfloat8x3_t
1176 // CHECK-SAME: (<vscale x 16 x i8> [[A_COERCE0:%.*]], <vscale x 16 x i8> [[A_COERCE1:%.*]], <vscale x 16 x i8> [[A_COERCE2:%.*]]) #[[ATTR0]] {
1177 // CHECK-NEXT:  entry:
1178 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
1179 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
1180 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
1181 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[A_COERCE0]], 0
1182 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[A_COERCE1]], 1
1183 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], <vscale x 16 x i8> [[A_COERCE2]], 2
1184 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP2]], ptr [[A]], align 16
1185 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A]], align 16
1186 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[A1]], ptr [[A_ADDR]], align 16
1187 // CHECK-NEXT:    [[TMP3:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A_ADDR]], align 16
1188 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP3]], ptr [[B]], align 16
1189 // CHECK-NEXT:    ret void
1190 //
1191 void test_copy_mf8x3(__clang_svmfloat8x3_t a) {
1192   __clang_svmfloat8x3_t b{a};
1193 }
1194 
1195 // CHECK-LABEL: define dso_local void @_Z15test_copy_mf8x413svmfloat8x4_t
1196 // CHECK-SAME: (<vscale x 16 x i8> [[A_COERCE0:%.*]], <vscale x 16 x i8> [[A_COERCE1:%.*]], <vscale x 16 x i8> [[A_COERCE2:%.*]], <vscale x 16 x i8> [[A_COERCE3:%.*]]) #[[ATTR0]] {
1197 // CHECK-NEXT:  entry:
1198 // CHECK-NEXT:    [[A:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
1199 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
1200 // CHECK-NEXT:    [[B:%.*]] = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
1201 // CHECK-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[A_COERCE0]], 0
1202 // CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[A_COERCE1]], 1
1203 // CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP1]], <vscale x 16 x i8> [[A_COERCE2]], 2
1204 // CHECK-NEXT:    [[TMP3:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP2]], <vscale x 16 x i8> [[A_COERCE3]], 3
1205 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP3]], ptr [[A]], align 16
1206 // CHECK-NEXT:    [[A1:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A]], align 16
1207 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[A1]], ptr [[A_ADDR]], align 16
1208 // CHECK-NEXT:    [[TMP4:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[A_ADDR]], align 16
1209 // CHECK-NEXT:    store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP4]], ptr [[B]], align 16
1210 // CHECK-NEXT:    ret void
1211 //
1212 void test_copy_mf8x4(__clang_svmfloat8x4_t a) {
1213   __clang_svmfloat8x4_t b{a};
1214 }
1215 
1216 /// Reduced from: https://github.com/llvm/llvm-project/issues/107609
1217 using vec_t = __SVInt8_t;
1218 
1219 // CHECK-LABEL: define dso_local void @_Z20test_copy_s8_typedefu10__SVInt8_t
1220 // CHECK-SAME: (<vscale x 16 x i8> [[A:%.*]]) #[[ATTR0]] {
1221 // CHECK-NEXT:  entry:
1222 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <vscale x 16 x i8>, align 16
1223 // CHECK-NEXT:    [[VEC:%.*]] = alloca <vscale x 16 x i8>, align 16
1224 // CHECK-NEXT:    store <vscale x 16 x i8> [[A]], ptr [[A_ADDR]], align 16
1225 // CHECK-NEXT:    [[TMP0:%.*]] = load <vscale x 16 x i8>, ptr [[A_ADDR]], align 16
1226 // CHECK-NEXT:    store <vscale x 16 x i8> [[TMP0]], ptr [[VEC]], align 16
1227 // CHECK-NEXT:    ret void
1228 //
1229 void test_copy_s8_typedef(__SVInt8_t a) {
1230   vec_t vec{a};
1231 }
1232