1 /* $OpenBSD: ehci.c,v 1.222 2024/10/11 09:55:24 kettenis Exp $ */ 2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2014-2015 Martin Pieuchot 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 /* 20 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 21 * All rights reserved. 22 * 23 * This code is derived from software contributed to The NetBSD Foundation 24 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 25 * Jeremy Morse (jeremy.morse@gmail.com). 26 * 27 * Redistribution and use in source and binary forms, with or without 28 * modification, are permitted provided that the following conditions 29 * are met: 30 * 1. Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * 2. Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in the 34 * documentation and/or other materials provided with the distribution. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 38 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 39 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 40 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 41 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 42 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 43 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 44 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 45 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 46 * POSSIBILITY OF SUCH DAMAGE. 47 */ 48 49 /* 50 * TODO: 51 * 1) The hub driver needs to handle and schedule the transaction translator, 52 * to assign place in frame where different devices get to go. See chapter 53 * on hubs in USB 2.0 for details. 54 * 55 * 2) Command failures are not recovered correctly. 56 */ 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/rwlock.h> 61 #include <sys/malloc.h> 62 #include <sys/device.h> 63 #include <sys/queue.h> 64 #include <sys/timeout.h> 65 #include <sys/pool.h> 66 #include <sys/endian.h> 67 #include <sys/atomic.h> 68 69 #include <machine/bus.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usb_mem.h> 75 76 #include <dev/usb/ehcireg.h> 77 #include <dev/usb/ehcivar.h> 78 79 struct cfdriver ehci_cd = { 80 NULL, "ehci", DV_DULL, CD_SKIPHIBERNATE 81 }; 82 83 #ifdef EHCI_DEBUG 84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 86 int ehcidebug = 0; 87 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 88 #else 89 #define DPRINTF(x) 90 #define DPRINTFN(n,x) 91 #endif 92 93 struct pool *ehcixfer; 94 95 struct ehci_pipe { 96 struct usbd_pipe pipe; 97 98 struct ehci_soft_qh *sqh; 99 union { 100 /* Control pipe */ 101 struct { 102 struct usb_dma reqdma; 103 } ctl; 104 /* Iso pipe */ 105 struct { 106 u_int next_frame; 107 u_int cur_xfers; 108 } isoc; 109 } u; 110 }; 111 112 u_int8_t ehci_reverse_bits(u_int8_t, int); 113 114 usbd_status ehci_open(struct usbd_pipe *); 115 int ehci_setaddr(struct usbd_device *, int); 116 void ehci_poll(struct usbd_bus *); 117 void ehci_softintr(void *); 118 int ehci_intr1(struct ehci_softc *); 119 void ehci_check_intr(struct ehci_softc *, struct usbd_xfer *); 120 void ehci_check_qh_intr(struct ehci_softc *, struct usbd_xfer *); 121 void ehci_check_itd_intr(struct ehci_softc *, struct usbd_xfer *); 122 void ehci_idone(struct usbd_xfer *); 123 void ehci_isoc_idone(struct usbd_xfer *); 124 void ehci_timeout(void *); 125 void ehci_timeout_task(void *); 126 void ehci_intrlist_timeout(void *); 127 128 struct usbd_xfer *ehci_allocx(struct usbd_bus *); 129 void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 130 131 usbd_status ehci_root_ctrl_transfer(struct usbd_xfer *); 132 usbd_status ehci_root_ctrl_start(struct usbd_xfer *); 133 void ehci_root_ctrl_abort(struct usbd_xfer *); 134 void ehci_root_ctrl_close(struct usbd_pipe *); 135 void ehci_root_ctrl_done(struct usbd_xfer *); 136 137 usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 138 usbd_status ehci_root_intr_start(struct usbd_xfer *); 139 void ehci_root_intr_abort(struct usbd_xfer *); 140 void ehci_root_intr_close(struct usbd_pipe *); 141 void ehci_root_intr_done(struct usbd_xfer *); 142 143 usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 144 usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 145 void ehci_device_ctrl_abort(struct usbd_xfer *); 146 void ehci_device_ctrl_close(struct usbd_pipe *); 147 void ehci_device_ctrl_done(struct usbd_xfer *); 148 149 usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 150 usbd_status ehci_device_bulk_start(struct usbd_xfer *); 151 void ehci_device_bulk_abort(struct usbd_xfer *); 152 void ehci_device_bulk_close(struct usbd_pipe *); 153 void ehci_device_bulk_done(struct usbd_xfer *); 154 155 usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 156 usbd_status ehci_device_intr_start(struct usbd_xfer *); 157 void ehci_device_intr_abort(struct usbd_xfer *); 158 void ehci_device_intr_close(struct usbd_pipe *); 159 void ehci_device_intr_done(struct usbd_xfer *); 160 161 usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 162 usbd_status ehci_device_isoc_start(struct usbd_xfer *); 163 void ehci_device_isoc_abort(struct usbd_xfer *); 164 void ehci_device_isoc_close(struct usbd_pipe *); 165 void ehci_device_isoc_done(struct usbd_xfer *); 166 167 void ehci_device_clear_toggle(struct usbd_pipe *pipe); 168 169 void ehci_pcd(struct ehci_softc *, struct usbd_xfer *); 170 void ehci_disown(struct ehci_softc *, int, int); 171 172 struct ehci_soft_qh *ehci_alloc_sqh(struct ehci_softc *); 173 void ehci_free_sqh(struct ehci_softc *, struct ehci_soft_qh *); 174 175 struct ehci_soft_qtd *ehci_alloc_sqtd(struct ehci_softc *); 176 void ehci_free_sqtd(struct ehci_softc *, struct ehci_soft_qtd *); 177 usbd_status ehci_alloc_sqtd_chain(struct ehci_softc *, u_int, 178 struct usbd_xfer *, struct ehci_soft_qtd **, struct ehci_soft_qtd **); 179 void ehci_free_sqtd_chain(struct ehci_softc *, struct ehci_xfer *); 180 181 struct ehci_soft_itd *ehci_alloc_itd(struct ehci_softc *); 182 void ehci_free_itd(struct ehci_softc *, struct ehci_soft_itd *); 183 void ehci_rem_itd_chain(struct ehci_softc *, struct ehci_xfer *); 184 void ehci_free_itd_chain(struct ehci_softc *, struct ehci_xfer *); 185 int ehci_alloc_itd_chain(struct ehci_softc *, struct usbd_xfer *); 186 int ehci_alloc_sitd_chain(struct ehci_softc *, struct usbd_xfer *); 187 void ehci_abort_isoc_xfer(struct usbd_xfer *xfer, 188 usbd_status status); 189 190 usbd_status ehci_device_setintr(struct ehci_softc *, struct ehci_soft_qh *, 191 int ival); 192 193 void ehci_add_qh(struct ehci_soft_qh *, struct ehci_soft_qh *); 194 void ehci_rem_qh(struct ehci_softc *, struct ehci_soft_qh *); 195 void ehci_set_qh_qtd(struct ehci_soft_qh *, struct ehci_soft_qtd *); 196 void ehci_sync_hc(struct ehci_softc *); 197 198 void ehci_close_pipe(struct usbd_pipe *); 199 void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 200 201 #ifdef EHCI_DEBUG 202 void ehci_dump_regs(struct ehci_softc *); 203 void ehci_dump(void); 204 struct ehci_softc *theehci; 205 void ehci_dump_link(ehci_link_t, int); 206 void ehci_dump_sqtds(struct ehci_soft_qtd *); 207 void ehci_dump_sqtd(struct ehci_soft_qtd *); 208 void ehci_dump_qtd(struct ehci_qtd *); 209 void ehci_dump_sqh(struct ehci_soft_qh *); 210 #if notyet 211 void ehci_dump_itd(struct ehci_soft_itd *); 212 #endif 213 #ifdef DIAGNOSTIC 214 void ehci_dump_exfer(struct ehci_xfer *); 215 #endif 216 #endif 217 218 #define EHCI_INTR_ENDPT 1 219 220 const struct usbd_bus_methods ehci_bus_methods = { 221 .open_pipe = ehci_open, 222 .dev_setaddr = ehci_setaddr, 223 .soft_intr = ehci_softintr, 224 .do_poll = ehci_poll, 225 .allocx = ehci_allocx, 226 .freex = ehci_freex, 227 }; 228 229 const struct usbd_pipe_methods ehci_root_ctrl_methods = { 230 .transfer = ehci_root_ctrl_transfer, 231 .start = ehci_root_ctrl_start, 232 .abort = ehci_root_ctrl_abort, 233 .close = ehci_root_ctrl_close, 234 .done = ehci_root_ctrl_done, 235 }; 236 237 const struct usbd_pipe_methods ehci_root_intr_methods = { 238 .transfer = ehci_root_intr_transfer, 239 .start = ehci_root_intr_start, 240 .abort = ehci_root_intr_abort, 241 .close = ehci_root_intr_close, 242 .done = ehci_root_intr_done, 243 }; 244 245 const struct usbd_pipe_methods ehci_device_ctrl_methods = { 246 .transfer = ehci_device_ctrl_transfer, 247 .start = ehci_device_ctrl_start, 248 .abort = ehci_device_ctrl_abort, 249 .close = ehci_device_ctrl_close, 250 .done = ehci_device_ctrl_done, 251 }; 252 253 const struct usbd_pipe_methods ehci_device_intr_methods = { 254 .transfer = ehci_device_intr_transfer, 255 .start = ehci_device_intr_start, 256 .abort = ehci_device_intr_abort, 257 .close = ehci_device_intr_close, 258 .cleartoggle = ehci_device_clear_toggle, 259 .done = ehci_device_intr_done, 260 }; 261 262 const struct usbd_pipe_methods ehci_device_bulk_methods = { 263 .transfer = ehci_device_bulk_transfer, 264 .start = ehci_device_bulk_start, 265 .abort = ehci_device_bulk_abort, 266 .close = ehci_device_bulk_close, 267 .cleartoggle = ehci_device_clear_toggle, 268 .done = ehci_device_bulk_done, 269 }; 270 271 const struct usbd_pipe_methods ehci_device_isoc_methods = { 272 .transfer = ehci_device_isoc_transfer, 273 .start = ehci_device_isoc_start, 274 .abort = ehci_device_isoc_abort, 275 .close = ehci_device_isoc_close, 276 .done = ehci_device_isoc_done, 277 }; 278 279 /* 280 * Reverse a number with nbits bits. Used to evenly distribute lower-level 281 * interrupt heads in the periodic schedule. 282 * Suitable for use with EHCI_IPOLLRATES <= 9. 283 */ 284 u_int8_t 285 ehci_reverse_bits(u_int8_t c, int nbits) 286 { 287 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa); 288 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc); 289 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0); 290 291 return c >> (8 - nbits); 292 } 293 294 usbd_status 295 ehci_init(struct ehci_softc *sc) 296 { 297 u_int32_t sparams, cparams, hcr; 298 u_int i, j; 299 usbd_status err; 300 struct ehci_soft_qh *sqh; 301 302 #ifdef EHCI_DEBUG 303 u_int32_t vers; 304 theehci = sc; 305 306 DPRINTF(("ehci_init: start\n")); 307 308 vers = EREAD2(sc, EHCI_HCIVERSION); 309 DPRINTF(("%s: EHCI version %x.%x\n", sc->sc_bus.bdev.dv_xname, 310 vers >> 8, vers & 0xff)); 311 #endif 312 313 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 314 315 sparams = EREAD4(sc, EHCI_HCSPARAMS); 316 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 317 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 318 cparams = EREAD4(sc, EHCI_HCCPARAMS); 319 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 320 321 /* MUST clear segment register if 64 bit capable. */ 322 if (EHCI_HCC_64BIT(cparams)) 323 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 324 325 sc->sc_bus.usbrev = USBREV_2_0; 326 327 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 328 err = ehci_reset(sc); 329 if (err) 330 return (err); 331 332 if (ehcixfer == NULL) { 333 ehcixfer = malloc(sizeof(struct pool), M_USBHC, M_NOWAIT); 334 if (ehcixfer == NULL) { 335 printf("%s: unable to allocate pool descriptor\n", 336 sc->sc_bus.bdev.dv_xname); 337 return (ENOMEM); 338 } 339 pool_init(ehcixfer, sizeof(struct ehci_xfer), 0, IPL_SOFTUSB, 340 0, "ehcixfer", NULL); 341 } 342 343 /* frame list size at default, read back what we got and use that */ 344 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 345 case 0: 346 sc->sc_flsize = 1024; 347 break; 348 case 1: 349 sc->sc_flsize = 512; 350 break; 351 case 2: 352 sc->sc_flsize = 256; 353 break; 354 case 3: 355 return (USBD_IOERROR); 356 } 357 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 358 EHCI_FLALIGN_ALIGN, USB_DMA_COHERENT, &sc->sc_fldma); 359 if (err) 360 return (err); 361 DPRINTF(("%s: flsize=%d\n", sc->sc_bus.bdev.dv_xname,sc->sc_flsize)); 362 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 363 364 for (i = 0; i < sc->sc_flsize; i++) 365 sc->sc_flist[i] = htole32(EHCI_LINK_TERMINATE); 366 367 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 368 369 sc->sc_softitds = mallocarray(sc->sc_flsize, 370 sizeof(struct ehci_soft_itd *), M_USBHC, M_NOWAIT | M_ZERO); 371 if (sc->sc_softitds == NULL) { 372 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 373 return (ENOMEM); 374 } 375 LIST_INIT(&sc->sc_freeitds); 376 TAILQ_INIT(&sc->sc_intrhead); 377 378 /* Set up the bus struct. */ 379 sc->sc_bus.methods = &ehci_bus_methods; 380 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 381 382 sc->sc_eintrs = EHCI_NORMAL_INTRS; 383 384 /* 385 * Allocate the interrupt dummy QHs. These are arranged to give poll 386 * intervals that are powers of 2 times 1ms. 387 */ 388 for (i = 0; i < EHCI_INTRQHS; i++) { 389 sqh = ehci_alloc_sqh(sc); 390 if (sqh == NULL) { 391 err = USBD_NOMEM; 392 goto bad1; 393 } 394 sc->sc_islots[i].sqh = sqh; 395 } 396 for (i = 0; i < EHCI_INTRQHS; i++) { 397 sqh = sc->sc_islots[i].sqh; 398 if (i == 0) { 399 /* The last (1ms) QH terminates. */ 400 sqh->qh.qh_link = htole32(EHCI_LINK_TERMINATE); 401 sqh->next = NULL; 402 } else { 403 /* Otherwise the next QH has half the poll interval */ 404 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 405 sqh->qh.qh_link = htole32(sqh->next->physaddr | 406 EHCI_LINK_QH); 407 } 408 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 409 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 410 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 411 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 412 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 413 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 414 sqh->sqtd = NULL; 415 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 416 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 417 } 418 /* Point the frame list at the last level (128ms). */ 419 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++) 420 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1)) 421 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[ 422 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits( 423 i, EHCI_IPOLLRATES - 1))].sqh->physaddr); 424 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 425 BUS_DMASYNC_PREWRITE); 426 427 /* Allocate dummy QH that starts the async list. */ 428 sqh = ehci_alloc_sqh(sc); 429 if (sqh == NULL) { 430 err = USBD_NOMEM; 431 goto bad1; 432 } 433 /* Fill the QH */ 434 sqh->qh.qh_endp = 435 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 436 sqh->qh.qh_link = 437 htole32(sqh->physaddr | EHCI_LINK_QH); 438 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 439 sqh->prev = sqh; /*It's a circular list.. */ 440 sqh->next = sqh; 441 /* Fill the overlay qTD */ 442 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 443 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 444 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 445 sqh->sqtd = NULL; 446 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 447 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 448 449 /* Point to async list */ 450 sc->sc_async_head = sqh; 451 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 452 453 timeout_set(&sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 454 455 rw_init(&sc->sc_doorbell_lock, "ehcidb"); 456 457 /* Turn on controller */ 458 EOWRITE4(sc, EHCI_USBCMD, 459 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 460 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 461 EHCI_CMD_ASE | 462 EHCI_CMD_PSE | 463 EHCI_CMD_RS); 464 465 /* Take over port ownership */ 466 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 467 468 for (i = 0; i < 100; i++) { 469 usb_delay_ms(&sc->sc_bus, 1); 470 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 471 if (!hcr) 472 break; 473 } 474 if (hcr) { 475 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 476 return (USBD_IOERROR); 477 } 478 479 /* Enable interrupts */ 480 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 481 482 return (USBD_NORMAL_COMPLETION); 483 484 #if 0 485 bad2: 486 ehci_free_sqh(sc, sc->sc_async_head); 487 #endif 488 bad1: 489 free(sc->sc_softitds, M_USBHC, 490 sc->sc_flsize * sizeof(struct ehci_soft_itd *)); 491 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 492 return (err); 493 } 494 495 int 496 ehci_intr(void *v) 497 { 498 struct ehci_softc *sc = v; 499 500 if (sc == NULL || sc->sc_bus.dying) 501 return (0); 502 503 /* If we get an interrupt while polling, then just ignore it. */ 504 if (sc->sc_bus.use_polling) { 505 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 506 507 if (intrs) 508 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 509 return (0); 510 } 511 512 return (ehci_intr1(sc)); 513 } 514 515 int 516 ehci_intr1(struct ehci_softc *sc) 517 { 518 u_int32_t intrs, eintrs; 519 520 /* In case the interrupt occurs before initialization has completed. */ 521 if (sc == NULL) { 522 #ifdef DIAGNOSTIC 523 printf("ehci_intr1: sc == NULL\n"); 524 #endif 525 return (0); 526 } 527 528 intrs = EOREAD4(sc, EHCI_USBSTS); 529 if (intrs == 0xffffffff) { 530 sc->sc_bus.dying = 1; 531 return (0); 532 } 533 intrs = EHCI_STS_INTRS(intrs); 534 if (!intrs) 535 return (0); 536 537 eintrs = intrs & sc->sc_eintrs; 538 if (!eintrs) 539 return (0); 540 541 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 542 sc->sc_bus.no_intrs++; 543 544 if (eintrs & EHCI_STS_HSE) { 545 printf("%s: unrecoverable error, controller halted\n", 546 sc->sc_bus.bdev.dv_xname); 547 sc->sc_bus.dying = 1; 548 return (1); 549 } 550 if (eintrs & EHCI_STS_IAA) { 551 wakeup(&sc->sc_async_head); 552 eintrs &= ~EHCI_STS_IAA; 553 } 554 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 555 usb_schedsoftintr(&sc->sc_bus); 556 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 557 } 558 if (eintrs & EHCI_STS_PCD) { 559 atomic_setbits_int(&sc->sc_flags, EHCIF_PCB_INTR); 560 usb_schedsoftintr(&sc->sc_bus); 561 eintrs &= ~EHCI_STS_PCD; 562 } 563 564 if (eintrs != 0) { 565 /* Block unprocessed interrupts. */ 566 sc->sc_eintrs &= ~eintrs; 567 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 568 printf("%s: blocking intrs 0x%x\n", 569 sc->sc_bus.bdev.dv_xname, eintrs); 570 } 571 572 return (1); 573 } 574 575 void 576 ehci_pcd(struct ehci_softc *sc, struct usbd_xfer *xfer) 577 { 578 u_char *p; 579 int i, m; 580 581 if (xfer == NULL) { 582 /* Just ignore the change. */ 583 return; 584 } 585 586 p = KERNADDR(&xfer->dmabuf, 0); 587 m = min(sc->sc_noport, xfer->length * 8 - 1); 588 memset(p, 0, xfer->length); 589 for (i = 1; i <= m; i++) { 590 /* Pick out CHANGE bits from the status reg. */ 591 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 592 p[i / 8] |= 1 << (i % 8); 593 } 594 xfer->actlen = xfer->length; 595 xfer->status = USBD_NORMAL_COMPLETION; 596 597 usb_transfer_complete(xfer); 598 } 599 600 /* 601 * Work around the half configured control (default) pipe when setting 602 * the address of a device. 603 * 604 * Because a single QH is setup per endpoint in ehci_open(), and the 605 * control pipe is configured before we could have set the address 606 * of the device or read the wMaxPacketSize of the endpoint, we have 607 * to re-open the pipe twice here. 608 */ 609 int 610 ehci_setaddr(struct usbd_device *dev, int addr) 611 { 612 /* Root Hub */ 613 if (dev->depth == 0) 614 return (0); 615 616 /* Re-establish the default pipe with the new max packet size. */ 617 ehci_close_pipe(dev->default_pipe); 618 if (ehci_open(dev->default_pipe)) 619 return (EINVAL); 620 621 if (usbd_set_address(dev, addr)) 622 return (1); 623 624 dev->address = addr; 625 626 /* Re-establish the default pipe with the new address. */ 627 ehci_close_pipe(dev->default_pipe); 628 if (ehci_open(dev->default_pipe)) 629 return (EINVAL); 630 631 return (0); 632 } 633 634 void 635 ehci_softintr(void *v) 636 { 637 struct ehci_softc *sc = v; 638 struct ehci_xfer *ex, *nextex; 639 640 if (sc->sc_bus.dying) 641 return; 642 643 sc->sc_bus.intr_context++; 644 645 if (sc->sc_flags & EHCIF_PCB_INTR) { 646 atomic_clearbits_int(&sc->sc_flags, EHCIF_PCB_INTR); 647 ehci_pcd(sc, sc->sc_intrxfer); 648 } 649 650 /* 651 * The only explanation I can think of for why EHCI is as brain dead 652 * as UHCI interrupt-wise is that Intel was involved in both. 653 * An interrupt just tells us that something is done, we have no 654 * clue what, so we need to scan through all active transfers. :-( 655 */ 656 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 657 nextex = TAILQ_NEXT(ex, inext); 658 ehci_check_intr(sc, &ex->xfer); 659 } 660 661 /* Schedule a callout to catch any dropped transactions. */ 662 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 663 !TAILQ_EMPTY(&sc->sc_intrhead)) { 664 timeout_add_sec(&sc->sc_tmo_intrlist, 1); 665 } 666 667 if (sc->sc_softwake) { 668 sc->sc_softwake = 0; 669 wakeup(&sc->sc_softwake); 670 } 671 672 sc->sc_bus.intr_context--; 673 } 674 675 void 676 ehci_check_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 677 { 678 int attr = xfer->pipe->endpoint->edesc->bmAttributes; 679 680 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 681 ehci_check_itd_intr(sc, xfer); 682 else 683 ehci_check_qh_intr(sc, xfer); 684 } 685 686 void 687 ehci_check_qh_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 688 { 689 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 690 struct ehci_soft_qtd *sqtd, *lsqtd = ex->sqtdend; 691 uint32_t status; 692 693 KASSERT(ex->sqtdstart != NULL && ex->sqtdend != NULL); 694 695 usb_syncmem(&lsqtd->dma, 696 lsqtd->offs + offsetof(struct ehci_qtd, qtd_status), 697 sizeof(lsqtd->qtd.qtd_status), 698 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 699 700 /* 701 * If the last TD is still active we need to check whether there 702 * is a an error somewhere in the middle, or whether there was a 703 * short packet (SPD and not ACTIVE). 704 */ 705 if (letoh32(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 706 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 707 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 708 usb_syncmem(&sqtd->dma, 709 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 710 sizeof(sqtd->qtd.qtd_status), 711 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 712 status = letoh32(sqtd->qtd.qtd_status); 713 usb_syncmem(&sqtd->dma, 714 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 715 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 716 /* If there's an active QTD the xfer isn't done. */ 717 if (status & EHCI_QTD_ACTIVE) 718 break; 719 /* Any kind of error makes the xfer done. */ 720 if (status & EHCI_QTD_HALTED) 721 goto done; 722 /* We want short packets, and it is short: it's done */ 723 if (EHCI_QTD_GET_BYTES(status) != 0) 724 goto done; 725 } 726 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 727 ex, ex->sqtdstart)); 728 usb_syncmem(&lsqtd->dma, 729 lsqtd->offs + offsetof(struct ehci_qtd, qtd_status), 730 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 731 return; 732 } 733 done: 734 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 735 timeout_del(&xfer->timeout_handle); 736 usb_rem_task(xfer->pipe->device, &xfer->abort_task); 737 ehci_idone(xfer); 738 } 739 740 void 741 ehci_check_itd_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 742 { 743 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 744 struct ehci_soft_itd *itd = ex->itdend; 745 int i; 746 747 if (xfer != SIMPLEQ_FIRST(&xfer->pipe->queue)) 748 return; 749 750 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 751 752 /* Check no active transfers in last itd, meaning we're finished */ 753 if (xfer->device->speed == USB_SPEED_HIGH) { 754 usb_syncmem(&itd->dma, 755 itd->offs + offsetof(struct ehci_itd, itd_ctl), 756 sizeof(itd->itd.itd_ctl), 757 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 758 759 for (i = 0; i < 8; i++) { 760 if (letoh32(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 761 return; 762 } 763 } else { 764 usb_syncmem(&itd->dma, 765 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 766 sizeof(itd->sitd.sitd_trans), 767 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 768 769 if (le32toh(itd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 770 return; 771 } 772 773 /* All descriptor(s) inactive, it's done */ 774 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 775 timeout_del(&xfer->timeout_handle); 776 usb_rem_task(xfer->pipe->device, &xfer->abort_task); 777 ehci_isoc_idone(xfer); 778 } 779 780 void 781 ehci_isoc_idone(struct usbd_xfer *xfer) 782 { 783 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 784 struct ehci_soft_itd *itd; 785 int i, len, uframes, nframes = 0, actlen = 0; 786 uint32_t status = 0; 787 788 if (xfer->status == USBD_CANCELLED || xfer->status == USBD_TIMEOUT) 789 return; 790 791 if (xfer->device->speed == USB_SPEED_HIGH) { 792 switch (xfer->pipe->endpoint->edesc->bInterval) { 793 case 0: 794 panic("isoc xfer suddenly has 0 bInterval, invalid"); 795 case 1: 796 uframes = 1; 797 break; 798 case 2: 799 uframes = 2; 800 break; 801 case 3: 802 uframes = 4; 803 break; 804 default: 805 uframes = 8; 806 break; 807 } 808 809 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 810 usb_syncmem(&itd->dma, 811 itd->offs + offsetof(struct ehci_itd, itd_ctl), 812 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 813 BUS_DMASYNC_POSTREAD); 814 815 for (i = 0; i < 8; i += uframes) { 816 /* XXX - driver didn't fill in the frame full 817 * of uframes. This leads to scheduling 818 * inefficiencies, but working around 819 * this doubles complexity of tracking 820 * an xfer. 821 */ 822 if (nframes >= xfer->nframes) 823 break; 824 825 status = letoh32(itd->itd.itd_ctl[i]); 826 len = EHCI_ITD_GET_LEN(status); 827 if (EHCI_ITD_GET_STATUS(status) != 0) 828 len = 0; /*No valid data on error*/ 829 830 xfer->frlengths[nframes++] = len; 831 actlen += len; 832 } 833 } 834 } else { 835 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 836 usb_syncmem(&itd->dma, 837 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 838 sizeof(itd->sitd.sitd_trans), 839 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 840 841 status = le32toh(itd->sitd.sitd_trans); 842 len = EHCI_SITD_GET_LEN(status); 843 if (xfer->frlengths[nframes] >= len) 844 len = xfer->frlengths[nframes] - len; 845 else 846 len = 0; 847 848 xfer->frlengths[nframes++] = len; 849 actlen += len; 850 } 851 } 852 853 #ifdef DIAGNOSTIC 854 ex->isdone = 1; 855 #endif 856 xfer->actlen = actlen; 857 xfer->status = USBD_NORMAL_COMPLETION; 858 859 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 860 usbd_xfer_isread(xfer) ? 861 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 862 usb_transfer_complete(xfer); 863 } 864 865 void 866 ehci_idone(struct usbd_xfer *xfer) 867 { 868 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 869 struct ehci_soft_qtd *sqtd; 870 u_int32_t status = 0, nstatus = 0; 871 int actlen, cerr; 872 873 #ifdef DIAGNOSTIC 874 { 875 int s = splhigh(); 876 if (ex->isdone) { 877 splx(s); 878 printf("ehci_idone: ex=%p is done!\n", ex); 879 return; 880 } 881 ex->isdone = 1; 882 splx(s); 883 } 884 #endif 885 if (xfer->status == USBD_CANCELLED || xfer->status == USBD_TIMEOUT) 886 return; 887 888 actlen = 0; 889 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 890 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 891 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 892 nstatus = letoh32(sqtd->qtd.qtd_status); 893 if (nstatus & EHCI_QTD_ACTIVE) 894 break; 895 896 status = nstatus; 897 /* halt is ok if descriptor is last, and complete */ 898 if (sqtd->qtd.qtd_next == htole32(EHCI_LINK_TERMINATE) && 899 EHCI_QTD_GET_BYTES(status) == 0) 900 status &= ~EHCI_QTD_HALTED; 901 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 902 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 903 } 904 905 cerr = EHCI_QTD_GET_CERR(status); 906 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 907 "status=0x%x\n", xfer->length, actlen, cerr, status)); 908 xfer->actlen = actlen; 909 if ((status & EHCI_QTD_HALTED) != 0) { 910 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0) 911 xfer->status = USBD_STALLED; 912 else 913 xfer->status = USBD_IOERROR; /* more info XXX */ 914 } else 915 xfer->status = USBD_NORMAL_COMPLETION; 916 917 if (xfer->actlen) 918 usb_syncmem(&xfer->dmabuf, 0, xfer->actlen, 919 usbd_xfer_isread(xfer) ? 920 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 921 usb_transfer_complete(xfer); 922 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 923 } 924 925 void 926 ehci_poll(struct usbd_bus *bus) 927 { 928 struct ehci_softc *sc = (struct ehci_softc *)bus; 929 930 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 931 ehci_intr1(sc); 932 } 933 934 int 935 ehci_detach(struct device *self, int flags) 936 { 937 struct ehci_softc *sc = (struct ehci_softc *)self; 938 int rv; 939 940 rv = config_detach_children(self, flags); 941 if (rv != 0) 942 return (rv); 943 944 timeout_del(&sc->sc_tmo_intrlist); 945 946 ehci_reset(sc); 947 948 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 949 950 free(sc->sc_softitds, M_USBHC, 951 sc->sc_flsize * sizeof(struct ehci_soft_itd *)); 952 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 953 /* XXX free other data structures XXX */ 954 955 return (rv); 956 } 957 958 959 int 960 ehci_activate(struct device *self, int act) 961 { 962 struct ehci_softc *sc = (struct ehci_softc *)self; 963 u_int32_t cmd, hcr, cparams; 964 int i, rv = 0; 965 966 switch (act) { 967 case DVACT_SUSPEND: 968 rv = config_activate_children(self, act); 969 970 #ifdef DIAGNOSTIC 971 if (!TAILQ_EMPTY(&sc->sc_intrhead)) { 972 printf("%s: interrupt list not empty\n", 973 sc->sc_bus.bdev.dv_xname); 974 return (-1); 975 } 976 #endif 977 978 sc->sc_bus.use_polling++; 979 980 for (i = 1; i <= sc->sc_noport; i++) { 981 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 982 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE) 983 EOWRITE4(sc, EHCI_PORTSC(i), 984 cmd | EHCI_PS_SUSP); 985 } 986 987 /* 988 * First tell the host to stop processing Asynchronous 989 * and Periodic schedules. 990 */ 991 cmd = EOREAD4(sc, EHCI_USBCMD) & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 992 EOWRITE4(sc, EHCI_USBCMD, cmd); 993 for (i = 0; i < 100; i++) { 994 usb_delay_ms(&sc->sc_bus, 1); 995 hcr = EOREAD4(sc, EHCI_USBSTS) & 996 (EHCI_STS_ASS | EHCI_STS_PSS); 997 if (hcr == 0) 998 break; 999 } 1000 if (hcr != 0) 1001 printf("%s: disable schedules timeout\n", 1002 sc->sc_bus.bdev.dv_xname); 1003 1004 /* 1005 * Then reset the host as if it was a shutdown. 1006 * 1007 * All USB devices are disconnected/reconnected during 1008 * a suspend/resume cycle so keep it simple. 1009 */ 1010 ehci_reset(sc); 1011 1012 sc->sc_bus.use_polling--; 1013 break; 1014 case DVACT_RESUME: 1015 sc->sc_bus.use_polling++; 1016 1017 ehci_reset(sc); 1018 1019 cparams = EREAD4(sc, EHCI_HCCPARAMS); 1020 /* MUST clear segment register if 64 bit capable. */ 1021 if (EHCI_HCC_64BIT(cparams)) 1022 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1023 1024 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1025 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1026 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1027 1028 hcr = 0; 1029 for (i = 1; i <= sc->sc_noport; i++) { 1030 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1031 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP) { 1032 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1033 hcr = 1; 1034 } 1035 } 1036 1037 if (hcr) { 1038 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1039 for (i = 1; i <= sc->sc_noport; i++) { 1040 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1041 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == 1042 EHCI_PS_SUSP) 1043 EOWRITE4(sc, EHCI_PORTSC(i), 1044 cmd & ~EHCI_PS_FPR); 1045 } 1046 } 1047 1048 /* Turn on controller */ 1049 EOWRITE4(sc, EHCI_USBCMD, 1050 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 1051 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 1052 EHCI_CMD_ASE | 1053 EHCI_CMD_PSE | 1054 EHCI_CMD_RS); 1055 1056 /* Take over port ownership */ 1057 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 1058 for (i = 0; i < 100; i++) { 1059 usb_delay_ms(&sc->sc_bus, 1); 1060 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1061 if (!hcr) 1062 break; 1063 } 1064 1065 if (hcr) { 1066 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 1067 /* XXX should we bail here? */ 1068 } 1069 1070 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1071 1072 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1073 1074 sc->sc_bus.use_polling--; 1075 rv = config_activate_children(self, act); 1076 break; 1077 case DVACT_POWERDOWN: 1078 rv = config_activate_children(self, act); 1079 ehci_reset(sc); 1080 break; 1081 default: 1082 rv = config_activate_children(self, act); 1083 break; 1084 } 1085 return (rv); 1086 } 1087 1088 usbd_status 1089 ehci_reset(struct ehci_softc *sc) 1090 { 1091 u_int32_t hcr, usbmode; 1092 int i; 1093 1094 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1095 for (i = 0; i < 100; i++) { 1096 usb_delay_ms(&sc->sc_bus, 1); 1097 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1098 if (hcr) 1099 break; 1100 } 1101 1102 if (!hcr) 1103 printf("%s: halt timeout\n", sc->sc_bus.bdev.dv_xname); 1104 1105 if (sc->sc_flags & EHCIF_USBMODE) 1106 usbmode = EOREAD4(sc, EHCI_USBMODE); 1107 1108 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1109 for (i = 0; i < 100; i++) { 1110 usb_delay_ms(&sc->sc_bus, 1); 1111 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 1112 if (!hcr) 1113 break; 1114 } 1115 1116 if (hcr) { 1117 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname); 1118 return (USBD_IOERROR); 1119 } 1120 1121 if (sc->sc_flags & EHCIF_USBMODE) 1122 EOWRITE4(sc, EHCI_USBMODE, usbmode); 1123 1124 return (USBD_NORMAL_COMPLETION); 1125 } 1126 1127 struct usbd_xfer * 1128 ehci_allocx(struct usbd_bus *bus) 1129 { 1130 struct ehci_xfer *ex; 1131 1132 ex = pool_get(ehcixfer, PR_NOWAIT | PR_ZERO); 1133 #ifdef DIAGNOSTIC 1134 if (ex != NULL) 1135 ex->isdone = 1; 1136 #endif 1137 return ((struct usbd_xfer *)ex); 1138 } 1139 1140 void 1141 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1142 { 1143 struct ehci_xfer *ex = (struct ehci_xfer*)xfer; 1144 1145 #ifdef DIAGNOSTIC 1146 if (!ex->isdone) { 1147 printf("%s: !isdone\n", __func__); 1148 return; 1149 } 1150 #endif 1151 pool_put(ehcixfer, ex); 1152 } 1153 1154 void 1155 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1156 { 1157 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1158 1159 #ifdef DIAGNOSTIC 1160 if ((epipe->sqh->qh.qh_qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) != 0) 1161 printf("%s: queue active\n", __func__); 1162 #endif 1163 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1164 } 1165 1166 #ifdef EHCI_DEBUG 1167 void 1168 ehci_dump_regs(struct ehci_softc *sc) 1169 { 1170 int i; 1171 1172 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1173 EOREAD4(sc, EHCI_USBCMD), 1174 EOREAD4(sc, EHCI_USBSTS), 1175 EOREAD4(sc, EHCI_USBINTR)); 1176 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1177 EOREAD4(sc, EHCI_FRINDEX), 1178 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1179 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1180 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1181 for (i = 1; i <= sc->sc_noport; i++) 1182 printf("port %d status=0x%08x\n", i, 1183 EOREAD4(sc, EHCI_PORTSC(i))); 1184 } 1185 1186 /* 1187 * Unused function - this is meant to be called from a kernel 1188 * debugger. 1189 */ 1190 void 1191 ehci_dump(void) 1192 { 1193 ehci_dump_regs(theehci); 1194 } 1195 1196 void 1197 ehci_dump_link(ehci_link_t link, int type) 1198 { 1199 link = letoh32(link); 1200 printf("0x%08x", link); 1201 if (link & EHCI_LINK_TERMINATE) 1202 printf("<T>"); 1203 else { 1204 printf("<"); 1205 if (type) { 1206 switch (EHCI_LINK_TYPE(link)) { 1207 case EHCI_LINK_ITD: 1208 printf("ITD"); 1209 break; 1210 case EHCI_LINK_QH: 1211 printf("QH"); 1212 break; 1213 case EHCI_LINK_SITD: 1214 printf("SITD"); 1215 break; 1216 case EHCI_LINK_FSTN: 1217 printf("FSTN"); 1218 break; 1219 } 1220 } 1221 printf(">"); 1222 } 1223 } 1224 1225 void 1226 ehci_dump_sqtds(struct ehci_soft_qtd *sqtd) 1227 { 1228 int i; 1229 u_int32_t stop; 1230 1231 stop = 0; 1232 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1233 ehci_dump_sqtd(sqtd); 1234 usb_syncmem(&sqtd->dma, 1235 sqtd->offs + offsetof(struct ehci_qtd, qtd_next), 1236 sizeof(sqtd->qtd), 1237 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1238 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1239 usb_syncmem(&sqtd->dma, 1240 sqtd->offs + offsetof(struct ehci_qtd, qtd_next), 1241 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1242 } 1243 if (!stop) 1244 printf("dump aborted, too many TDs\n"); 1245 } 1246 1247 void 1248 ehci_dump_sqtd(struct ehci_soft_qtd *sqtd) 1249 { 1250 usb_syncmem(&sqtd->dma, sqtd->offs, 1251 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1252 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1253 ehci_dump_qtd(&sqtd->qtd); 1254 usb_syncmem(&sqtd->dma, sqtd->offs, 1255 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1256 } 1257 1258 void 1259 ehci_dump_qtd(struct ehci_qtd *qtd) 1260 { 1261 u_int32_t s; 1262 char sbuf[128]; 1263 1264 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1265 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1266 printf("\n"); 1267 s = letoh32(qtd->qtd_status); 1268 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED" 1269 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING", 1270 sbuf, sizeof(sbuf)); 1271 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1272 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1273 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1274 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1275 EHCI_QTD_GET_PID(s), sbuf); 1276 for (s = 0; s < 5; s++) 1277 printf(" buffer[%d]=0x%08x\n", s, letoh32(qtd->qtd_buffer[s])); 1278 } 1279 1280 void 1281 ehci_dump_sqh(struct ehci_soft_qh *sqh) 1282 { 1283 struct ehci_qh *qh = &sqh->qh; 1284 u_int32_t endp, endphub; 1285 1286 usb_syncmem(&sqh->dma, sqh->offs, 1287 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1288 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1289 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1290 endp = letoh32(qh->qh_endp); 1291 printf(" endp=0x%08x\n", endp); 1292 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1293 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1294 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1295 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1296 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1297 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1298 EHCI_QH_GET_NRL(endp)); 1299 endphub = letoh32(qh->qh_endphub); 1300 printf(" endphub=0x%08x\n", endphub); 1301 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1302 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1303 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1304 EHCI_QH_GET_MULT(endphub)); 1305 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1306 printf("Overlay qTD:\n"); 1307 ehci_dump_qtd(&qh->qh_qtd); 1308 usb_syncmem(&sqh->dma, sqh->offs, 1309 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1310 } 1311 1312 #if notyet 1313 void 1314 ehci_dump_itd(struct ehci_soft_itd *itd) 1315 { 1316 ehci_isoc_trans_t t; 1317 ehci_isoc_bufr_ptr_t b, b2, b3; 1318 int i; 1319 1320 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1321 1322 for (i = 0; i < 8; i++) { 1323 t = letoh32(itd->itd.itd_ctl[i]); 1324 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1325 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1326 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1327 EHCI_ITD_GET_OFFS(t)); 1328 } 1329 printf("ITDbufr: "); 1330 for (i = 0; i < 7; i++) 1331 printf("%X,", EHCI_ITD_GET_BPTR(letoh32(itd->itd.itd_bufr[i]))); 1332 1333 b = letoh32(itd->itd.itd_bufr[0]); 1334 b2 = letoh32(itd->itd.itd_bufr[1]); 1335 b3 = letoh32(itd->itd.itd_bufr[2]); 1336 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1337 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1338 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1339 } 1340 #endif 1341 1342 #ifdef DIAGNOSTIC 1343 void 1344 ehci_dump_exfer(struct ehci_xfer *ex) 1345 { 1346 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p " 1347 "isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, 1348 ex->itdend, ex->isdone); 1349 } 1350 #endif 1351 1352 #endif /* EHCI_DEBUG */ 1353 1354 usbd_status 1355 ehci_open(struct usbd_pipe *pipe) 1356 { 1357 struct usbd_device *dev = pipe->device; 1358 struct ehci_softc *sc = (struct ehci_softc *)dev->bus; 1359 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1360 u_int8_t addr = dev->address; 1361 u_int8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1362 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1363 struct ehci_soft_qh *sqh; 1364 usbd_status err; 1365 int s; 1366 int ival, speed, naks; 1367 int hshubaddr, hshubport; 1368 1369 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d\n", 1370 pipe, addr, ed->bEndpointAddress)); 1371 1372 if (sc->sc_bus.dying) 1373 return (USBD_IOERROR); 1374 1375 if (dev->myhsport) { 1376 hshubaddr = dev->myhsport->parent->address; 1377 hshubport = dev->myhsport->portno; 1378 } else { 1379 hshubaddr = 0; 1380 hshubport = 0; 1381 } 1382 1383 /* Root Hub */ 1384 if (pipe->device->depth == 0) { 1385 switch (ed->bEndpointAddress) { 1386 case USB_CONTROL_ENDPOINT: 1387 pipe->methods = &ehci_root_ctrl_methods; 1388 break; 1389 case UE_DIR_IN | EHCI_INTR_ENDPT: 1390 pipe->methods = &ehci_root_intr_methods; 1391 break; 1392 default: 1393 return (USBD_INVAL); 1394 } 1395 return (USBD_NORMAL_COMPLETION); 1396 } 1397 1398 /* XXX All this stuff is only valid for async. */ 1399 switch (dev->speed) { 1400 case USB_SPEED_LOW: 1401 speed = EHCI_QH_SPEED_LOW; 1402 break; 1403 case USB_SPEED_FULL: 1404 speed = EHCI_QH_SPEED_FULL; 1405 break; 1406 case USB_SPEED_HIGH: 1407 speed = EHCI_QH_SPEED_HIGH; 1408 break; 1409 default: 1410 panic("ehci_open: bad device speed %d", dev->speed); 1411 } 1412 1413 /* 1414 * NAK reload count: 1415 * must be zero with using periodic transfer. 1416 * Linux 4.20's driver (ehci-q.c) sets 4, we use same value. 1417 */ 1418 naks = ((xfertype == UE_CONTROL) || (xfertype == UE_BULK)) ? 4 : 0; 1419 1420 /* Allocate sqh for everything, save isoc xfers */ 1421 if (xfertype != UE_ISOCHRONOUS) { 1422 sqh = ehci_alloc_sqh(sc); 1423 if (sqh == NULL) 1424 return (USBD_NOMEM); 1425 /* qh_link filled when the QH is added */ 1426 sqh->qh.qh_endp = htole32( 1427 EHCI_QH_SET_ADDR(addr) | 1428 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1429 EHCI_QH_SET_EPS(speed) | 1430 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1431 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1432 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1433 EHCI_QH_CTL : 0) | 1434 EHCI_QH_SET_NRL(naks) 1435 ); 1436 /* 1437 * To reduce conflict with split isochronous transfer, 1438 * schedule (split) interrupt transfer at latter half of 1439 * 1ms frame: 1440 * 1441 * |<-------------- H-Frame -------------->| 1442 * .H0 :H1 H2 H3 H4 H5 H6 H7 .H0" :H1" 1443 * . : . : 1444 * [HS] . : SS CS CS' CS" . : 1445 * [FS/LS] . : |<== >>>> >>>| . : 1446 * . : . : 1447 * .B7' :B0 B1 B2 B3 B4 B5 B6 .B7 :B0" 1448 * |<-------------- B-Frame -------------->| 1449 * 1450 */ 1451 sqh->qh.qh_endphub = htole32( 1452 EHCI_QH_SET_MULT(1) | 1453 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x08 : 0) 1454 ); 1455 if (speed != EHCI_QH_SPEED_HIGH) { 1456 sqh->qh.qh_endphub |= htole32( 1457 EHCI_QH_SET_HUBA(hshubaddr) | 1458 EHCI_QH_SET_PORT(hshubport) | 1459 EHCI_QH_SET_CMASK(0xe0) 1460 ); 1461 } 1462 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 1463 /* Fill the overlay qTD */ 1464 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 1465 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1466 sqh->qh.qh_qtd.qtd_status = 1467 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1468 1469 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1470 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1471 epipe->sqh = sqh; 1472 } /*xfertype == UE_ISOC*/ 1473 1474 switch (xfertype) { 1475 case UE_CONTROL: 1476 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1477 0, USB_DMA_COHERENT, &epipe->u.ctl.reqdma); 1478 if (err) { 1479 ehci_free_sqh(sc, sqh); 1480 return (err); 1481 } 1482 pipe->methods = &ehci_device_ctrl_methods; 1483 s = splusb(); 1484 ehci_add_qh(sqh, sc->sc_async_head); 1485 splx(s); 1486 break; 1487 case UE_BULK: 1488 pipe->methods = &ehci_device_bulk_methods; 1489 s = splusb(); 1490 ehci_add_qh(sqh, sc->sc_async_head); 1491 splx(s); 1492 break; 1493 case UE_INTERRUPT: 1494 pipe->methods = &ehci_device_intr_methods; 1495 ival = pipe->interval; 1496 if (ival == USBD_DEFAULT_INTERVAL) 1497 ival = ed->bInterval; 1498 s = splusb(); 1499 err = ehci_device_setintr(sc, sqh, ival); 1500 splx(s); 1501 return (err); 1502 case UE_ISOCHRONOUS: 1503 switch (speed) { 1504 case EHCI_QH_SPEED_HIGH: 1505 case EHCI_QH_SPEED_FULL: 1506 pipe->methods = &ehci_device_isoc_methods; 1507 break; 1508 case EHCI_QH_SPEED_LOW: 1509 default: 1510 return (USBD_INVAL); 1511 } 1512 /* Spec page 271 says intervals > 16 are invalid */ 1513 if (ed->bInterval == 0 || ed->bInterval > 16) { 1514 printf("ehci: opening pipe with invalid bInterval\n"); 1515 return (USBD_INVAL); 1516 } 1517 if (UGETW(ed->wMaxPacketSize) == 0) { 1518 printf("ehci: zero length endpoint open request\n"); 1519 return (USBD_INVAL); 1520 } 1521 epipe->u.isoc.next_frame = 0; 1522 epipe->u.isoc.cur_xfers = 0; 1523 break; 1524 default: 1525 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1526 return (USBD_INVAL); 1527 } 1528 return (USBD_NORMAL_COMPLETION); 1529 } 1530 1531 /* 1532 * Add an ED to the schedule. Called at splusb(). 1533 * If in the async schedule, it will always have a next. 1534 * If in the intr schedule it may not. 1535 */ 1536 void 1537 ehci_add_qh(struct ehci_soft_qh *sqh, struct ehci_soft_qh *head) 1538 { 1539 splsoftassert(IPL_SOFTUSB); 1540 1541 usb_syncmem(&head->dma, head->offs + offsetof(struct ehci_qh, qh_link), 1542 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1543 sqh->next = head->next; 1544 sqh->prev = head; 1545 sqh->qh.qh_link = head->qh.qh_link; 1546 usb_syncmem(&sqh->dma, sqh->offs + offsetof(struct ehci_qh, qh_link), 1547 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1548 head->next = sqh; 1549 if (sqh->next) 1550 sqh->next->prev = sqh; 1551 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1552 usb_syncmem(&head->dma, head->offs + offsetof(struct ehci_qh, qh_link), 1553 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1554 } 1555 1556 /* 1557 * Remove an ED from the schedule. Called at splusb(). 1558 * Will always have a 'next' if it's in the async list as it's circular. 1559 */ 1560 void 1561 ehci_rem_qh(struct ehci_softc *sc, struct ehci_soft_qh *sqh) 1562 { 1563 splsoftassert(IPL_SOFTUSB); 1564 /* XXX */ 1565 usb_syncmem(&sqh->dma, sqh->offs + offsetof(struct ehci_qh, qh_link), 1566 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1567 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1568 sqh->prev->next = sqh->next; 1569 if (sqh->next) 1570 sqh->next->prev = sqh->prev; 1571 usb_syncmem(&sqh->prev->dma, 1572 sqh->prev->offs + offsetof(struct ehci_qh, qh_link), 1573 sizeof(sqh->prev->qh.qh_link), BUS_DMASYNC_PREWRITE); 1574 1575 ehci_sync_hc(sc); 1576 } 1577 1578 void 1579 ehci_set_qh_qtd(struct ehci_soft_qh *sqh, struct ehci_soft_qtd *sqtd) 1580 { 1581 int i; 1582 u_int32_t status; 1583 1584 /* Save toggle bit and ping status. */ 1585 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1586 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1587 status = sqh->qh.qh_qtd.qtd_status & 1588 htole32(EHCI_QTD_TOGGLE_MASK | 1589 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1590 /* Set HALTED to make hw leave it alone. */ 1591 sqh->qh.qh_qtd.qtd_status = 1592 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1593 usb_syncmem(&sqh->dma, 1594 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 1595 sizeof(sqh->qh.qh_qtd.qtd_status), 1596 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1597 sqh->qh.qh_curqtd = 0; 1598 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1599 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1600 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1601 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1602 sqh->sqtd = sqtd; 1603 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1604 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1605 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1606 sqh->qh.qh_qtd.qtd_status = status; 1607 usb_syncmem(&sqh->dma, 1608 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 1609 sizeof(sqh->qh.qh_qtd.qtd_status), 1610 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1611 } 1612 1613 /* 1614 * Ensure that the HC has released all references to the QH. We do this 1615 * by asking for a Async Advance Doorbell interrupt and then we wait for 1616 * the interrupt. 1617 * To make this easier we first obtain exclusive use of the doorbell. 1618 */ 1619 void 1620 ehci_sync_hc(struct ehci_softc *sc) 1621 { 1622 int s, error; 1623 int tries = 0; 1624 1625 if (sc->sc_bus.dying) { 1626 return; 1627 } 1628 1629 /* get doorbell */ 1630 rw_enter_write(&sc->sc_doorbell_lock); 1631 s = splhardusb(); 1632 do { 1633 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | 1634 EHCI_CMD_IAAD); 1635 error = tsleep_nsec(&sc->sc_async_head, PZERO, "ehcidi", 1636 MSEC_TO_NSEC(500)); 1637 } while (error && ++tries < 10); 1638 splx(s); 1639 /* release doorbell */ 1640 rw_exit_write(&sc->sc_doorbell_lock); 1641 #ifdef DIAGNOSTIC 1642 if (error) 1643 printf("ehci_sync_hc: tsleep() = %d\n", error); 1644 #endif 1645 } 1646 1647 void 1648 ehci_rem_itd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 1649 { 1650 struct ehci_soft_itd *itd, *prev = NULL; 1651 1652 splsoftassert(IPL_SOFTUSB); 1653 1654 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 1655 1656 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1657 prev = itd->u.frame_list.prev; 1658 /* Unlink itd from hardware chain, or frame array */ 1659 if (prev == NULL) { /* We're at the table head */ 1660 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1661 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1662 usb_syncmem(&sc->sc_fldma, 1663 sizeof(uint32_t) * itd->slot, sizeof(uint32_t), 1664 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1665 1666 if (itd->u.frame_list.next != NULL) 1667 itd->u.frame_list.next->u.frame_list.prev = 1668 NULL; 1669 } else { 1670 /* XXX this part is untested... */ 1671 prev->itd.itd_next = itd->itd.itd_next; 1672 usb_syncmem(&itd->dma, 1673 itd->offs + offsetof(struct ehci_itd, itd_next), 1674 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1675 1676 prev->u.frame_list.next = itd->u.frame_list.next; 1677 if (itd->u.frame_list.next != NULL) 1678 itd->u.frame_list.next->u.frame_list.prev = 1679 prev; 1680 } 1681 } 1682 } 1683 1684 void 1685 ehci_free_itd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 1686 { 1687 struct ehci_soft_itd *itd, *prev = NULL; 1688 1689 splsoftassert(IPL_SOFTUSB); 1690 1691 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 1692 1693 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1694 if (prev != NULL) 1695 ehci_free_itd(sc, prev); 1696 prev = itd; 1697 } 1698 if (prev) 1699 ehci_free_itd(sc, prev); 1700 ex->itdstart = NULL; 1701 ex->itdend = NULL; 1702 } 1703 1704 /* 1705 * Data structures and routines to emulate the root hub. 1706 */ 1707 const usb_device_descriptor_t ehci_devd = { 1708 USB_DEVICE_DESCRIPTOR_SIZE, 1709 UDESC_DEVICE, /* type */ 1710 {0x00, 0x02}, /* USB version */ 1711 UDCLASS_HUB, /* class */ 1712 UDSUBCLASS_HUB, /* subclass */ 1713 UDPROTO_HSHUBSTT, /* protocol */ 1714 64, /* max packet */ 1715 {0},{0},{0x00,0x01}, /* device id */ 1716 1,2,0, /* string indices */ 1717 1 /* # of configurations */ 1718 }; 1719 1720 const usb_device_qualifier_t ehci_odevd = { 1721 USB_DEVICE_DESCRIPTOR_SIZE, 1722 UDESC_DEVICE_QUALIFIER, /* type */ 1723 {0x00, 0x02}, /* USB version */ 1724 UDCLASS_HUB, /* class */ 1725 UDSUBCLASS_HUB, /* subclass */ 1726 UDPROTO_FSHUB, /* protocol */ 1727 64, /* max packet */ 1728 1, /* # of configurations */ 1729 0 1730 }; 1731 1732 const usb_config_descriptor_t ehci_confd = { 1733 USB_CONFIG_DESCRIPTOR_SIZE, 1734 UDESC_CONFIG, 1735 {USB_CONFIG_DESCRIPTOR_SIZE + 1736 USB_INTERFACE_DESCRIPTOR_SIZE + 1737 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1738 1, 1739 1, 1740 0, 1741 UC_BUS_POWERED | UC_SELF_POWERED, 1742 0 /* max power */ 1743 }; 1744 1745 const usb_interface_descriptor_t ehci_ifcd = { 1746 USB_INTERFACE_DESCRIPTOR_SIZE, 1747 UDESC_INTERFACE, 1748 0, 1749 0, 1750 1, 1751 UICLASS_HUB, 1752 UISUBCLASS_HUB, 1753 UIPROTO_HSHUBSTT, 1754 0 1755 }; 1756 1757 const usb_endpoint_descriptor_t ehci_endpd = { 1758 USB_ENDPOINT_DESCRIPTOR_SIZE, 1759 UDESC_ENDPOINT, 1760 UE_DIR_IN | EHCI_INTR_ENDPT, 1761 UE_INTERRUPT, 1762 {8, 0}, /* max packet */ 1763 12 1764 }; 1765 1766 const usb_hub_descriptor_t ehci_hubd = { 1767 USB_HUB_DESCRIPTOR_SIZE, 1768 UDESC_HUB, 1769 0, 1770 {0,0}, 1771 0, 1772 0, 1773 {0}, 1774 }; 1775 1776 /* 1777 * Simulate a hardware hub by handling all the necessary requests. 1778 */ 1779 usbd_status 1780 ehci_root_ctrl_transfer(struct usbd_xfer *xfer) 1781 { 1782 usbd_status err; 1783 1784 /* Insert last in queue. */ 1785 err = usb_insert_transfer(xfer); 1786 if (err) 1787 return (err); 1788 1789 /* Pipe isn't running, start first */ 1790 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1791 } 1792 1793 usbd_status 1794 ehci_root_ctrl_start(struct usbd_xfer *xfer) 1795 { 1796 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1797 usb_device_request_t *req; 1798 void *buf = NULL; 1799 int port, i; 1800 int s, len, value, index, l, totlen = 0; 1801 usb_port_status_t ps; 1802 usb_device_descriptor_t devd; 1803 usb_hub_descriptor_t hubd; 1804 usbd_status err; 1805 u_int32_t v; 1806 1807 if (sc->sc_bus.dying) 1808 return (USBD_IOERROR); 1809 1810 #ifdef DIAGNOSTIC 1811 if (!(xfer->rqflags & URQ_REQUEST)) 1812 /* XXX panic */ 1813 return (USBD_INVAL); 1814 #endif 1815 req = &xfer->request; 1816 1817 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1818 req->bmRequestType, req->bRequest)); 1819 1820 len = UGETW(req->wLength); 1821 value = UGETW(req->wValue); 1822 index = UGETW(req->wIndex); 1823 1824 if (len != 0) 1825 buf = KERNADDR(&xfer->dmabuf, 0); 1826 1827 #define C(x,y) ((x) | ((y) << 8)) 1828 switch(C(req->bRequest, req->bmRequestType)) { 1829 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1830 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1831 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1832 /* 1833 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1834 * for the integrated root hub. 1835 */ 1836 break; 1837 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1838 if (len > 0) { 1839 *(u_int8_t *)buf = sc->sc_conf; 1840 totlen = 1; 1841 } 1842 break; 1843 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1844 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1845 switch(value >> 8) { 1846 case UDESC_DEVICE: 1847 if ((value & 0xff) != 0) { 1848 err = USBD_IOERROR; 1849 goto ret; 1850 } 1851 devd = ehci_devd; 1852 USETW(devd.idVendor, sc->sc_id_vendor); 1853 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1854 memcpy(buf, &devd, l); 1855 break; 1856 case UDESC_DEVICE_QUALIFIER: 1857 if ((value & 0xff) != 0) { 1858 err = USBD_IOERROR; 1859 goto ret; 1860 } 1861 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1862 memcpy(buf, &ehci_odevd, l); 1863 break; 1864 /* 1865 * We can't really operate at another speed, but the spec says 1866 * we need this descriptor. 1867 */ 1868 case UDESC_OTHER_SPEED_CONFIGURATION: 1869 case UDESC_CONFIG: 1870 if ((value & 0xff) != 0) { 1871 err = USBD_IOERROR; 1872 goto ret; 1873 } 1874 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1875 memcpy(buf, &ehci_confd, l); 1876 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1877 value >> 8; 1878 buf = (char *)buf + l; 1879 len -= l; 1880 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1881 totlen += l; 1882 memcpy(buf, &ehci_ifcd, l); 1883 buf = (char *)buf + l; 1884 len -= l; 1885 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1886 totlen += l; 1887 memcpy(buf, &ehci_endpd, l); 1888 break; 1889 case UDESC_STRING: 1890 if (len == 0) 1891 break; 1892 *(u_int8_t *)buf = 0; 1893 totlen = 1; 1894 switch (value & 0xff) { 1895 case 0: /* Language table */ 1896 totlen = usbd_str(buf, len, "\001"); 1897 break; 1898 case 1: /* Vendor */ 1899 totlen = usbd_str(buf, len, sc->sc_vendor); 1900 break; 1901 case 2: /* Product */ 1902 totlen = usbd_str(buf, len, "EHCI root hub"); 1903 break; 1904 } 1905 break; 1906 default: 1907 err = USBD_IOERROR; 1908 goto ret; 1909 } 1910 break; 1911 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1912 if (len > 0) { 1913 *(u_int8_t *)buf = 0; 1914 totlen = 1; 1915 } 1916 break; 1917 case C(UR_GET_STATUS, UT_READ_DEVICE): 1918 if (len > 1) { 1919 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1920 totlen = 2; 1921 } 1922 break; 1923 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1924 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1925 if (len > 1) { 1926 USETW(((usb_status_t *)buf)->wStatus, 0); 1927 totlen = 2; 1928 } 1929 break; 1930 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1931 if (value >= USB_MAX_DEVICES) { 1932 err = USBD_IOERROR; 1933 goto ret; 1934 } 1935 break; 1936 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1937 if (value != 0 && value != 1) { 1938 err = USBD_IOERROR; 1939 goto ret; 1940 } 1941 sc->sc_conf = value; 1942 break; 1943 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1944 break; 1945 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1946 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1947 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1948 err = USBD_IOERROR; 1949 goto ret; 1950 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1951 break; 1952 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1953 break; 1954 /* Hub requests */ 1955 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1956 break; 1957 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1958 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 1959 "port=%d feature=%d\n", index, value)); 1960 if (index < 1 || index > sc->sc_noport) { 1961 err = USBD_IOERROR; 1962 goto ret; 1963 } 1964 port = EHCI_PORTSC(index); 1965 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1966 switch(value) { 1967 case UHF_PORT_ENABLE: 1968 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 1969 break; 1970 case UHF_PORT_SUSPEND: 1971 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 1972 break; 1973 case UHF_PORT_POWER: 1974 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 1975 break; 1976 case UHF_PORT_TEST: 1977 DPRINTFN(2,("ehci_root_ctrl_start: " 1978 "clear port test %d\n", index)); 1979 break; 1980 case UHF_PORT_INDICATOR: 1981 DPRINTFN(2,("ehci_root_ctrl_start: " 1982 "clear port index %d\n", index)); 1983 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 1984 break; 1985 case UHF_C_PORT_CONNECTION: 1986 EOWRITE4(sc, port, v | EHCI_PS_CSC); 1987 break; 1988 case UHF_C_PORT_ENABLE: 1989 EOWRITE4(sc, port, v | EHCI_PS_PEC); 1990 break; 1991 case UHF_C_PORT_SUSPEND: 1992 /* how? */ 1993 break; 1994 case UHF_C_PORT_OVER_CURRENT: 1995 EOWRITE4(sc, port, v | EHCI_PS_OCC); 1996 break; 1997 case UHF_C_PORT_RESET: 1998 sc->sc_isreset = 0; 1999 break; 2000 default: 2001 err = USBD_IOERROR; 2002 goto ret; 2003 } 2004 break; 2005 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2006 if ((value & 0xff) != 0) { 2007 err = USBD_IOERROR; 2008 goto ret; 2009 } 2010 hubd = ehci_hubd; 2011 hubd.bNbrPorts = sc->sc_noport; 2012 v = EREAD4(sc, EHCI_HCSPARAMS); 2013 USETW(hubd.wHubCharacteristics, 2014 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2015 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2016 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2017 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2018 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2019 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2020 l = min(len, hubd.bDescLength); 2021 totlen = l; 2022 memcpy(buf, &hubd, l); 2023 break; 2024 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2025 if (len != 4) { 2026 err = USBD_IOERROR; 2027 goto ret; 2028 } 2029 memset(buf, 0, len); /* ? XXX */ 2030 totlen = len; 2031 break; 2032 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2033 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2034 index)); 2035 if (index < 1 || index > sc->sc_noport) { 2036 err = USBD_IOERROR; 2037 goto ret; 2038 } 2039 if (len != 4) { 2040 err = USBD_IOERROR; 2041 goto ret; 2042 } 2043 v = EOREAD4(sc, EHCI_PORTSC(index)); 2044 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2045 i = UPS_HIGH_SPEED; 2046 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2047 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2048 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2049 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2050 if (v & EHCI_PS_PR) i |= UPS_RESET; 2051 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2052 USETW(ps.wPortStatus, i); 2053 i = 0; 2054 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2055 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2056 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2057 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2058 USETW(ps.wPortChange, i); 2059 l = min(len, sizeof(ps)); 2060 memcpy(buf, &ps, l); 2061 totlen = l; 2062 break; 2063 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2064 err = USBD_IOERROR; 2065 goto ret; 2066 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2067 break; 2068 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2069 if (index < 1 || index > sc->sc_noport) { 2070 err = USBD_IOERROR; 2071 goto ret; 2072 } 2073 port = EHCI_PORTSC(index); 2074 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2075 switch(value) { 2076 case UHF_PORT_ENABLE: 2077 EOWRITE4(sc, port, v | EHCI_PS_PE); 2078 break; 2079 case UHF_PORT_SUSPEND: 2080 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2081 break; 2082 case UHF_PORT_DISOWN_TO_1_1: 2083 /* enter to Port Reset State */ 2084 v &= ~EHCI_PS_PE; 2085 EOWRITE4(sc, port, v | EHCI_PS_PR); 2086 ehci_disown(sc, index, 0); 2087 break; 2088 case UHF_PORT_RESET: 2089 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2090 index)); 2091 if (EHCI_PS_IS_LOWSPEED(v)) { 2092 /* Low speed device, give up ownership. */ 2093 ehci_disown(sc, index, 1); 2094 break; 2095 } 2096 /* Start reset sequence. */ 2097 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2098 EOWRITE4(sc, port, v | EHCI_PS_PR); 2099 /* Wait for reset to complete. */ 2100 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2101 if (sc->sc_bus.dying) { 2102 err = USBD_IOERROR; 2103 goto ret; 2104 } 2105 /* Terminate reset sequence. */ 2106 v = EOREAD4(sc, port); 2107 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2108 /* Wait for HC to complete reset. */ 2109 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2110 if (sc->sc_bus.dying) { 2111 err = USBD_IOERROR; 2112 goto ret; 2113 } 2114 v = EOREAD4(sc, port); 2115 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2116 if (v & EHCI_PS_PR) { 2117 printf("%s: port reset timeout\n", 2118 sc->sc_bus.bdev.dv_xname); 2119 err = USBD_IOERROR; 2120 goto ret; 2121 } 2122 if (!(v & EHCI_PS_PE)) { 2123 /* Not a high speed device, give up ownership.*/ 2124 ehci_disown(sc, index, 0); 2125 break; 2126 } 2127 sc->sc_isreset = 1; 2128 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2129 index, v)); 2130 break; 2131 case UHF_PORT_POWER: 2132 DPRINTFN(2,("ehci_root_ctrl_start: " 2133 "set port power %d\n", index)); 2134 EOWRITE4(sc, port, v | EHCI_PS_PP); 2135 break; 2136 case UHF_PORT_TEST: 2137 DPRINTFN(2,("ehci_root_ctrl_start: " 2138 "set port test %d\n", index)); 2139 break; 2140 case UHF_PORT_INDICATOR: 2141 DPRINTFN(2,("ehci_root_ctrl_start: " 2142 "set port ind %d\n", index)); 2143 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2144 break; 2145 default: 2146 err = USBD_IOERROR; 2147 goto ret; 2148 } 2149 break; 2150 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2151 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2152 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2153 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2154 break; 2155 default: 2156 err = USBD_IOERROR; 2157 goto ret; 2158 } 2159 xfer->actlen = totlen; 2160 err = USBD_NORMAL_COMPLETION; 2161 ret: 2162 xfer->status = err; 2163 s = splusb(); 2164 usb_transfer_complete(xfer); 2165 splx(s); 2166 return (err); 2167 } 2168 2169 void 2170 ehci_disown(struct ehci_softc *sc, int index, int lowspeed) 2171 { 2172 int port; 2173 u_int32_t v; 2174 2175 port = EHCI_PORTSC(index); 2176 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2177 EOWRITE4(sc, port, v | EHCI_PS_PO); 2178 } 2179 2180 /* Abort a root control request. */ 2181 void 2182 ehci_root_ctrl_abort(struct usbd_xfer *xfer) 2183 { 2184 /* Nothing to do, all transfers are synchronous. */ 2185 } 2186 2187 /* Close the root pipe. */ 2188 void 2189 ehci_root_ctrl_close(struct usbd_pipe *pipe) 2190 { 2191 /* Nothing to do. */ 2192 } 2193 2194 void 2195 ehci_root_intr_done(struct usbd_xfer *xfer) 2196 { 2197 } 2198 2199 usbd_status 2200 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2201 { 2202 usbd_status err; 2203 2204 /* Insert last in queue. */ 2205 err = usb_insert_transfer(xfer); 2206 if (err) 2207 return (err); 2208 2209 /* Pipe isn't running, start first */ 2210 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2211 } 2212 2213 usbd_status 2214 ehci_root_intr_start(struct usbd_xfer *xfer) 2215 { 2216 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2217 2218 if (sc->sc_bus.dying) 2219 return (USBD_IOERROR); 2220 2221 sc->sc_intrxfer = xfer; 2222 2223 return (USBD_IN_PROGRESS); 2224 } 2225 2226 void 2227 ehci_root_intr_abort(struct usbd_xfer *xfer) 2228 { 2229 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2230 int s; 2231 2232 sc->sc_intrxfer = NULL; 2233 2234 xfer->status = USBD_CANCELLED; 2235 s = splusb(); 2236 usb_transfer_complete(xfer); 2237 splx(s); 2238 } 2239 2240 void 2241 ehci_root_intr_close(struct usbd_pipe *pipe) 2242 { 2243 } 2244 2245 void 2246 ehci_root_ctrl_done(struct usbd_xfer *xfer) 2247 { 2248 } 2249 2250 struct ehci_soft_qh * 2251 ehci_alloc_sqh(struct ehci_softc *sc) 2252 { 2253 struct ehci_soft_qh *sqh = NULL; 2254 usbd_status err; 2255 int i, offs; 2256 struct usb_dma dma; 2257 int s; 2258 2259 s = splusb(); 2260 if (sc->sc_freeqhs == NULL) { 2261 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2262 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2263 EHCI_PAGE_SIZE, USB_DMA_COHERENT, &dma); 2264 if (err) 2265 goto out; 2266 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2267 offs = i * EHCI_SQH_SIZE; 2268 sqh = KERNADDR(&dma, offs); 2269 sqh->physaddr = DMAADDR(&dma, offs); 2270 sqh->dma = dma; 2271 sqh->offs = offs; 2272 sqh->next = sc->sc_freeqhs; 2273 sc->sc_freeqhs = sqh; 2274 } 2275 } 2276 sqh = sc->sc_freeqhs; 2277 sc->sc_freeqhs = sqh->next; 2278 memset(&sqh->qh, 0, sizeof(struct ehci_qh)); 2279 sqh->next = NULL; 2280 sqh->prev = NULL; 2281 2282 out: 2283 splx(s); 2284 return (sqh); 2285 } 2286 2287 void 2288 ehci_free_sqh(struct ehci_softc *sc, struct ehci_soft_qh *sqh) 2289 { 2290 int s; 2291 2292 s = splusb(); 2293 sqh->next = sc->sc_freeqhs; 2294 sc->sc_freeqhs = sqh; 2295 splx(s); 2296 } 2297 2298 struct ehci_soft_qtd * 2299 ehci_alloc_sqtd(struct ehci_softc *sc) 2300 { 2301 struct ehci_soft_qtd *sqtd = NULL; 2302 usbd_status err; 2303 int i, offs; 2304 struct usb_dma dma; 2305 int s; 2306 2307 s = splusb(); 2308 if (sc->sc_freeqtds == NULL) { 2309 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2310 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2311 EHCI_PAGE_SIZE, USB_DMA_COHERENT, &dma); 2312 if (err) 2313 goto out; 2314 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2315 offs = i * EHCI_SQTD_SIZE; 2316 sqtd = KERNADDR(&dma, offs); 2317 sqtd->physaddr = DMAADDR(&dma, offs); 2318 sqtd->dma = dma; 2319 sqtd->offs = offs; 2320 sqtd->nextqtd = sc->sc_freeqtds; 2321 sc->sc_freeqtds = sqtd; 2322 } 2323 } 2324 2325 sqtd = sc->sc_freeqtds; 2326 sc->sc_freeqtds = sqtd->nextqtd; 2327 memset(&sqtd->qtd, 0, sizeof(struct ehci_qtd)); 2328 sqtd->nextqtd = NULL; 2329 2330 out: 2331 splx(s); 2332 return (sqtd); 2333 } 2334 2335 void 2336 ehci_free_sqtd(struct ehci_softc *sc, struct ehci_soft_qtd *sqtd) 2337 { 2338 int s; 2339 2340 s = splusb(); 2341 sqtd->nextqtd = sc->sc_freeqtds; 2342 sc->sc_freeqtds = sqtd; 2343 splx(s); 2344 } 2345 2346 usbd_status 2347 ehci_alloc_sqtd_chain(struct ehci_softc *sc, u_int alen, struct usbd_xfer *xfer, 2348 struct ehci_soft_qtd **sp, struct ehci_soft_qtd **ep) 2349 { 2350 struct ehci_soft_qtd *next, *cur; 2351 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2352 u_int32_t qtdstatus; 2353 u_int len, curlen; 2354 int mps, i, iscontrol, forceshort; 2355 int rd = usbd_xfer_isread(xfer); 2356 struct usb_dma *dma = &xfer->dmabuf; 2357 2358 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2359 2360 len = alen; 2361 iscontrol = UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) == 2362 UE_CONTROL; 2363 2364 dataphys = DMAADDR(dma, 0); 2365 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2366 qtdstatus = EHCI_QTD_ACTIVE | 2367 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2368 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */ 2369 mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize); 2370 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2371 len % mps == 0; 2372 /* 2373 * The control transfer data stage always starts with a toggle of 1. 2374 * For other transfers we let the hardware track the toggle state. 2375 */ 2376 if (iscontrol) 2377 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2378 2379 cur = ehci_alloc_sqtd(sc); 2380 *sp = cur; 2381 if (cur == NULL) 2382 goto nomem; 2383 2384 usb_syncmem(dma, 0, alen, 2385 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2386 for (;;) { 2387 dataphyspage = EHCI_PAGE(dataphys); 2388 /* The EHCI hardware can handle at most 5 pages. */ 2389 if (dataphyslastpage - dataphyspage < 2390 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2391 /* we can handle it in this QTD */ 2392 curlen = len; 2393 } else { 2394 /* must use multiple TDs, fill as much as possible. */ 2395 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2396 EHCI_PAGE_OFFSET(dataphys); 2397 2398 if (curlen > len) { 2399 DPRINTFN(1,("ehci_alloc_sqtd_chain: curlen=%u " 2400 "len=%u offs=0x%x\n", curlen, len, 2401 EHCI_PAGE_OFFSET(dataphys))); 2402 DPRINTFN(1,("lastpage=0x%x page=0x%x phys=0x%x\n", 2403 dataphyslastpage, dataphyspage, dataphys)); 2404 curlen = len; 2405 } 2406 2407 /* the length must be a multiple of the max size */ 2408 curlen -= curlen % mps; 2409 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2410 "curlen=%u\n", curlen)); 2411 } 2412 2413 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2414 "dataphyslastpage=0x%08x len=%u curlen=%u\n", 2415 dataphys, dataphyslastpage, len, curlen)); 2416 len -= curlen; 2417 2418 /* 2419 * Allocate another transfer if there's more data left, 2420 * or if force last short transfer flag is set and we're 2421 * allocating a multiple of the max packet size. 2422 */ 2423 if (len != 0 || forceshort) { 2424 next = ehci_alloc_sqtd(sc); 2425 if (next == NULL) 2426 goto nomem; 2427 nextphys = htole32(next->physaddr); 2428 } else { 2429 next = NULL; 2430 nextphys = htole32(EHCI_LINK_TERMINATE); 2431 } 2432 2433 for (i = 0; i * EHCI_PAGE_SIZE < 2434 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2435 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2436 if (i != 0) /* use offset only in first buffer */ 2437 a = EHCI_PAGE(a); 2438 #ifdef DIAGNOSTIC 2439 if (i >= EHCI_QTD_NBUFFERS) { 2440 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2441 goto nomem; 2442 } 2443 #endif 2444 cur->qtd.qtd_buffer[i] = htole32(a); 2445 cur->qtd.qtd_buffer_hi[i] = 0; 2446 } 2447 cur->nextqtd = next; 2448 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2449 cur->qtd.qtd_status = htole32(qtdstatus | 2450 EHCI_QTD_SET_BYTES(curlen)); 2451 cur->len = curlen; 2452 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2453 dataphys, dataphys + curlen)); 2454 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%u\n", curlen)); 2455 if (iscontrol) { 2456 /* 2457 * adjust the toggle based on the number of packets 2458 * in this qtd 2459 */ 2460 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2461 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2462 } 2463 if (len == 0) { 2464 if (! forceshort) 2465 break; 2466 forceshort = 0; 2467 } 2468 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2469 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2470 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2471 dataphys += curlen; 2472 cur = next; 2473 } 2474 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2475 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2476 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2477 *ep = cur; 2478 2479 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2480 *sp, *ep)); 2481 2482 return (USBD_NORMAL_COMPLETION); 2483 2484 nomem: 2485 /* XXX free chain */ 2486 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2487 return (USBD_NOMEM); 2488 } 2489 2490 void 2491 ehci_free_sqtd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 2492 { 2493 struct ehci_pipe *epipe = (struct ehci_pipe *)ex->xfer.pipe; 2494 struct ehci_soft_qtd *sqtd, *next; 2495 2496 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p\n", ex->sqtdstart)); 2497 2498 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = next) { 2499 next = sqtd->nextqtd; 2500 ehci_free_sqtd(sc, sqtd); 2501 } 2502 ex->sqtdstart = ex->sqtdend = NULL; 2503 epipe->sqh->sqtd = NULL; 2504 } 2505 2506 struct ehci_soft_itd * 2507 ehci_alloc_itd(struct ehci_softc *sc) 2508 { 2509 struct ehci_soft_itd *itd, *freeitd; 2510 usbd_status err; 2511 int i, s, offs, frindex, previndex; 2512 struct usb_dma dma; 2513 2514 s = splusb(); 2515 2516 /* Find an itd that wasn't freed this frame or last frame. This can 2517 * discard itds that were freed before frindex wrapped around 2518 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2519 * interrupt and fiddling with list when that happens */ 2520 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2521 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2522 2523 freeitd = NULL; 2524 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2525 if (itd->slot != frindex && itd->slot != previndex) { 2526 freeitd = itd; 2527 break; 2528 } 2529 } 2530 2531 if (freeitd == NULL) { 2532 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2533 EHCI_PAGE_SIZE, USB_DMA_COHERENT, &dma); 2534 if (err) { 2535 splx(s); 2536 return (NULL); 2537 } 2538 2539 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2540 offs = i * EHCI_ITD_SIZE; 2541 itd = KERNADDR(&dma, offs); 2542 itd->physaddr = DMAADDR(&dma, offs); 2543 itd->dma = dma; 2544 itd->offs = offs; 2545 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2546 } 2547 freeitd = LIST_FIRST(&sc->sc_freeitds); 2548 } 2549 2550 itd = freeitd; 2551 LIST_REMOVE(itd, u.free_list); 2552 memset(&itd->itd, 0, sizeof(struct ehci_itd)); 2553 usb_syncmem(&itd->dma, itd->offs + offsetof(struct ehci_itd, itd_next), 2554 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2555 BUS_DMASYNC_PREREAD); 2556 2557 itd->u.frame_list.next = NULL; 2558 itd->u.frame_list.prev = NULL; 2559 itd->xfer_next = NULL; 2560 itd->slot = 0; 2561 splx(s); 2562 2563 return (itd); 2564 } 2565 2566 void 2567 ehci_free_itd(struct ehci_softc *sc, struct ehci_soft_itd *itd) 2568 { 2569 int s; 2570 2571 s = splusb(); 2572 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2573 splx(s); 2574 } 2575 2576 /* 2577 * Close a regular pipe. 2578 * Assumes that there are no pending transactions. 2579 */ 2580 void 2581 ehci_close_pipe(struct usbd_pipe *pipe) 2582 { 2583 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2584 struct ehci_softc *sc = (struct ehci_softc *)pipe->device->bus; 2585 struct ehci_soft_qh *sqh = epipe->sqh; 2586 int s; 2587 2588 s = splusb(); 2589 ehci_rem_qh(sc, sqh); 2590 splx(s); 2591 pipe->endpoint->savedtoggle = 2592 EHCI_QTD_GET_TOGGLE(letoh32(sqh->qh.qh_qtd.qtd_status)); 2593 ehci_free_sqh(sc, epipe->sqh); 2594 } 2595 2596 /* 2597 * Abort a device request. 2598 * If this routine is called at splusb() it guarantees that the request 2599 * will be removed from the hardware scheduling and that the callback 2600 * for it will be called with USBD_CANCELLED status. 2601 * It's impossible to guarantee that the requested transfer will not 2602 * have happened since the hardware runs concurrently. 2603 * If the transaction has already happened we rely on the ordinary 2604 * interrupt processing to process it. 2605 */ 2606 void 2607 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2608 { 2609 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2610 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2611 struct ehci_xfer *ex = (struct ehci_xfer*)xfer; 2612 struct ehci_soft_qh *sqh = epipe->sqh; 2613 struct ehci_soft_qtd *sqtd; 2614 int s; 2615 2616 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 2617 s = splusb(); 2618 if (xfer->status != USBD_NOT_STARTED) 2619 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2620 xfer->status = status; /* make software ignore it */ 2621 timeout_del(&xfer->timeout_handle); 2622 usb_rem_task(xfer->device, &xfer->abort_task); 2623 #ifdef DIAGNOSTIC 2624 ex->isdone = 1; 2625 #endif 2626 usb_transfer_complete(xfer); 2627 splx(s); 2628 return; 2629 } 2630 2631 if (xfer->device->bus->intr_context) 2632 panic("ehci_abort_xfer: not in process context"); 2633 2634 /* 2635 * If an abort is already in progress then just wait for it to 2636 * complete and return. 2637 */ 2638 if (ex->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2639 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2640 /* No need to wait if we're aborting from a timeout. */ 2641 if (status == USBD_TIMEOUT) 2642 return; 2643 /* Override the status which might be USBD_TIMEOUT. */ 2644 xfer->status = status; 2645 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2646 ex->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2647 while (ex->ehci_xfer_flags & EHCI_XFER_ABORTING) 2648 tsleep_nsec(&ex->ehci_xfer_flags, PZERO, "ehciaw", INFSLP); 2649 return; 2650 } 2651 2652 /* 2653 * Step 1: Make interrupt routine and timeouts ignore xfer. 2654 */ 2655 s = splusb(); 2656 ex->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2657 xfer->status = status; /* make software ignore it */ 2658 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2659 timeout_del(&xfer->timeout_handle); 2660 usb_rem_task(xfer->device, &xfer->abort_task); 2661 splx(s); 2662 2663 /* 2664 * Step 2: Deactivate all of the qTDs that we will be removing, 2665 * otherwise the queue head may go active again. 2666 */ 2667 usb_syncmem(&sqh->dma, 2668 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 2669 sizeof(sqh->qh.qh_qtd.qtd_status), 2670 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2671 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2672 usb_syncmem(&sqh->dma, 2673 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 2674 sizeof(sqh->qh.qh_qtd.qtd_status), 2675 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2676 2677 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 2678 usb_syncmem(&sqtd->dma, 2679 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 2680 sizeof(sqtd->qtd.qtd_status), 2681 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2682 sqtd->qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2683 usb_syncmem(&sqtd->dma, 2684 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 2685 sizeof(sqtd->qtd.qtd_status), 2686 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2687 } 2688 ehci_sync_hc(sc); 2689 2690 /* 2691 * Step 3: Make sure the soft interrupt routine has run. This 2692 * should remove any completed items off the queue. 2693 * The hardware has no reference to completed items (TDs). 2694 * It's safe to remove them at any time. 2695 */ 2696 s = splusb(); 2697 sc->sc_softwake = 1; 2698 usb_schedsoftintr(&sc->sc_bus); 2699 tsleep_nsec(&sc->sc_softwake, PZERO, "ehciab", INFSLP); 2700 2701 #ifdef DIAGNOSTIC 2702 ex->isdone = 1; 2703 #endif 2704 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2705 ex->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 2706 if (ex->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 2707 ex->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 2708 wakeup(&ex->ehci_xfer_flags); 2709 } 2710 usb_transfer_complete(xfer); 2711 2712 splx(s); 2713 } 2714 2715 void 2716 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 2717 { 2718 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2719 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2720 ehci_isoc_trans_t trans_status; 2721 struct ehci_soft_itd *itd; 2722 int i; 2723 2724 splsoftassert(IPL_SOFTUSB); 2725 2726 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 2727 if (xfer->status != USBD_NOT_STARTED) 2728 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2729 xfer->status = status; 2730 timeout_del(&xfer->timeout_handle); 2731 usb_rem_task(xfer->device, &xfer->abort_task); 2732 usb_transfer_complete(xfer); 2733 return; 2734 } 2735 2736 /* Transfer is already done. */ 2737 if (xfer->status != USBD_IN_PROGRESS) { 2738 DPRINTF(("%s: already done \n", __func__)); 2739 return; 2740 } 2741 2742 2743 #ifdef DIAGNOSTIC 2744 ex->isdone = 1; 2745 #endif 2746 xfer->status = status; 2747 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2748 timeout_del(&xfer->timeout_handle); 2749 usb_rem_task(xfer->device, &xfer->abort_task); 2750 2751 if (xfer->device->speed == USB_SPEED_HIGH) { 2752 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 2753 usb_syncmem(&itd->dma, 2754 itd->offs + offsetof(struct ehci_itd, itd_ctl), 2755 sizeof(itd->itd.itd_ctl), 2756 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2757 2758 for (i = 0; i < 8; i++) { 2759 trans_status = le32toh(itd->itd.itd_ctl[i]); 2760 trans_status &= ~EHCI_ITD_ACTIVE; 2761 itd->itd.itd_ctl[i] = htole32(trans_status); 2762 } 2763 2764 usb_syncmem(&itd->dma, 2765 itd->offs + offsetof(struct ehci_itd, itd_ctl), 2766 sizeof(itd->itd.itd_ctl), 2767 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2768 } 2769 } else { 2770 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 2771 usb_syncmem(&itd->dma, 2772 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 2773 sizeof(itd->sitd.sitd_trans), 2774 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2775 2776 trans_status = le32toh(itd->sitd.sitd_trans); 2777 trans_status &= ~EHCI_SITD_ACTIVE; 2778 itd->sitd.sitd_trans = htole32(trans_status); 2779 2780 usb_syncmem(&itd->dma, 2781 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 2782 sizeof(itd->sitd.sitd_trans), 2783 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2784 } 2785 } 2786 2787 sc->sc_softwake = 1; 2788 usb_schedsoftintr(&sc->sc_bus); 2789 tsleep_nsec(&sc->sc_softwake, PZERO, "ehciab", INFSLP); 2790 2791 usb_transfer_complete(xfer); 2792 } 2793 2794 void 2795 ehci_timeout(void *addr) 2796 { 2797 struct usbd_xfer *xfer = addr; 2798 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2799 2800 if (sc->sc_bus.dying) { 2801 ehci_timeout_task(addr); 2802 return; 2803 } 2804 2805 usb_init_task(&xfer->abort_task, ehci_timeout_task, addr, 2806 USB_TASK_TYPE_ABORT); 2807 usb_add_task(xfer->device, &xfer->abort_task); 2808 } 2809 2810 void 2811 ehci_timeout_task(void *addr) 2812 { 2813 struct usbd_xfer *xfer = addr; 2814 int s; 2815 2816 s = splusb(); 2817 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2818 splx(s); 2819 } 2820 2821 /* 2822 * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing 2823 * back the qTD status, or miss signalling occasionally under heavy load. 2824 * If the host machine is too fast, we can miss transaction completion - when 2825 * we scan the active list the transaction still seems to be active. This 2826 * generally exhibits itself as a umass stall that never recovers. 2827 * 2828 * We work around this behaviour by setting up this callback after any softintr 2829 * that completes with transactions still pending, giving us another chance to 2830 * check for completion after the writeback has taken place. 2831 */ 2832 void 2833 ehci_intrlist_timeout(void *arg) 2834 { 2835 struct ehci_softc *sc = arg; 2836 int s; 2837 2838 if (sc->sc_bus.dying) 2839 return; 2840 2841 s = splusb(); 2842 DPRINTFN(1, ("ehci_intrlist_timeout\n")); 2843 usb_schedsoftintr(&sc->sc_bus); 2844 splx(s); 2845 } 2846 2847 usbd_status 2848 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 2849 { 2850 usbd_status err; 2851 2852 /* Insert last in queue. */ 2853 err = usb_insert_transfer(xfer); 2854 if (err) 2855 return (err); 2856 2857 /* Pipe isn't running, start first */ 2858 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2859 } 2860 2861 usbd_status 2862 ehci_device_ctrl_start(struct usbd_xfer *xfer) 2863 { 2864 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2865 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2866 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2867 usb_device_request_t *req = &xfer->request; 2868 struct ehci_soft_qtd *setup, *stat, *next; 2869 struct ehci_soft_qh *sqh; 2870 u_int len = UGETW(req->wLength); 2871 usbd_status err; 2872 int s; 2873 2874 KASSERT(xfer->rqflags & URQ_REQUEST); 2875 2876 if (sc->sc_bus.dying) 2877 return (USBD_IOERROR); 2878 2879 setup = ehci_alloc_sqtd(sc); 2880 if (setup == NULL) { 2881 err = USBD_NOMEM; 2882 goto bad1; 2883 } 2884 stat = ehci_alloc_sqtd(sc); 2885 if (stat == NULL) { 2886 err = USBD_NOMEM; 2887 goto bad2; 2888 } 2889 2890 sqh = epipe->sqh; 2891 2892 /* Set up data transaction */ 2893 if (len != 0) { 2894 struct ehci_soft_qtd *end; 2895 2896 err = ehci_alloc_sqtd_chain(sc, len, xfer, &next, &end); 2897 if (err) 2898 goto bad3; 2899 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 2900 end->nextqtd = stat; 2901 end->qtd.qtd_next = 2902 end->qtd.qtd_altnext = htole32(stat->physaddr); 2903 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 2904 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2905 } else { 2906 next = stat; 2907 } 2908 2909 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 2910 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2911 2912 /* Clear toggle */ 2913 setup->qtd.qtd_status = htole32( 2914 EHCI_QTD_ACTIVE | 2915 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 2916 EHCI_QTD_SET_CERR(3) | 2917 EHCI_QTD_SET_TOGGLE(0) | 2918 EHCI_QTD_SET_BYTES(sizeof(*req))); 2919 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 2920 setup->qtd.qtd_buffer_hi[0] = 0; 2921 setup->nextqtd = next; 2922 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 2923 setup->len = sizeof(*req); 2924 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 2925 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2926 2927 stat->qtd.qtd_status = htole32( 2928 EHCI_QTD_ACTIVE | 2929 EHCI_QTD_SET_PID(usbd_xfer_isread(xfer) ? 2930 EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 2931 EHCI_QTD_SET_CERR(3) | 2932 EHCI_QTD_SET_TOGGLE(1) | 2933 EHCI_QTD_IOC); 2934 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 2935 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 2936 stat->nextqtd = NULL; 2937 stat->qtd.qtd_next = stat->qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 2938 stat->len = 0; 2939 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 2940 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2941 2942 ex->sqtdstart = setup; 2943 ex->sqtdend = stat; 2944 #ifdef DIAGNOSTIC 2945 if (!ex->isdone) { 2946 printf("%s: not done, ex=%p\n", __func__, ex); 2947 } 2948 ex->isdone = 0; 2949 #endif 2950 2951 /* Insert qTD in QH list. */ 2952 s = splusb(); 2953 ehci_set_qh_qtd(sqh, setup); 2954 if (xfer->timeout && !sc->sc_bus.use_polling) { 2955 timeout_del(&xfer->timeout_handle); 2956 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 2957 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 2958 } 2959 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 2960 xfer->status = USBD_IN_PROGRESS; 2961 splx(s); 2962 2963 return (USBD_IN_PROGRESS); 2964 2965 bad3: 2966 ehci_free_sqtd(sc, stat); 2967 bad2: 2968 ehci_free_sqtd(sc, setup); 2969 bad1: 2970 xfer->status = err; 2971 usb_transfer_complete(xfer); 2972 return (err); 2973 } 2974 2975 void 2976 ehci_device_ctrl_done(struct usbd_xfer *xfer) 2977 { 2978 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2979 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2980 2981 KASSERT(xfer->rqflags & URQ_REQUEST); 2982 2983 if (xfer->status != USBD_NOMEM) { 2984 ehci_free_sqtd_chain(sc, ex); 2985 } 2986 } 2987 2988 void 2989 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 2990 { 2991 ehci_abort_xfer(xfer, USBD_CANCELLED); 2992 } 2993 2994 void 2995 ehci_device_ctrl_close(struct usbd_pipe *pipe) 2996 { 2997 ehci_close_pipe(pipe); 2998 } 2999 3000 usbd_status 3001 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3002 { 3003 usbd_status err; 3004 3005 /* Insert last in queue. */ 3006 err = usb_insert_transfer(xfer); 3007 if (err) 3008 return (err); 3009 3010 /* Pipe isn't running, start first */ 3011 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3012 } 3013 3014 usbd_status 3015 ehci_device_bulk_start(struct usbd_xfer *xfer) 3016 { 3017 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3018 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3019 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3020 struct ehci_soft_qtd *data, *dataend; 3021 struct ehci_soft_qh *sqh; 3022 usbd_status err; 3023 int s; 3024 3025 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3026 3027 if (sc->sc_bus.dying) 3028 return (USBD_IOERROR); 3029 3030 sqh = epipe->sqh; 3031 3032 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3033 if (err) { 3034 xfer->status = err; 3035 usb_transfer_complete(xfer); 3036 return (err); 3037 } 3038 3039 /* Set up interrupt info. */ 3040 ex->sqtdstart = data; 3041 ex->sqtdend = dataend; 3042 #ifdef DIAGNOSTIC 3043 if (!ex->isdone) { 3044 printf("ehci_device_bulk_start: not done, ex=%p\n", ex); 3045 } 3046 ex->isdone = 0; 3047 #endif 3048 3049 s = splusb(); 3050 ehci_set_qh_qtd(sqh, data); 3051 if (xfer->timeout && !sc->sc_bus.use_polling) { 3052 timeout_del(&xfer->timeout_handle); 3053 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3054 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3055 } 3056 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3057 xfer->status = USBD_IN_PROGRESS; 3058 splx(s); 3059 3060 return (USBD_IN_PROGRESS); 3061 } 3062 3063 void 3064 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3065 { 3066 ehci_abort_xfer(xfer, USBD_CANCELLED); 3067 } 3068 3069 /* 3070 * Close a device bulk pipe. 3071 */ 3072 void 3073 ehci_device_bulk_close(struct usbd_pipe *pipe) 3074 { 3075 ehci_close_pipe(pipe); 3076 } 3077 3078 void 3079 ehci_device_bulk_done(struct usbd_xfer *xfer) 3080 { 3081 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3082 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3083 3084 if (xfer->status != USBD_NOMEM) { 3085 ehci_free_sqtd_chain(sc, ex); 3086 } 3087 } 3088 3089 usbd_status 3090 ehci_device_setintr(struct ehci_softc *sc, struct ehci_soft_qh *sqh, int ival) 3091 { 3092 struct ehci_soft_islot *isp; 3093 int islot, lev; 3094 3095 /* Find a poll rate that is large enough. */ 3096 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3097 if (EHCI_ILEV_IVAL(lev) <= ival) 3098 break; 3099 3100 /* Pick an interrupt slot at the right level. */ 3101 /* XXX could do better than picking at random */ 3102 islot = EHCI_IQHIDX(lev, arc4random()); 3103 3104 sqh->islot = islot; 3105 isp = &sc->sc_islots[islot]; 3106 ehci_add_qh(sqh, isp->sqh); 3107 3108 return (USBD_NORMAL_COMPLETION); 3109 } 3110 3111 usbd_status 3112 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3113 { 3114 usbd_status err; 3115 3116 /* Insert last in queue. */ 3117 err = usb_insert_transfer(xfer); 3118 if (err) 3119 return (err); 3120 3121 /* 3122 * Pipe isn't running (otherwise err would be USBD_INPROG), 3123 * so start it first. 3124 */ 3125 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3126 } 3127 3128 usbd_status 3129 ehci_device_intr_start(struct usbd_xfer *xfer) 3130 { 3131 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3132 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3133 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3134 struct ehci_soft_qtd *data, *dataend; 3135 struct ehci_soft_qh *sqh; 3136 usbd_status err; 3137 int s; 3138 3139 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3140 3141 if (sc->sc_bus.dying) 3142 return (USBD_IOERROR); 3143 3144 sqh = epipe->sqh; 3145 3146 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3147 if (err) { 3148 xfer->status = err; 3149 usb_transfer_complete(xfer); 3150 return (err); 3151 } 3152 3153 /* Set up interrupt info. */ 3154 ex->sqtdstart = data; 3155 ex->sqtdend = dataend; 3156 #ifdef DIAGNOSTIC 3157 if (!ex->isdone) 3158 printf("ehci_device_intr_start: not done, ex=%p\n", ex); 3159 ex->isdone = 0; 3160 #endif 3161 3162 s = splusb(); 3163 ehci_set_qh_qtd(sqh, data); 3164 if (xfer->timeout && !sc->sc_bus.use_polling) { 3165 timeout_del(&xfer->timeout_handle); 3166 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3167 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3168 } 3169 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3170 xfer->status = USBD_IN_PROGRESS; 3171 splx(s); 3172 3173 return (USBD_IN_PROGRESS); 3174 } 3175 3176 void 3177 ehci_device_intr_abort(struct usbd_xfer *xfer) 3178 { 3179 KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer); 3180 3181 /* 3182 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3183 * async doorbell. That's dependant on the async list, whereas 3184 * intr xfers are periodic, should not use this? 3185 */ 3186 ehci_abort_xfer(xfer, USBD_CANCELLED); 3187 } 3188 3189 void 3190 ehci_device_intr_close(struct usbd_pipe *pipe) 3191 { 3192 ehci_close_pipe(pipe); 3193 } 3194 3195 void 3196 ehci_device_intr_done(struct usbd_xfer *xfer) 3197 { 3198 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3199 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3200 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3201 struct ehci_soft_qtd *data, *dataend; 3202 struct ehci_soft_qh *sqh; 3203 usbd_status err; 3204 int s; 3205 3206 if (xfer->pipe->repeat) { 3207 ehci_free_sqtd_chain(sc, ex); 3208 3209 sqh = epipe->sqh; 3210 3211 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3212 if (err) { 3213 xfer->status = err; 3214 return; 3215 } 3216 3217 /* Set up interrupt info. */ 3218 ex->sqtdstart = data; 3219 ex->sqtdend = dataend; 3220 #ifdef DIAGNOSTIC 3221 if (!ex->isdone) { 3222 printf("ehci_device_intr_done: not done, ex=%p\n", 3223 ex); 3224 } 3225 ex->isdone = 0; 3226 #endif 3227 3228 s = splusb(); 3229 ehci_set_qh_qtd(sqh, data); 3230 if (xfer->timeout && !sc->sc_bus.use_polling) { 3231 timeout_del(&xfer->timeout_handle); 3232 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3233 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3234 } 3235 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3236 xfer->status = USBD_IN_PROGRESS; 3237 splx(s); 3238 } else if (xfer->status != USBD_NOMEM) { 3239 ehci_free_sqtd_chain(sc, ex); 3240 } 3241 } 3242 3243 usbd_status 3244 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 3245 { 3246 usbd_status err; 3247 3248 err = usb_insert_transfer(xfer); 3249 if (err && err != USBD_IN_PROGRESS) 3250 return (err); 3251 3252 return (ehci_device_isoc_start(xfer)); 3253 } 3254 3255 usbd_status 3256 ehci_device_isoc_start(struct usbd_xfer *xfer) 3257 { 3258 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3259 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3260 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3261 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3262 uint8_t ival = ed->bInterval; 3263 struct ehci_soft_itd *itd; 3264 int s, frindex; 3265 uint32_t link; 3266 3267 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3268 KASSERT(ival > 0 && ival <= 16); 3269 3270 /* 3271 * To allow continuous transfers, above we start all transfers 3272 * immediately. However, we're still going to get usbd_start_next call 3273 * this when another xfer completes. So, check if this is already 3274 * in progress or not 3275 */ 3276 if (ex->itdstart != NULL) 3277 return (USBD_IN_PROGRESS); 3278 3279 if (sc->sc_bus.dying) 3280 return (USBD_IOERROR); 3281 3282 /* Why would you do that anyway? */ 3283 if (sc->sc_bus.use_polling) 3284 return (USBD_INVAL); 3285 3286 /* 3287 * To avoid complication, don't allow a request right now that'll span 3288 * the entire frame table. To within 4 frames, to allow some leeway 3289 * on either side of where the hc currently is. 3290 */ 3291 if ((1 << (ival - 1)) * xfer->nframes >= (sc->sc_flsize - 4) * 8) 3292 return (USBD_INVAL); 3293 3294 /* 3295 * Step 1: Allocate and initialize itds. 3296 */ 3297 if (xfer->device->speed == USB_SPEED_HIGH) { 3298 if (ehci_alloc_itd_chain(sc, xfer)) 3299 return (USBD_INVAL); 3300 3301 link = EHCI_LINK_ITD; 3302 } else { 3303 if (ehci_alloc_sitd_chain(sc, xfer)) 3304 return (USBD_INVAL); 3305 3306 link = EHCI_LINK_SITD; 3307 } 3308 3309 #ifdef DIAGNOSTIC 3310 if (!ex->isdone) { 3311 printf("%s: not done, ex=%p\n", __func__, ex); 3312 } 3313 ex->isdone = 0; 3314 #endif 3315 3316 /* 3317 * Part 2: Transfer descriptors have now been set up, now they must 3318 * be scheduled into the period frame list. Erk. Not wanting to 3319 * complicate matters, transfer is denied if the transfer spans 3320 * more than the period frame list. 3321 */ 3322 s = splusb(); 3323 3324 /* Start inserting frames */ 3325 if (epipe->u.isoc.cur_xfers > 0) { 3326 frindex = epipe->u.isoc.next_frame; 3327 } else { 3328 frindex = EOREAD4(sc, EHCI_FRINDEX); 3329 frindex = frindex >> 3; /* Erase microframe index */ 3330 frindex += 2; 3331 } 3332 3333 if (frindex >= sc->sc_flsize) 3334 frindex &= (sc->sc_flsize - 1); 3335 3336 /* What's the frame interval? */ 3337 ival = (1 << (ival - 1)); 3338 if (ival / 8 == 0) 3339 ival = 1; 3340 else 3341 ival /= 8; 3342 3343 /* Abuse the fact that itd_next == sitd_next. */ 3344 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 3345 itd->itd.itd_next = sc->sc_flist[frindex]; 3346 if (itd->itd.itd_next == 0) 3347 itd->itd.itd_next = htole32(EHCI_LINK_TERMINATE); 3348 3349 sc->sc_flist[frindex] = htole32(link | itd->physaddr); 3350 itd->u.frame_list.next = sc->sc_softitds[frindex]; 3351 sc->sc_softitds[frindex] = itd; 3352 if (itd->u.frame_list.next != NULL) 3353 itd->u.frame_list.next->u.frame_list.prev = itd; 3354 itd->slot = frindex; 3355 itd->u.frame_list.prev = NULL; 3356 3357 frindex += ival; 3358 if (frindex >= sc->sc_flsize) 3359 frindex -= sc->sc_flsize; 3360 } 3361 3362 epipe->u.isoc.cur_xfers++; 3363 epipe->u.isoc.next_frame = frindex; 3364 3365 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3366 xfer->status = USBD_IN_PROGRESS; 3367 xfer->done = 0; 3368 splx(s); 3369 3370 return (USBD_IN_PROGRESS); 3371 } 3372 3373 int 3374 ehci_alloc_itd_chain(struct ehci_softc *sc, struct usbd_xfer *xfer) 3375 { 3376 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3377 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3378 const uint32_t mps = UGETW(ed->wMaxPacketSize); 3379 struct ehci_soft_itd *itd = NULL, *pitd = NULL; 3380 int i, j, nframes, uframes, ufrperframe; 3381 int offs = 0, trans_count = 0; 3382 3383 /* 3384 * How many itds do we need? One per transfer if interval >= 8 3385 * microframes, fewer if we use multiple microframes per frame. 3386 */ 3387 switch (ed->bInterval) { 3388 case 1: 3389 ufrperframe = 8; 3390 break; 3391 case 2: 3392 ufrperframe = 4; 3393 break; 3394 case 3: 3395 ufrperframe = 2; 3396 break; 3397 default: 3398 ufrperframe = 1; 3399 break; 3400 } 3401 nframes = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3402 uframes = 8 / ufrperframe; 3403 if (nframes == 0) 3404 return (1); 3405 3406 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3407 usbd_xfer_isread(xfer) ? 3408 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3409 for (i = 0; i < nframes; i++) { 3410 uint32_t froffs = offs; 3411 3412 itd = ehci_alloc_itd(sc); 3413 if (itd == NULL) { 3414 ehci_free_itd_chain(sc, ex); 3415 return (1); 3416 } 3417 3418 if (pitd != NULL) 3419 pitd->xfer_next = itd; 3420 else 3421 ex->itdstart = itd; 3422 3423 /* 3424 * Step 1.5, initialize uframes 3425 */ 3426 for (j = 0; j < 8; j += uframes) { 3427 /* Calculate which page in the list this starts in */ 3428 int addr = DMAADDR(&xfer->dmabuf, froffs); 3429 addr = EHCI_PAGE_OFFSET(addr) + (offs - froffs); 3430 addr = EHCI_PAGE(addr) / EHCI_PAGE_SIZE; 3431 3432 /* This gets the initial offset into the first page, 3433 * looks how far further along the current uframe 3434 * offset is. Works out how many pages that is. 3435 */ 3436 itd->itd.itd_ctl[j] = htole32( 3437 EHCI_ITD_ACTIVE | 3438 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3439 EHCI_ITD_SET_PG(addr) | 3440 EHCI_ITD_SET_OFFS(DMAADDR(&xfer->dmabuf, offs)) 3441 ); 3442 3443 offs += xfer->frlengths[trans_count]; 3444 trans_count++; 3445 3446 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3447 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3448 break; 3449 } 3450 } 3451 3452 /* Step 1.75, set buffer pointers. To simplify matters, all 3453 * pointers are filled out for the next 7 hardware pages in 3454 * the dma block, so no need to worry what pages to cover 3455 * and what to not. 3456 */ 3457 3458 for (j = 0; j < 7; j++) { 3459 /* 3460 * Don't try to lookup a page that's past the end 3461 * of buffer 3462 */ 3463 int page_offs = EHCI_PAGE(froffs + 3464 (EHCI_PAGE_SIZE * j)); 3465 3466 if (page_offs >= xfer->dmabuf.block->size) 3467 break; 3468 3469 long long page = DMAADDR(&xfer->dmabuf, page_offs); 3470 page = EHCI_PAGE(page); 3471 itd->itd.itd_bufr[j] = htole32(page); 3472 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 3473 } 3474 3475 /* 3476 * Other special values 3477 */ 3478 itd->itd.itd_bufr[0] |= htole32( 3479 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 3480 EHCI_ITD_SET_DADDR(xfer->pipe->device->address) 3481 ); 3482 3483 itd->itd.itd_bufr[1] |= htole32( 3484 (usbd_xfer_isread(xfer) ? EHCI_ITD_SET_DIR(1) : 0) | 3485 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(mps)) 3486 ); 3487 /* FIXME: handle invalid trans */ 3488 itd->itd.itd_bufr[2] |= htole32( 3489 EHCI_ITD_SET_MULTI(UE_GET_TRANS(mps)+1) 3490 ); 3491 3492 pitd = itd; 3493 } 3494 3495 ex->itdend = itd; 3496 3497 return (0); 3498 } 3499 3500 int 3501 ehci_alloc_sitd_chain(struct ehci_softc *sc, struct usbd_xfer *xfer) 3502 { 3503 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3504 struct usbd_device *hshub = xfer->device->myhsport->parent; 3505 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3506 struct ehci_soft_itd *itd = NULL, *pitd = NULL; 3507 uint8_t smask, cmask, tp, uf; 3508 int i, nframes, offs = 0; 3509 uint32_t endp; 3510 3511 nframes = xfer->nframes; 3512 if (nframes == 0) 3513 return (1); 3514 3515 endp = EHCI_SITD_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 3516 EHCI_SITD_SET_ADDR(xfer->device->address) | 3517 EHCI_SITD_SET_PORT(xfer->device->myhsport->portno) | 3518 EHCI_SITD_SET_HUBA(hshub->address); 3519 3520 if (usbd_xfer_isread(xfer)) 3521 endp |= EHCI_SITD_SET_DIR(1); 3522 3523 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3524 usbd_xfer_isread(xfer) ? 3525 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3526 for (i = 0; i < nframes; i++) { 3527 uint32_t addr = DMAADDR(&xfer->dmabuf, offs); 3528 uint32_t page = EHCI_PAGE(addr + xfer->frlengths[i] - 1); 3529 3530 itd = ehci_alloc_itd(sc); 3531 if (itd == NULL) { 3532 ehci_free_itd_chain(sc, ex); 3533 return (1); 3534 } 3535 if (pitd) 3536 pitd->xfer_next = itd; 3537 else 3538 ex->itdstart = itd; 3539 3540 itd->sitd.sitd_endp = htole32(endp); 3541 itd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 3542 itd->sitd.sitd_trans = htole32( 3543 EHCI_SITD_ACTIVE | 3544 EHCI_SITD_SET_LEN(xfer->frlengths[i]) | 3545 ((i == nframes - 1) ? EHCI_SITD_IOC : 0) 3546 ); 3547 3548 uf = max(1, ((xfer->frlengths[i] + 187) / 188)); 3549 3550 /* 3551 * Since we do not yet budget and schedule micro-frames 3552 * we assume there is no other transfer using the same 3553 * TT. 3554 */ 3555 if (usbd_xfer_isread(xfer)) { 3556 smask = 0x01; 3557 cmask = ((1 << (uf + 2)) - 1) << 2; 3558 } else { 3559 /* Is the payload is greater than 188 bytes? */ 3560 if (uf == 1) 3561 tp = EHCI_SITD_TP_ALL; 3562 else 3563 tp = EHCI_SITD_TP_BEGIN; 3564 3565 page |= EHCI_SITD_SET_TCOUNT(uf) | EHCI_SITD_SET_TP(tp); 3566 smask = (1 << uf) - 1; 3567 cmask = 0x00; 3568 } 3569 3570 itd->sitd.sitd_sched = htole32( 3571 EHCI_SITD_SET_SMASK(smask) | EHCI_SITD_SET_CMASK(cmask) 3572 ); 3573 itd->sitd.sitd_bufr[0] = htole32(addr); 3574 itd->sitd.sitd_bufr[1] = htole32(page); 3575 3576 offs += xfer->frlengths[i]; 3577 pitd = itd; 3578 } 3579 3580 ex->itdend = itd; 3581 3582 return (0); 3583 } 3584 3585 void 3586 ehci_device_isoc_abort(struct usbd_xfer *xfer) 3587 { 3588 int s; 3589 3590 s = splusb(); 3591 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 3592 splx(s); 3593 } 3594 3595 void 3596 ehci_device_isoc_close(struct usbd_pipe *pipe) 3597 { 3598 } 3599 3600 void 3601 ehci_device_isoc_done(struct usbd_xfer *xfer) 3602 { 3603 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3604 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3605 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3606 int s; 3607 3608 s = splusb(); 3609 epipe->u.isoc.cur_xfers--; 3610 if (xfer->status != USBD_NOMEM) { 3611 ehci_rem_itd_chain(sc, ex); 3612 ehci_free_itd_chain(sc, ex); 3613 } 3614 splx(s); 3615 } 3616