1 /* $NetBSD: dsc.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 #ifndef __DAL_DSC_H__ 28 #define __DAL_DSC_H__ 29 30 #include "dc_dsc.h" 31 #include "dc_hw_types.h" 32 #include "dc_types.h" 33 /* do not include any other headers 34 * or else it might break Edid Utility functionality. 35 */ 36 37 38 /* Input parameters for configuring DSC from the outside of DSC */ 39 struct dsc_config { 40 uint32_t pic_width; 41 uint32_t pic_height; 42 enum dc_pixel_encoding pixel_encoding; 43 enum dc_color_depth color_depth; /* Bits per component */ 44 struct dc_dsc_config dc_dsc_cfg; 45 }; 46 47 48 /* Output parameters for configuring DSC-related part of OPTC */ 49 struct dsc_optc_config { 50 uint32_t slice_width; /* Slice width in pixels */ 51 uint32_t bytes_per_pixel; /* Bytes per pixel in u3.28 format */ 52 bool is_pixel_format_444; /* 'true' if pixel format is 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4)' */ 53 }; 54 55 56 struct dcn_dsc_state { 57 uint32_t dsc_clock_en; 58 uint32_t dsc_slice_width; 59 uint32_t dsc_bytes_per_pixel; 60 }; 61 62 63 /* DSC encoder capabilities 64 * They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps. 65 */ 66 union dsc_enc_slice_caps { 67 struct { 68 uint8_t NUM_SLICES_1 : 1; 69 uint8_t NUM_SLICES_2 : 1; 70 uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */ 71 uint8_t NUM_SLICES_4 : 1; 72 uint8_t NUM_SLICES_8 : 1; 73 } bits; 74 uint8_t raw; 75 }; 76 77 struct dsc_enc_caps { 78 uint8_t dsc_version; 79 union dsc_enc_slice_caps slice_caps; 80 int32_t lb_bit_depth; 81 bool is_block_pred_supported; 82 union dsc_color_formats color_formats; 83 union dsc_color_depth color_depth; 84 int32_t max_total_throughput_mps; /* Maximum total throughput with all the slices combined */ 85 int32_t max_slice_width; 86 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 87 }; 88 89 struct dsc_funcs { 90 void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); 91 void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 92 bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 93 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 94 struct dsc_optc_config *dsc_optc_cfg); 95 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 96 uint8_t *dsc_packed_pps); 97 void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe); 98 void (*dsc_disable)(struct display_stream_compressor *dsc); 99 }; 100 101 #endif 102