1 /* $NetBSD: amdgpu_dcn20_dpp.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn20_dpp.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $");
30
31 #include "dm_services.h"
32
33 #include "core_types.h"
34
35 #include "reg_helper.h"
36 #include "dcn20_dpp.h"
37 #include "basics/conversion.h"
38
39 #define NUM_PHASES 64
40 #define HORZ_MAX_TAPS 8
41 #define VERT_MAX_TAPS 8
42
43 #define BLACK_OFFSET_RGB_Y 0x0
44 #define BLACK_OFFSET_CBCR 0x8000
45
46 #define REG(reg)\
47 dpp->tf_regs->reg
48
49 #define CTX \
50 dpp->base.ctx
51
52 #undef FN
53 #define FN(reg_name, field_name) \
54 dpp->tf_shift->field_name, dpp->tf_mask->field_name
55
dpp20_read_state(struct dpp * dpp_base,struct dcn_dpp_state * s)56 void dpp20_read_state(struct dpp *dpp_base,
57 struct dcn_dpp_state *s)
58 {
59 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
60
61 REG_GET(DPP_CONTROL,
62 DPP_CLOCK_ENABLE, &s->is_enabled);
63 REG_GET(CM_DGAM_CONTROL,
64 CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
65 // BGAM has no ROM, and definition is different, can't reuse same dump
66 //REG_GET(CM_BLNDGAM_CONTROL,
67 // CM_BLNDGAM_LUT_MODE, &s->rgam_lut_mode);
68 REG_GET(CM_GAMUT_REMAP_CONTROL,
69 CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
70 if (s->gamut_remap_mode) {
71 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
72 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
73 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
74 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
75 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
76 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
77 }
78 }
79
dpp2_power_on_obuf(struct dpp * dpp_base,bool power_on)80 void dpp2_power_on_obuf(
81 struct dpp *dpp_base,
82 bool power_on)
83 {
84 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
85
86 REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);
87
88 REG_UPDATE(OBUF_MEM_PWR_CTRL,
89 OBUF_MEM_PWR_FORCE, power_on == true ? 0:1);
90
91 REG_UPDATE(DSCL_MEM_PWR_CTRL,
92 LUT_MEM_PWR_FORCE, power_on == true ? 0:1);
93 }
94
dpp2_dummy_program_input_lut(struct dpp * dpp_base,const struct dc_gamma * gamma)95 void dpp2_dummy_program_input_lut(
96 struct dpp *dpp_base,
97 const struct dc_gamma *gamma)
98 {}
99
dpp2_cnv_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut)100 static void dpp2_cnv_setup (
101 struct dpp *dpp_base,
102 enum surface_pixel_format format,
103 enum expansion_mode mode,
104 struct dc_csc_transform input_csc_color_matrix,
105 enum dc_color_space input_color_space,
106 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
107 {
108 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
109 uint32_t pixel_format = 0;
110 uint32_t alpha_en = 1;
111 enum dc_color_space color_space = COLOR_SPACE_SRGB;
112 enum dcn20_input_csc_select select = DCN2_ICSC_SELECT_BYPASS;
113 bool force_disable_cursor = false;
114 struct out_csc_color_matrix tbl_entry;
115 uint32_t is_2bit = 0;
116 int i = 0;
117
118 REG_SET_2(FORMAT_CONTROL, 0,
119 CNVC_BYPASS, 0,
120 FORMAT_EXPANSION_MODE, mode);
121
122 //hardcode default
123 //FORMAT_CONTROL. FORMAT_CNV16 default 0: U0.16/S.1.15; 1: U1.15/ S.1.14
124 //FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN default 0: disabled 1: enabled
125 //FORMAT_CONTROL. CLAMP_POSITIVE default 0: disabled 1: enabled
126 //FORMAT_CONTROL. CLAMP_POSITIVE_C default 0: disabled 1: enabled
127 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
128 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
129 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
130 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
131
132 switch (format) {
133 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
134 pixel_format = 1;
135 break;
136 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
137 pixel_format = 3;
138 alpha_en = 0;
139 break;
140 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
141 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
142 pixel_format = 8;
143 break;
144 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
145 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
146 pixel_format = 10;
147 is_2bit = 1;
148 break;
149 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
150 force_disable_cursor = false;
151 pixel_format = 65;
152 color_space = COLOR_SPACE_YCBCR709;
153 select = DCN2_ICSC_SELECT_ICSC_A;
154 break;
155 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
156 force_disable_cursor = true;
157 pixel_format = 64;
158 color_space = COLOR_SPACE_YCBCR709;
159 select = DCN2_ICSC_SELECT_ICSC_A;
160 break;
161 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
162 force_disable_cursor = true;
163 pixel_format = 67;
164 color_space = COLOR_SPACE_YCBCR709;
165 select = DCN2_ICSC_SELECT_ICSC_A;
166 break;
167 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
168 force_disable_cursor = true;
169 pixel_format = 66;
170 color_space = COLOR_SPACE_YCBCR709;
171 select = DCN2_ICSC_SELECT_ICSC_A;
172 break;
173 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
174 pixel_format = 22;
175 break;
176 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
177 pixel_format = 24;
178 break;
179 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
180 pixel_format = 25;
181 break;
182 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
183 pixel_format = 12;
184 color_space = COLOR_SPACE_YCBCR709;
185 select = DCN2_ICSC_SELECT_ICSC_A;
186 break;
187 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
188 pixel_format = 112;
189 break;
190 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
191 pixel_format = 113;
192 break;
193 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
194 pixel_format = 114;
195 color_space = COLOR_SPACE_YCBCR709;
196 select = DCN2_ICSC_SELECT_ICSC_A;
197 is_2bit = 1;
198 break;
199 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
200 pixel_format = 115;
201 color_space = COLOR_SPACE_YCBCR709;
202 select = DCN2_ICSC_SELECT_ICSC_A;
203 is_2bit = 1;
204 break;
205 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
206 pixel_format = 118;
207 break;
208 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
209 pixel_format = 119;
210 break;
211 default:
212 break;
213 }
214
215 if (is_2bit == 1 && alpha_2bit_lut != NULL) {
216 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
217 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
218 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
219 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
220 }
221
222 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
223 CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
224 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
225
226 // if input adjustments exist, program icsc with those values
227 if (input_csc_color_matrix.enable_adjustment
228 == true) {
229 for (i = 0; i < 12; i++)
230 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
231
232 tbl_entry.color_space = input_color_space;
233
234 if (color_space >= COLOR_SPACE_YCBCR601)
235 select = DCN2_ICSC_SELECT_ICSC_A;
236 else
237 select = DCN2_ICSC_SELECT_BYPASS;
238
239 dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry);
240 } else
241 dpp2_program_input_csc(dpp_base, color_space, select, NULL);
242
243 if (force_disable_cursor) {
244 REG_UPDATE(CURSOR_CONTROL,
245 CURSOR_ENABLE, 0);
246 REG_UPDATE(CURSOR0_CONTROL,
247 CUR0_ENABLE, 0);
248
249 }
250 dpp2_power_on_obuf(dpp_base, true);
251
252 }
253
dpp2_cnv_set_bias_scale(struct dpp * dpp_base,struct dc_bias_and_scale * bias_and_scale)254 void dpp2_cnv_set_bias_scale(
255 struct dpp *dpp_base,
256 struct dc_bias_and_scale *bias_and_scale)
257 {
258 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
259
260 REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red);
261 REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green);
262 REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue);
263 REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red);
264 REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green);
265 REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue);
266 }
267
268 /*compute the maximum number of lines that we can fit in the line buffer*/
dscl2_calc_lb_num_partitions(const struct scaler_data * scl_data,enum lb_memory_config lb_config,int * num_part_y,int * num_part_c)269 void dscl2_calc_lb_num_partitions(
270 const struct scaler_data *scl_data,
271 enum lb_memory_config lb_config,
272 int *num_part_y,
273 int *num_part_c)
274 {
275 int memory_line_size_y, memory_line_size_c, memory_line_size_a,
276 lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
277
278 int line_size = scl_data->viewport.width < scl_data->recout.width ?
279 scl_data->viewport.width : scl_data->recout.width;
280 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
281 scl_data->viewport_c.width : scl_data->recout.width;
282
283 if (line_size == 0)
284 line_size = 1;
285
286 if (line_size_c == 0)
287 line_size_c = 1;
288
289 memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
290 memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
291 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
292
293 if (lb_config == LB_MEMORY_CONFIG_1) {
294 lb_memory_size = 970;
295 lb_memory_size_c = 970;
296 lb_memory_size_a = 970;
297 } else if (lb_config == LB_MEMORY_CONFIG_2) {
298 lb_memory_size = 1290;
299 lb_memory_size_c = 1290;
300 lb_memory_size_a = 1290;
301 } else if (lb_config == LB_MEMORY_CONFIG_3) {
302 /* 420 mode: using 3rd mem from Y, Cr and Cb */
303 lb_memory_size = 970 + 1290 + 484 + 484 + 484;
304 lb_memory_size_c = 970 + 1290;
305 lb_memory_size_a = 970 + 1290 + 484;
306 } else {
307 lb_memory_size = 970 + 1290 + 484;
308 lb_memory_size_c = 970 + 1290 + 484;
309 lb_memory_size_a = 970 + 1290 + 484;
310 }
311 *num_part_y = lb_memory_size / memory_line_size_y;
312 *num_part_c = lb_memory_size_c / memory_line_size_c;
313 num_partitions_a = lb_memory_size_a / memory_line_size_a;
314
315 if (scl_data->lb_params.alpha_en
316 && (num_partitions_a < *num_part_y))
317 *num_part_y = num_partitions_a;
318
319 if (*num_part_y > 64)
320 *num_part_y = 64;
321 if (*num_part_c > 64)
322 *num_part_c = 64;
323 }
324
dpp2_cnv_set_alpha_keyer(struct dpp * dpp_base,struct cnv_color_keyer_params * color_keyer)325 void dpp2_cnv_set_alpha_keyer(
326 struct dpp *dpp_base,
327 struct cnv_color_keyer_params *color_keyer)
328 {
329 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
330
331 REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_EN, color_keyer->color_keyer_en);
332
333 REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, color_keyer->color_keyer_mode);
334
335 REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, color_keyer->color_keyer_alpha_low);
336 REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, color_keyer->color_keyer_alpha_high);
337
338 REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low);
339 REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high);
340
341 REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, color_keyer->color_keyer_green_low);
342 REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, color_keyer->color_keyer_green_high);
343
344 REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low);
345 REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high);
346 }
347
dpp2_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes)348 void dpp2_set_cursor_attributes(
349 struct dpp *dpp_base,
350 struct dc_cursor_attributes *cursor_attributes)
351 {
352 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
353 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
354 int cur_rom_en = 0;
355
356 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
357 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
358 if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
359 cur_rom_en = 1;
360 }
361 }
362
363 REG_UPDATE_3(CURSOR0_CONTROL,
364 CUR0_MODE, color_format,
365 CUR0_EXPANSION_MODE, 0,
366 CUR0_ROM_EN, cur_rom_en);
367
368 if (color_format == CURSOR_MODE_MONO) {
369 /* todo: clarify what to program these to */
370 REG_UPDATE(CURSOR0_COLOR0,
371 CUR0_COLOR0, 0x00000000);
372 REG_UPDATE(CURSOR0_COLOR1,
373 CUR0_COLOR1, 0xFFFFFFFF);
374 }
375 }
376
377 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
378
dpp2_get_optimal_number_of_taps(struct dpp * dpp,struct scaler_data * scl_data,const struct scaling_taps * in_taps)379 bool dpp2_get_optimal_number_of_taps(
380 struct dpp *dpp,
381 struct scaler_data *scl_data,
382 const struct scaling_taps *in_taps)
383 {
384 /* Some ASICs does not support FP16 scaling, so we reject modes require this*/
385 if (scl_data->viewport.width != scl_data->h_active &&
386 scl_data->viewport.height != scl_data->v_active &&
387 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
388 scl_data->format == PIXEL_FORMAT_FP16)
389 return false;
390
391 if (scl_data->viewport.width > scl_data->h_active &&
392 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
393 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
394 return false;
395
396 /* TODO: add lb check */
397
398 /* No support for programming ratio of 8, drop to 7.99999.. */
399 if (scl_data->ratios.horz.value == (8ll << 32))
400 scl_data->ratios.horz.value--;
401 if (scl_data->ratios.vert.value == (8ll << 32))
402 scl_data->ratios.vert.value--;
403 if (scl_data->ratios.horz_c.value == (8ll << 32))
404 scl_data->ratios.horz_c.value--;
405 if (scl_data->ratios.vert_c.value == (8ll << 32))
406 scl_data->ratios.vert_c.value--;
407
408 /* Set default taps if none are provided */
409 if (in_taps->h_taps == 0) {
410 if (dc_fixpt_ceil(scl_data->ratios.horz) > 4)
411 scl_data->taps.h_taps = 8;
412 else
413 scl_data->taps.h_taps = 4;
414 } else
415 scl_data->taps.h_taps = in_taps->h_taps;
416 if (in_taps->v_taps == 0) {
417 if (dc_fixpt_ceil(scl_data->ratios.vert) > 4)
418 scl_data->taps.v_taps = 8;
419 else
420 scl_data->taps.v_taps = 4;
421 } else
422 scl_data->taps.v_taps = in_taps->v_taps;
423 if (in_taps->v_taps_c == 0) {
424 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 4)
425 scl_data->taps.v_taps_c = 4;
426 else
427 scl_data->taps.v_taps_c = 2;
428 } else
429 scl_data->taps.v_taps_c = in_taps->v_taps_c;
430 if (in_taps->h_taps_c == 0) {
431 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 4)
432 scl_data->taps.h_taps_c = 4;
433 else
434 scl_data->taps.h_taps_c = 2;
435 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
436 /* Only 1 and even h_taps_c are supported by hw */
437 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
438 else
439 scl_data->taps.h_taps_c = in_taps->h_taps_c;
440
441 if (!dpp->ctx->dc->debug.always_scale) {
442 if (IDENTITY_RATIO(scl_data->ratios.horz))
443 scl_data->taps.h_taps = 1;
444 if (IDENTITY_RATIO(scl_data->ratios.vert))
445 scl_data->taps.v_taps = 1;
446 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
447 scl_data->taps.h_taps_c = 1;
448 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
449 scl_data->taps.v_taps_c = 1;
450 }
451
452 return true;
453 }
454
oppn20_dummy_program_regamma_pwl(struct dpp * dpp,const struct pwl_params * params,enum opp_regamma mode)455 void oppn20_dummy_program_regamma_pwl(
456 struct dpp *dpp,
457 const struct pwl_params *params,
458 enum opp_regamma mode)
459 {}
460
461 static struct dpp_funcs dcn20_dpp_funcs = {
462 .dpp_read_state = dpp20_read_state,
463 .dpp_reset = dpp_reset,
464 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
465 .dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps,
466 .dpp_set_gamut_remap = dpp2_cm_set_gamut_remap,
467 .dpp_set_csc_adjustment = NULL,
468 .dpp_set_csc_default = NULL,
469 .dpp_program_regamma_pwl = oppn20_dummy_program_regamma_pwl,
470 .dpp_set_degamma = dpp2_set_degamma,
471 .dpp_program_input_lut = dpp2_dummy_program_input_lut,
472 .dpp_full_bypass = dpp1_full_bypass,
473 .dpp_setup = dpp2_cnv_setup,
474 .dpp_program_degamma_pwl = dpp2_set_degamma_pwl,
475 .dpp_program_blnd_lut = dpp20_program_blnd_lut,
476 .dpp_program_shaper_lut = dpp20_program_shaper,
477 .dpp_program_3dlut = dpp20_program_3dlut,
478 .dpp_program_bias_and_scale = NULL,
479 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
480 .set_cursor_attributes = dpp2_set_cursor_attributes,
481 .set_cursor_position = dpp1_set_cursor_position,
482 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
483 .dpp_dppclk_control = dpp1_dppclk_control,
484 .dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier,
485 };
486
487 static struct dpp_caps dcn20_dpp_cap = {
488 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
489 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
490 };
491
dpp2_construct(struct dcn20_dpp * dpp,struct dc_context * ctx,uint32_t inst,const struct dcn2_dpp_registers * tf_regs,const struct dcn2_dpp_shift * tf_shift,const struct dcn2_dpp_mask * tf_mask)492 bool dpp2_construct(
493 struct dcn20_dpp *dpp,
494 struct dc_context *ctx,
495 uint32_t inst,
496 const struct dcn2_dpp_registers *tf_regs,
497 const struct dcn2_dpp_shift *tf_shift,
498 const struct dcn2_dpp_mask *tf_mask)
499 {
500 dpp->base.ctx = ctx;
501
502 dpp->base.inst = inst;
503 dpp->base.funcs = &dcn20_dpp_funcs;
504 dpp->base.caps = &dcn20_dpp_cap;
505
506 dpp->tf_regs = tf_regs;
507 dpp->tf_shift = tf_shift;
508 dpp->tf_mask = tf_mask;
509
510 dpp->lb_pixel_depth_supported =
511 LB_PIXEL_DEPTH_18BPP |
512 LB_PIXEL_DEPTH_24BPP |
513 LB_PIXEL_DEPTH_30BPP;
514
515 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
516 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
517
518 return true;
519 }
520
521