1 /* $NetBSD: kfd_device_queue_manager_v10.c,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: kfd_device_queue_manager_v10.c,v 1.2 2021/12/18 23:44:59 riastradh Exp $");
28
29 #include "kfd_device_queue_manager.h"
30 #include "navi10_enum.h"
31 #include "gc/gc_10_1_0_offset.h"
32 #include "gc/gc_10_1_0_sh_mask.h"
33
34 static int update_qpd_v10(struct device_queue_manager *dqm,
35 struct qcm_process_device *qpd);
36 static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
37 struct qcm_process_device *qpd);
38
device_queue_manager_init_v10_navi10(struct device_queue_manager_asic_ops * asic_ops)39 void device_queue_manager_init_v10_navi10(
40 struct device_queue_manager_asic_ops *asic_ops)
41 {
42 asic_ops->update_qpd = update_qpd_v10;
43 asic_ops->init_sdma_vm = init_sdma_vm_v10;
44 asic_ops->mqd_manager_init = mqd_manager_init_v10;
45 }
46
compute_sh_mem_bases_64bit(struct kfd_process_device * pdd)47 static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
48 {
49 uint32_t shared_base = pdd->lds_base >> 48;
50 uint32_t private_base = pdd->scratch_base >> 48;
51
52 return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
53 private_base;
54 }
55
update_qpd_v10(struct device_queue_manager * dqm,struct qcm_process_device * qpd)56 static int update_qpd_v10(struct device_queue_manager *dqm,
57 struct qcm_process_device *qpd)
58 {
59 struct kfd_process_device *pdd;
60
61 pdd = qpd_to_pdd(qpd);
62
63 /* check if sh_mem_config register already configured */
64 if (qpd->sh_mem_config == 0) {
65 qpd->sh_mem_config =
66 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
67 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
68 #if 0
69 /* TODO:
70 * This shouldn't be an issue with Navi10. Verify.
71 */
72 if (vega10_noretry)
73 qpd->sh_mem_config |=
74 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
75 #endif
76
77 qpd->sh_mem_ape1_limit = 0;
78 qpd->sh_mem_ape1_base = 0;
79 }
80
81 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
82
83 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
84
85 return 0;
86 }
87
init_sdma_vm_v10(struct device_queue_manager * dqm,struct queue * q,struct qcm_process_device * qpd)88 static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
89 struct qcm_process_device *qpd)
90 {
91 /* Not needed on SDMAv4 onwards any more */
92 q->properties.sdma_vm_addr = 0;
93 }
94