xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/amdgpu_dce_dmcu.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: amdgpu_dce_dmcu.c,v 1.2 2021/12/18 23:45:02 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2012-16 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: AMD
25  *
26  */
27 
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce_dmcu.c,v 1.2 2021/12/18 23:45:02 riastradh Exp $");
30 
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 
34 #include "core_types.h"
35 #include "link_encoder.h"
36 #include "dce_dmcu.h"
37 #include "dm_services.h"
38 #include "reg_helper.h"
39 #include "fixed31_32.h"
40 #include "dc.h"
41 
42 #define TO_DCE_DMCU(dmcu)\
43 	container_of(dmcu, struct dce_dmcu, base)
44 
45 #define REG(reg) \
46 	(dmcu_dce->regs->reg)
47 
48 #undef FN
49 #define FN(reg_name, field_name) \
50 	dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name
51 
52 #define CTX \
53 	dmcu_dce->base.ctx
54 
55 /* PSR related commands */
56 #define PSR_ENABLE 0x20
57 #define PSR_EXIT 0x21
58 #define PSR_SET 0x23
59 #define PSR_SET_WAITLOOP 0x31
60 #define MCP_INIT_DMCU 0x88
61 #define MCP_INIT_IRAM 0x89
62 #define MCP_SYNC_PHY_LOCK 0x90
63 #define MCP_SYNC_PHY_UNLOCK 0x91
64 #define MCP_BL_SET_PWM_FRAC 0x6A  /* Enable or disable Fractional PWM */
65 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK   0x00000001L
66 
67 // PSP FW version
68 #define mmMP0_SMN_C2PMSG_58				0x1607A
69 
70 //Register access policy version
71 #define mmMP0_SMN_C2PMSG_91				0x1609B
72 
dce_dmcu_init(struct dmcu * dmcu)73 static bool dce_dmcu_init(struct dmcu *dmcu)
74 {
75 	// Do nothing
76 	return true;
77 }
78 
dce_dmcu_load_iram(struct dmcu * dmcu,unsigned int start_offset,const char * src,unsigned int bytes)79 bool dce_dmcu_load_iram(struct dmcu *dmcu,
80 		unsigned int start_offset,
81 		const char *src,
82 		unsigned int bytes)
83 {
84 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
85 	unsigned int count = 0;
86 
87 	/* Enable write access to IRAM */
88 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
89 			IRAM_HOST_ACCESS_EN, 1,
90 			IRAM_WR_ADDR_AUTO_INC, 1);
91 
92 	REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
93 
94 	REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
95 
96 	for (count = 0; count < bytes; count++)
97 		REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
98 
99 	/* Disable write access to IRAM to allow dynamic sleep state */
100 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
101 			IRAM_HOST_ACCESS_EN, 0,
102 			IRAM_WR_ADDR_AUTO_INC, 0);
103 
104 	return true;
105 }
106 
dce_get_dmcu_psr_state(struct dmcu * dmcu,uint32_t * psr_state)107 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
108 {
109 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
110 
111 	uint32_t psr_state_offset = 0xf0;
112 
113 	/* Enable write access to IRAM */
114 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
115 
116 	REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
117 
118 	/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
119 	REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
120 
121 	/* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
122 	*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
123 
124 	/* Disable write access to IRAM after finished using IRAM
125 	 * in order to allow dynamic sleep state
126 	 */
127 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
128 }
129 
dce_dmcu_set_psr_enable(struct dmcu * dmcu,bool enable,bool wait)130 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
131 {
132 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
133 	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
134 	unsigned int dmcu_wait_reg_ready_interval = 100;
135 
136 	unsigned int retryCount;
137 	uint32_t psr_state = 0;
138 
139 	/* waitDMCUReadyForCmd */
140 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
141 				dmcu_wait_reg_ready_interval,
142 				dmcu_max_retry_on_wait_reg_ready);
143 
144 	/* setDMCUParam_Cmd */
145 	if (enable)
146 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
147 				PSR_ENABLE);
148 	else
149 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
150 				PSR_EXIT);
151 
152 	/* notifyDMCUMsg */
153 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
154 	if (wait == true) {
155 		for (retryCount = 0; retryCount <= 100; retryCount++) {
156 			dce_get_dmcu_psr_state(dmcu, &psr_state);
157 			if (enable) {
158 				if (psr_state != 0)
159 					break;
160 			} else {
161 				if (psr_state == 0)
162 					break;
163 			}
164 			udelay(10);
165 		}
166 	}
167 }
168 
dce_dmcu_setup_psr(struct dmcu * dmcu,struct dc_link * link,struct psr_context * psr_context)169 static bool dce_dmcu_setup_psr(struct dmcu *dmcu,
170 		struct dc_link *link,
171 		struct psr_context *psr_context)
172 {
173 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
174 
175 	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
176 	unsigned int dmcu_wait_reg_ready_interval = 100;
177 
178 	union dce_dmcu_psr_config_data_reg1 masterCmdData1;
179 	union dce_dmcu_psr_config_data_reg2 masterCmdData2;
180 	union dce_dmcu_psr_config_data_reg3 masterCmdData3;
181 
182 	link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
183 			psr_context->psrExitLinkTrainingRequired);
184 
185 	/* Enable static screen interrupts for PSR supported display */
186 	/* Disable the interrupt coming from other displays. */
187 	REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
188 			STATIC_SCREEN1_INT_TO_UC_EN, 0,
189 			STATIC_SCREEN2_INT_TO_UC_EN, 0,
190 			STATIC_SCREEN3_INT_TO_UC_EN, 0,
191 			STATIC_SCREEN4_INT_TO_UC_EN, 0);
192 
193 	switch (psr_context->controllerId) {
194 	/* Driver uses case 1 for unconfigured */
195 	case 1:
196 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
197 				STATIC_SCREEN1_INT_TO_UC_EN, 1);
198 		break;
199 	case 2:
200 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
201 				STATIC_SCREEN2_INT_TO_UC_EN, 1);
202 		break;
203 	case 3:
204 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
205 				STATIC_SCREEN3_INT_TO_UC_EN, 1);
206 		break;
207 	case 4:
208 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
209 				STATIC_SCREEN4_INT_TO_UC_EN, 1);
210 		break;
211 	case 5:
212 		/* CZ/NL only has 4 CRTC!!
213 		 * really valid.
214 		 * There is no interrupt enable mask for these instances.
215 		 */
216 		break;
217 	case 6:
218 		/* CZ/NL only has 4 CRTC!!
219 		 * These are here because they are defined in HW regspec,
220 		 * but not really valid. There is no interrupt enable mask
221 		 * for these instances.
222 		 */
223 		break;
224 	default:
225 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
226 				STATIC_SCREEN1_INT_TO_UC_EN, 1);
227 		break;
228 	}
229 
230 	link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
231 			psr_context->sdpTransmitLineNumDeadline);
232 
233 	/* waitDMCUReadyForCmd */
234 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
235 					dmcu_wait_reg_ready_interval,
236 					dmcu_max_retry_on_wait_reg_ready);
237 
238 	/* setDMCUParam_PSRHostConfigData */
239 	masterCmdData1.u32All = 0;
240 	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
241 	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
242 	masterCmdData1.bits.rfb_update_auto_en =
243 			psr_context->rfb_update_auto_en;
244 	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
245 	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
246 	masterCmdData1.bits.phy_type  = psr_context->phyType;
247 	masterCmdData1.bits.frame_cap_ind =
248 			psr_context->psrFrameCaptureIndicationReq;
249 	masterCmdData1.bits.aux_chan = psr_context->channel;
250 	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
251 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
252 					masterCmdData1.u32All);
253 
254 	masterCmdData2.u32All = 0;
255 	masterCmdData2.bits.dig_fe = psr_context->engineId;
256 	masterCmdData2.bits.dig_be = psr_context->transmitterId;
257 	masterCmdData2.bits.skip_wait_for_pll_lock =
258 			psr_context->skipPsrWaitForPllLock;
259 	masterCmdData2.bits.frame_delay = psr_context->frame_delay;
260 	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
261 	masterCmdData2.bits.num_of_controllers =
262 			psr_context->numberOfControllers;
263 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
264 			masterCmdData2.u32All);
265 
266 	masterCmdData3.u32All = 0;
267 	masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
268 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
269 			masterCmdData3.u32All);
270 
271 	/* setDMCUParam_Cmd */
272 	REG_UPDATE(MASTER_COMM_CMD_REG,
273 			MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
274 
275 	/* notifyDMCUMsg */
276 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
277 
278 	return true;
279 }
280 
dce_is_dmcu_initialized(struct dmcu * dmcu)281 static bool dce_is_dmcu_initialized(struct dmcu *dmcu)
282 {
283 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
284 	unsigned int dmcu_uc_reset;
285 
286 	/* microcontroller is not running */
287 	REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);
288 
289 	/* DMCU is not running */
290 	if (dmcu_uc_reset)
291 		return false;
292 
293 	return true;
294 }
295 
dce_psr_wait_loop(struct dmcu * dmcu,unsigned int wait_loop_number)296 static void dce_psr_wait_loop(
297 	struct dmcu *dmcu,
298 	unsigned int wait_loop_number)
299 {
300 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
301 	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
302 
303 	if (dmcu->cached_wait_loop_number == wait_loop_number)
304 		return;
305 
306 	/* DMCU is not running */
307 	if (!dce_is_dmcu_initialized(dmcu))
308 		return;
309 
310 	/* waitDMCUReadyForCmd */
311 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
312 
313 	masterCmdData1.u32 = 0;
314 	masterCmdData1.bits.wait_loop = wait_loop_number;
315 	dmcu->cached_wait_loop_number = wait_loop_number;
316 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
317 
318 	/* setDMCUParam_Cmd */
319 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
320 
321 	/* notifyDMCUMsg */
322 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
323 }
324 
dce_get_psr_wait_loop(struct dmcu * dmcu,unsigned int * psr_wait_loop_number)325 static void dce_get_psr_wait_loop(
326 		struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
327 {
328 	*psr_wait_loop_number = dmcu->cached_wait_loop_number;
329 	return;
330 }
331 
332 #if defined(CONFIG_DRM_AMD_DC_DCN)
dcn10_get_dmcu_version(struct dmcu * dmcu)333 static void dcn10_get_dmcu_version(struct dmcu *dmcu)
334 {
335 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
336 	uint32_t dmcu_version_offset = 0xf1;
337 
338 	/* Enable write access to IRAM */
339 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
340 			IRAM_HOST_ACCESS_EN, 1,
341 			IRAM_RD_ADDR_AUTO_INC, 1);
342 
343 	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
344 
345 	/* Write address to IRAM_RD_ADDR and read from DATA register */
346 	REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
347 	dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
348 	dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);
349 	dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);
350 	dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
351 						REG_READ(DMCU_IRAM_RD_DATA));
352 
353 	/* Disable write access to IRAM to allow dynamic sleep state */
354 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
355 			IRAM_HOST_ACCESS_EN, 0,
356 			IRAM_RD_ADDR_AUTO_INC, 0);
357 }
358 
dcn10_dmcu_enable_fractional_pwm(struct dmcu * dmcu,uint32_t fractional_pwm)359 static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu,
360 		uint32_t fractional_pwm)
361 {
362 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
363 
364 	/* Wait until microcontroller is ready to process interrupt */
365 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
366 
367 	/* Set PWM fractional enable/disable */
368 	REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm);
369 
370 	/* Set command to enable or disable fractional PWM microcontroller */
371 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
372 			MCP_BL_SET_PWM_FRAC);
373 
374 	/* Notify microcontroller of new command */
375 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
376 
377 	/* Ensure command has been executed before continuing */
378 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
379 }
380 
dcn10_dmcu_init(struct dmcu * dmcu)381 static bool dcn10_dmcu_init(struct dmcu *dmcu)
382 {
383 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
384 	const struct dc_config *config = &dmcu->ctx->dc->config;
385 	bool status = false;
386 
387 	PERF_TRACE();
388 	/*  Definition of DC_DMCU_SCRATCH
389 	 *  0 : firmare not loaded
390 	 *  1 : PSP load DMCU FW but not initialized
391 	 *  2 : Firmware already initialized
392 	 */
393 	dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
394 
395 	switch (dmcu->dmcu_state) {
396 	case DMCU_UNLOADED:
397 		status = false;
398 		break;
399 	case DMCU_LOADED_UNINITIALIZED:
400 		/* Wait until microcontroller is ready to process interrupt */
401 		REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
402 
403 		/* Set initialized ramping boundary value */
404 		REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
405 
406 		/* Set backlight ramping stepsize */
407 		REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize);
408 
409 		/* Set command to initialize microcontroller */
410 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
411 			MCP_INIT_DMCU);
412 
413 		/* Notify microcontroller of new command */
414 		REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
415 
416 		/* Ensure command has been executed before continuing */
417 		REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
418 
419 		// Check state is initialized
420 		dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
421 
422 		// If microcontroller is not in running state, fail
423 		if (dmcu->dmcu_state == DMCU_RUNNING) {
424 			/* Retrieve and cache the DMCU firmware version. */
425 			dcn10_get_dmcu_version(dmcu);
426 
427 			/* Initialize DMCU to use fractional PWM or not */
428 			dcn10_dmcu_enable_fractional_pwm(dmcu,
429 				(config->disable_fractional_pwm == false) ? 1 : 0);
430 			status = true;
431 		} else {
432 			status = false;
433 		}
434 
435 		break;
436 	case DMCU_RUNNING:
437 		status = true;
438 		break;
439 	default:
440 		status = false;
441 		break;
442 	}
443 
444 	PERF_TRACE();
445 	return status;
446 }
447 
dcn21_dmcu_init(struct dmcu * dmcu)448 static bool dcn21_dmcu_init(struct dmcu *dmcu)
449 {
450 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
451 	uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15);
452 
453 	if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) {
454 		return false;
455 	}
456 
457 	return dcn10_dmcu_init(dmcu);
458 }
459 
dcn10_dmcu_load_iram(struct dmcu * dmcu,unsigned int start_offset,const char * src,unsigned int bytes)460 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
461 		unsigned int start_offset,
462 		const char *src,
463 		unsigned int bytes)
464 {
465 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
466 	unsigned int count = 0;
467 
468 	/* If microcontroller is not running, do nothing */
469 	if (dmcu->dmcu_state != DMCU_RUNNING)
470 		return false;
471 
472 	/* Enable write access to IRAM */
473 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
474 			IRAM_HOST_ACCESS_EN, 1,
475 			IRAM_WR_ADDR_AUTO_INC, 1);
476 
477 	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
478 
479 	REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
480 
481 	for (count = 0; count < bytes; count++)
482 		REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
483 
484 	/* Disable write access to IRAM to allow dynamic sleep state */
485 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
486 			IRAM_HOST_ACCESS_EN, 0,
487 			IRAM_WR_ADDR_AUTO_INC, 0);
488 
489 	/* Wait until microcontroller is ready to process interrupt */
490 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
491 
492 	/* Set command to signal IRAM is loaded and to initialize IRAM */
493 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
494 			MCP_INIT_IRAM);
495 
496 	/* Notify microcontroller of new command */
497 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
498 
499 	/* Ensure command has been executed before continuing */
500 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
501 
502 	return true;
503 }
504 
dcn10_get_dmcu_psr_state(struct dmcu * dmcu,uint32_t * psr_state)505 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
506 {
507 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
508 
509 	uint32_t psr_state_offset = 0xf0;
510 
511 	/* If microcontroller is not running, do nothing */
512 	if (dmcu->dmcu_state != DMCU_RUNNING)
513 		return;
514 
515 	/* Enable write access to IRAM */
516 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
517 
518 	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
519 
520 	/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
521 	REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
522 
523 	/* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
524 	*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
525 
526 	/* Disable write access to IRAM after finished using IRAM
527 	 * in order to allow dynamic sleep state
528 	 */
529 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
530 }
531 
dcn10_dmcu_set_psr_enable(struct dmcu * dmcu,bool enable,bool wait)532 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
533 {
534 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
535 	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
536 	unsigned int dmcu_wait_reg_ready_interval = 100;
537 
538 	unsigned int retryCount;
539 	uint32_t psr_state = 0;
540 
541 	/* If microcontroller is not running, do nothing */
542 	if (dmcu->dmcu_state != DMCU_RUNNING)
543 		return;
544 
545 	/* waitDMCUReadyForCmd */
546 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
547 				dmcu_wait_reg_ready_interval,
548 				dmcu_max_retry_on_wait_reg_ready);
549 
550 	/* setDMCUParam_Cmd */
551 	if (enable)
552 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
553 				PSR_ENABLE);
554 	else
555 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
556 				PSR_EXIT);
557 
558 	/* notifyDMCUMsg */
559 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
560 
561 	/* Below loops 1000 x 500us = 500 ms.
562 	 *  Exit PSR may need to wait 1-2 frames to power up. Timeout after at
563 	 *  least a few frames. Should never hit the max retry assert below.
564 	 */
565 	if (wait == true) {
566 		for (retryCount = 0; retryCount <= 1000; retryCount++) {
567 			dcn10_get_dmcu_psr_state(dmcu, &psr_state);
568 			if (enable) {
569 				if (psr_state != 0)
570 					break;
571 			} else {
572 				if (psr_state == 0)
573 					break;
574 			}
575 			udelay(500);
576 		}
577 
578 		/* assert if max retry hit */
579 		if (retryCount >= 1000)
580 			ASSERT(0);
581 	}
582 }
583 
dcn10_dmcu_setup_psr(struct dmcu * dmcu,struct dc_link * link,struct psr_context * psr_context)584 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
585 		struct dc_link *link,
586 		struct psr_context *psr_context)
587 {
588 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
589 
590 	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
591 	unsigned int dmcu_wait_reg_ready_interval = 100;
592 
593 	union dce_dmcu_psr_config_data_reg1 masterCmdData1;
594 	union dce_dmcu_psr_config_data_reg2 masterCmdData2;
595 	union dce_dmcu_psr_config_data_reg3 masterCmdData3;
596 
597 	/* If microcontroller is not running, do nothing */
598 	if (dmcu->dmcu_state != DMCU_RUNNING)
599 		return false;
600 
601 	link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
602 			psr_context->psrExitLinkTrainingRequired);
603 
604 	/* Enable static screen interrupts for PSR supported display */
605 	/* Disable the interrupt coming from other displays. */
606 	REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
607 			STATIC_SCREEN1_INT_TO_UC_EN, 0,
608 			STATIC_SCREEN2_INT_TO_UC_EN, 0,
609 			STATIC_SCREEN3_INT_TO_UC_EN, 0,
610 			STATIC_SCREEN4_INT_TO_UC_EN, 0);
611 
612 	switch (psr_context->controllerId) {
613 	/* Driver uses case 1 for unconfigured */
614 	case 1:
615 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
616 				STATIC_SCREEN1_INT_TO_UC_EN, 1);
617 		break;
618 	case 2:
619 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
620 				STATIC_SCREEN2_INT_TO_UC_EN, 1);
621 		break;
622 	case 3:
623 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
624 				STATIC_SCREEN3_INT_TO_UC_EN, 1);
625 		break;
626 	case 4:
627 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
628 				STATIC_SCREEN4_INT_TO_UC_EN, 1);
629 		break;
630 	case 5:
631 		/* CZ/NL only has 4 CRTC!!
632 		 * really valid.
633 		 * There is no interrupt enable mask for these instances.
634 		 */
635 		break;
636 	case 6:
637 		/* CZ/NL only has 4 CRTC!!
638 		 * These are here because they are defined in HW regspec,
639 		 * but not really valid. There is no interrupt enable mask
640 		 * for these instances.
641 		 */
642 		break;
643 	default:
644 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
645 				STATIC_SCREEN1_INT_TO_UC_EN, 1);
646 		break;
647 	}
648 
649 	link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
650 			psr_context->sdpTransmitLineNumDeadline);
651 
652 	if (psr_context->allow_smu_optimizations)
653 		REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
654 
655 	/* waitDMCUReadyForCmd */
656 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
657 			dmcu_wait_reg_ready_interval,
658 			dmcu_max_retry_on_wait_reg_ready);
659 
660 	/* setDMCUParam_PSRHostConfigData */
661 	masterCmdData1.u32All = 0;
662 	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
663 	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
664 	masterCmdData1.bits.rfb_update_auto_en =
665 			psr_context->rfb_update_auto_en;
666 	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
667 	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
668 	masterCmdData1.bits.phy_type  = psr_context->phyType;
669 	masterCmdData1.bits.frame_cap_ind =
670 			psr_context->psrFrameCaptureIndicationReq;
671 	masterCmdData1.bits.aux_chan = psr_context->channel;
672 	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
673 	masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;
674 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
675 					masterCmdData1.u32All);
676 
677 	masterCmdData2.u32All = 0;
678 	masterCmdData2.bits.dig_fe = psr_context->engineId;
679 	masterCmdData2.bits.dig_be = psr_context->transmitterId;
680 	masterCmdData2.bits.skip_wait_for_pll_lock =
681 			psr_context->skipPsrWaitForPllLock;
682 	masterCmdData2.bits.frame_delay = psr_context->frame_delay;
683 	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
684 	masterCmdData2.bits.num_of_controllers =
685 			psr_context->numberOfControllers;
686 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
687 			masterCmdData2.u32All);
688 
689 	masterCmdData3.u32All = 0;
690 	masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
691 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
692 			masterCmdData3.u32All);
693 
694 
695 	/* setDMCUParam_Cmd */
696 	REG_UPDATE(MASTER_COMM_CMD_REG,
697 			MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
698 
699 	/* notifyDMCUMsg */
700 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
701 
702 	/* waitDMCUReadyForCmd */
703 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
704 
705 	return true;
706 }
707 
dcn10_psr_wait_loop(struct dmcu * dmcu,unsigned int wait_loop_number)708 static void dcn10_psr_wait_loop(
709 	struct dmcu *dmcu,
710 	unsigned int wait_loop_number)
711 {
712 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
713 	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
714 
715 	/* If microcontroller is not running, do nothing */
716 	if (dmcu->dmcu_state != DMCU_RUNNING)
717 		return;
718 
719 	if (wait_loop_number != 0) {
720 	/* waitDMCUReadyForCmd */
721 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
722 
723 	masterCmdData1.u32 = 0;
724 	masterCmdData1.bits.wait_loop = wait_loop_number;
725 	dmcu->cached_wait_loop_number = wait_loop_number;
726 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
727 
728 	/* setDMCUParam_Cmd */
729 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
730 
731 	/* notifyDMCUMsg */
732 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
733 	}
734 }
735 
dcn10_get_psr_wait_loop(struct dmcu * dmcu,unsigned int * psr_wait_loop_number)736 static void dcn10_get_psr_wait_loop(
737 		struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
738 {
739 	*psr_wait_loop_number = dmcu->cached_wait_loop_number;
740 	return;
741 }
742 
dcn10_is_dmcu_initialized(struct dmcu * dmcu)743 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
744 {
745 	/* microcontroller is not running */
746 	if (dmcu->dmcu_state != DMCU_RUNNING)
747 		return false;
748 	return true;
749 }
750 
751 
752 
dcn20_lock_phy(struct dmcu * dmcu)753 static bool dcn20_lock_phy(struct dmcu *dmcu)
754 {
755 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
756 
757 	/* If microcontroller is not running, do nothing */
758 	if (dmcu->dmcu_state != DMCU_RUNNING)
759 		return false;
760 
761 	/* waitDMCUReadyForCmd */
762 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
763 
764 	/* setDMCUParam_Cmd */
765 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK);
766 
767 	/* notifyDMCUMsg */
768 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
769 
770 	/* waitDMCUReadyForCmd */
771 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
772 
773 	return true;
774 }
775 
dcn20_unlock_phy(struct dmcu * dmcu)776 static bool dcn20_unlock_phy(struct dmcu *dmcu)
777 {
778 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
779 
780 	/* If microcontroller is not running, do nothing */
781 	if (dmcu->dmcu_state != DMCU_RUNNING)
782 		return false;
783 
784 	/* waitDMCUReadyForCmd */
785 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
786 
787 	/* setDMCUParam_Cmd */
788 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK);
789 
790 	/* notifyDMCUMsg */
791 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
792 
793 	/* waitDMCUReadyForCmd */
794 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
795 
796 	return true;
797 }
798 
799 #endif //(CONFIG_DRM_AMD_DC_DCN)
800 
801 static const struct dmcu_funcs dce_funcs = {
802 	.dmcu_init = dce_dmcu_init,
803 	.load_iram = dce_dmcu_load_iram,
804 	.set_psr_enable = dce_dmcu_set_psr_enable,
805 	.setup_psr = dce_dmcu_setup_psr,
806 	.get_psr_state = dce_get_dmcu_psr_state,
807 	.set_psr_wait_loop = dce_psr_wait_loop,
808 	.get_psr_wait_loop = dce_get_psr_wait_loop,
809 	.is_dmcu_initialized = dce_is_dmcu_initialized
810 };
811 
812 #if defined(CONFIG_DRM_AMD_DC_DCN)
813 static const struct dmcu_funcs dcn10_funcs = {
814 	.dmcu_init = dcn10_dmcu_init,
815 	.load_iram = dcn10_dmcu_load_iram,
816 	.set_psr_enable = dcn10_dmcu_set_psr_enable,
817 	.setup_psr = dcn10_dmcu_setup_psr,
818 	.get_psr_state = dcn10_get_dmcu_psr_state,
819 	.set_psr_wait_loop = dcn10_psr_wait_loop,
820 	.get_psr_wait_loop = dcn10_get_psr_wait_loop,
821 	.is_dmcu_initialized = dcn10_is_dmcu_initialized
822 };
823 
824 static const struct dmcu_funcs dcn20_funcs = {
825 	.dmcu_init = dcn10_dmcu_init,
826 	.load_iram = dcn10_dmcu_load_iram,
827 	.set_psr_enable = dcn10_dmcu_set_psr_enable,
828 	.setup_psr = dcn10_dmcu_setup_psr,
829 	.get_psr_state = dcn10_get_dmcu_psr_state,
830 	.set_psr_wait_loop = dcn10_psr_wait_loop,
831 	.get_psr_wait_loop = dcn10_get_psr_wait_loop,
832 	.is_dmcu_initialized = dcn10_is_dmcu_initialized,
833 	.lock_phy = dcn20_lock_phy,
834 	.unlock_phy = dcn20_unlock_phy
835 };
836 
837 static const struct dmcu_funcs dcn21_funcs = {
838 	.dmcu_init = dcn21_dmcu_init,
839 	.load_iram = dcn10_dmcu_load_iram,
840 	.set_psr_enable = dcn10_dmcu_set_psr_enable,
841 	.setup_psr = dcn10_dmcu_setup_psr,
842 	.get_psr_state = dcn10_get_dmcu_psr_state,
843 	.set_psr_wait_loop = dcn10_psr_wait_loop,
844 	.get_psr_wait_loop = dcn10_get_psr_wait_loop,
845 	.is_dmcu_initialized = dcn10_is_dmcu_initialized,
846 	.lock_phy = dcn20_lock_phy,
847 	.unlock_phy = dcn20_unlock_phy
848 };
849 #endif
850 
dce_dmcu_construct(struct dce_dmcu * dmcu_dce,struct dc_context * ctx,const struct dce_dmcu_registers * regs,const struct dce_dmcu_shift * dmcu_shift,const struct dce_dmcu_mask * dmcu_mask)851 static void dce_dmcu_construct(
852 	struct dce_dmcu *dmcu_dce,
853 	struct dc_context *ctx,
854 	const struct dce_dmcu_registers *regs,
855 	const struct dce_dmcu_shift *dmcu_shift,
856 	const struct dce_dmcu_mask *dmcu_mask)
857 {
858 	struct dmcu *base = &dmcu_dce->base;
859 
860 	base->ctx = ctx;
861 	base->funcs = &dce_funcs;
862 	base->cached_wait_loop_number = 0;
863 
864 	dmcu_dce->regs = regs;
865 	dmcu_dce->dmcu_shift = dmcu_shift;
866 	dmcu_dce->dmcu_mask = dmcu_mask;
867 }
868 
869 #if defined(CONFIG_DRM_AMD_DC_DCN)
dcn21_dmcu_construct(struct dce_dmcu * dmcu_dce,struct dc_context * ctx,const struct dce_dmcu_registers * regs,const struct dce_dmcu_shift * dmcu_shift,const struct dce_dmcu_mask * dmcu_mask)870 static void dcn21_dmcu_construct(
871 		struct dce_dmcu *dmcu_dce,
872 		struct dc_context *ctx,
873 		const struct dce_dmcu_registers *regs,
874 		const struct dce_dmcu_shift *dmcu_shift,
875 		const struct dce_dmcu_mask *dmcu_mask)
876 {
877 	uint32_t psp_version = 0;
878 
879 	dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
880 
881 	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
882 		psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58);
883 		dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029);
884 		dmcu_dce->base.psp_version = psp_version;
885 	}
886 }
887 #endif
888 
dce_dmcu_create(struct dc_context * ctx,const struct dce_dmcu_registers * regs,const struct dce_dmcu_shift * dmcu_shift,const struct dce_dmcu_mask * dmcu_mask)889 struct dmcu *dce_dmcu_create(
890 	struct dc_context *ctx,
891 	const struct dce_dmcu_registers *regs,
892 	const struct dce_dmcu_shift *dmcu_shift,
893 	const struct dce_dmcu_mask *dmcu_mask)
894 {
895 	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
896 
897 	if (dmcu_dce == NULL) {
898 		BREAK_TO_DEBUGGER();
899 		return NULL;
900 	}
901 
902 	dce_dmcu_construct(
903 		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
904 
905 	dmcu_dce->base.funcs = &dce_funcs;
906 
907 	return &dmcu_dce->base;
908 }
909 
910 #if defined(CONFIG_DRM_AMD_DC_DCN)
dcn10_dmcu_create(struct dc_context * ctx,const struct dce_dmcu_registers * regs,const struct dce_dmcu_shift * dmcu_shift,const struct dce_dmcu_mask * dmcu_mask)911 struct dmcu *dcn10_dmcu_create(
912 	struct dc_context *ctx,
913 	const struct dce_dmcu_registers *regs,
914 	const struct dce_dmcu_shift *dmcu_shift,
915 	const struct dce_dmcu_mask *dmcu_mask)
916 {
917 	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
918 
919 	if (dmcu_dce == NULL) {
920 		BREAK_TO_DEBUGGER();
921 		return NULL;
922 	}
923 
924 	dce_dmcu_construct(
925 		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
926 
927 	dmcu_dce->base.funcs = &dcn10_funcs;
928 
929 	return &dmcu_dce->base;
930 }
931 
dcn20_dmcu_create(struct dc_context * ctx,const struct dce_dmcu_registers * regs,const struct dce_dmcu_shift * dmcu_shift,const struct dce_dmcu_mask * dmcu_mask)932 struct dmcu *dcn20_dmcu_create(
933 	struct dc_context *ctx,
934 	const struct dce_dmcu_registers *regs,
935 	const struct dce_dmcu_shift *dmcu_shift,
936 	const struct dce_dmcu_mask *dmcu_mask)
937 {
938 	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
939 
940 	if (dmcu_dce == NULL) {
941 		BREAK_TO_DEBUGGER();
942 		return NULL;
943 	}
944 
945 	dce_dmcu_construct(
946 		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
947 
948 	dmcu_dce->base.funcs = &dcn20_funcs;
949 
950 	return &dmcu_dce->base;
951 }
952 
dcn21_dmcu_create(struct dc_context * ctx,const struct dce_dmcu_registers * regs,const struct dce_dmcu_shift * dmcu_shift,const struct dce_dmcu_mask * dmcu_mask)953 struct dmcu *dcn21_dmcu_create(
954 	struct dc_context *ctx,
955 	const struct dce_dmcu_registers *regs,
956 	const struct dce_dmcu_shift *dmcu_shift,
957 	const struct dce_dmcu_mask *dmcu_mask)
958 {
959 	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
960 
961 	if (dmcu_dce == NULL) {
962 		BREAK_TO_DEBUGGER();
963 		return NULL;
964 	}
965 
966 	dcn21_dmcu_construct(
967 		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
968 
969 	dmcu_dce->base.funcs = &dcn21_funcs;
970 
971 	return &dmcu_dce->base;
972 }
973 #endif
974 
dce_dmcu_destroy(struct dmcu ** dmcu)975 void dce_dmcu_destroy(struct dmcu **dmcu)
976 {
977 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
978 
979 	kfree(dmcu_dce);
980 	*dmcu = NULL;
981 }
982