1 /* $NetBSD: radeon_evergreen_hdmi.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2008 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 * Copyright 2009 Christian König.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors: Christian König
27 * Rafał Miłecki
28 */
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: radeon_evergreen_hdmi.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $");
31
32 #include <linux/hdmi.h>
33
34 #include <drm/radeon_drm.h>
35 #include "radeon.h"
36 #include "radeon_asic.h"
37 #include "radeon_audio.h"
38 #include "evergreend.h"
39 #include "atom.h"
40
41 /* enable the audio stream */
dce4_audio_enable(struct radeon_device * rdev,struct r600_audio_pin * pin,u8 enable_mask)42 void dce4_audio_enable(struct radeon_device *rdev,
43 struct r600_audio_pin *pin,
44 u8 enable_mask)
45 {
46 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
47
48 if (!pin)
49 return;
50
51 if (enable_mask) {
52 tmp |= AUDIO_ENABLED;
53 if (enable_mask & 1)
54 tmp |= PIN0_AUDIO_ENABLED;
55 if (enable_mask & 2)
56 tmp |= PIN1_AUDIO_ENABLED;
57 if (enable_mask & 4)
58 tmp |= PIN2_AUDIO_ENABLED;
59 if (enable_mask & 8)
60 tmp |= PIN3_AUDIO_ENABLED;
61 } else {
62 tmp &= ~(AUDIO_ENABLED |
63 PIN0_AUDIO_ENABLED |
64 PIN1_AUDIO_ENABLED |
65 PIN2_AUDIO_ENABLED |
66 PIN3_AUDIO_ENABLED);
67 }
68
69 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
70 }
71
evergreen_hdmi_update_acr(struct drm_encoder * encoder,long offset,const struct radeon_hdmi_acr * acr)72 void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
73 const struct radeon_hdmi_acr *acr)
74 {
75 struct drm_device *dev = encoder->dev;
76 struct radeon_device *rdev = dev->dev_private;
77 int bpc = 8;
78
79 if (encoder->crtc) {
80 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
81 bpc = radeon_crtc->bpc;
82 }
83
84 if (bpc > 8)
85 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
86 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
87 else
88 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
89 HDMI_ACR_SOURCE | /* select SW CTS value */
90 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
91
92 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
93 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
94
95 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
96 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
97
98 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
99 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
100 }
101
dce4_afmt_write_latency_fields(struct drm_encoder * encoder,struct drm_connector * connector,struct drm_display_mode * mode)102 void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
103 struct drm_connector *connector, struct drm_display_mode *mode)
104 {
105 struct radeon_device *rdev = encoder->dev->dev_private;
106 u32 tmp = 0;
107
108 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
109 if (connector->latency_present[1])
110 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
111 AUDIO_LIPSYNC(connector->audio_latency[1]);
112 else
113 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
114 } else {
115 if (connector->latency_present[0])
116 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
117 AUDIO_LIPSYNC(connector->audio_latency[0]);
118 else
119 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
120 }
121 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
122 }
123
dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder * encoder,u8 * sadb,int sad_count)124 void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
125 u8 *sadb, int sad_count)
126 {
127 struct radeon_device *rdev = encoder->dev->dev_private;
128 u32 tmp;
129
130 /* program the speaker allocation */
131 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
132 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
133 /* set HDMI mode */
134 tmp |= HDMI_CONNECTION;
135 if (sad_count)
136 tmp |= SPEAKER_ALLOCATION(sadb[0]);
137 else
138 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
139 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
140 }
141
dce4_afmt_dp_write_speaker_allocation(struct drm_encoder * encoder,u8 * sadb,int sad_count)142 void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
143 u8 *sadb, int sad_count)
144 {
145 struct radeon_device *rdev = encoder->dev->dev_private;
146 u32 tmp;
147
148 /* program the speaker allocation */
149 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
150 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
151 /* set DP mode */
152 tmp |= DP_CONNECTION;
153 if (sad_count)
154 tmp |= SPEAKER_ALLOCATION(sadb[0]);
155 else
156 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
157 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
158 }
159
evergreen_hdmi_write_sad_regs(struct drm_encoder * encoder,struct cea_sad * sads,int sad_count)160 void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
161 struct cea_sad *sads, int sad_count)
162 {
163 int i;
164 struct radeon_device *rdev = encoder->dev->dev_private;
165 static const u16 eld_reg_to_type[][2] = {
166 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
167 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
168 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
169 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
170 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
171 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
172 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
173 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
174 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
175 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
176 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
177 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
178 };
179
180 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
181 u32 value = 0;
182 u8 stereo_freqs = 0;
183 int max_channels = -1;
184 int j;
185
186 for (j = 0; j < sad_count; j++) {
187 struct cea_sad *sad = &sads[j];
188
189 if (sad->format == eld_reg_to_type[i][1]) {
190 if (sad->channels > max_channels) {
191 value = MAX_CHANNELS(sad->channels) |
192 DESCRIPTOR_BYTE_2(sad->byte2) |
193 SUPPORTED_FREQUENCIES(sad->freq);
194 max_channels = sad->channels;
195 }
196
197 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
198 stereo_freqs |= sad->freq;
199 else
200 break;
201 }
202 }
203
204 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
205
206 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
207 }
208 }
209
210 /*
211 * build a AVI Info Frame
212 */
evergreen_set_avi_packet(struct radeon_device * rdev,u32 offset,unsigned char * buffer,size_t size)213 void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,
214 unsigned char *buffer, size_t size)
215 {
216 uint8_t *frame = buffer + 3;
217
218 WREG32(AFMT_AVI_INFO0 + offset,
219 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
220 WREG32(AFMT_AVI_INFO1 + offset,
221 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
222 WREG32(AFMT_AVI_INFO2 + offset,
223 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
224 WREG32(AFMT_AVI_INFO3 + offset,
225 frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
226
227 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
228 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
229 ~HDMI_AVI_INFO_LINE_MASK);
230 }
231
dce4_hdmi_audio_set_dto(struct radeon_device * rdev,struct radeon_crtc * crtc,unsigned int clock)232 void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
233 struct radeon_crtc *crtc, unsigned int clock)
234 {
235 unsigned int max_ratio = clock / 24000;
236 u32 dto_phase;
237 u32 wallclock_ratio;
238 u32 value;
239
240 if (max_ratio >= 8) {
241 dto_phase = 192 * 1000;
242 wallclock_ratio = 3;
243 } else if (max_ratio >= 4) {
244 dto_phase = 96 * 1000;
245 wallclock_ratio = 2;
246 } else if (max_ratio >= 2) {
247 dto_phase = 48 * 1000;
248 wallclock_ratio = 1;
249 } else {
250 dto_phase = 24 * 1000;
251 wallclock_ratio = 0;
252 }
253
254 value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
255 value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
256 value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;
257 WREG32(DCCG_AUDIO_DTO0_CNTL, value);
258
259 /* Two dtos; generally use dto0 for HDMI */
260 value = 0;
261
262 if (crtc)
263 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
264
265 WREG32(DCCG_AUDIO_DTO_SOURCE, value);
266
267 /* Express [24MHz / target pixel clock] as an exact rational
268 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
269 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
270 */
271 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
272 WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
273 }
274
dce4_dp_audio_set_dto(struct radeon_device * rdev,struct radeon_crtc * crtc,unsigned int clock)275 void dce4_dp_audio_set_dto(struct radeon_device *rdev,
276 struct radeon_crtc *crtc, unsigned int clock)
277 {
278 u32 value;
279
280 value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
281 value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO;
282 WREG32(DCCG_AUDIO_DTO1_CNTL, value);
283
284 /* Two dtos; generally use dto1 for DP */
285 value = 0;
286 value |= DCCG_AUDIO_DTO_SEL;
287
288 if (crtc)
289 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
290
291 WREG32(DCCG_AUDIO_DTO_SOURCE, value);
292
293 /* Express [24MHz / target pixel clock] as an exact rational
294 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
295 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
296 */
297 if (ASIC_IS_DCE41(rdev)) {
298 unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) &
299 DENTIST_DPREFCLK_WDIVIDER_MASK) >>
300 DENTIST_DPREFCLK_WDIVIDER_SHIFT;
301 div = radeon_audio_decode_dfs_div(div);
302
303 if (div)
304 clock = 100 * clock / div;
305 }
306
307 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
308 WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
309 }
310
dce4_set_vbi_packet(struct drm_encoder * encoder,u32 offset)311 void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
312 {
313 struct drm_device *dev = encoder->dev;
314 struct radeon_device *rdev = dev->dev_private;
315
316 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
317 HDMI_NULL_SEND | /* send null packets when required */
318 HDMI_GC_SEND | /* send general control packets */
319 HDMI_GC_CONT); /* send general control packets every frame */
320 }
321
dce4_hdmi_set_color_depth(struct drm_encoder * encoder,u32 offset,int bpc)322 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)
323 {
324 struct drm_device *dev = encoder->dev;
325 struct radeon_device *rdev = dev->dev_private;
326 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
327 uint32_t val;
328
329 val = RREG32(HDMI_CONTROL + offset);
330 val &= ~HDMI_DEEP_COLOR_ENABLE;
331 val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
332
333 switch (bpc) {
334 case 0:
335 case 6:
336 case 8:
337 case 16:
338 default:
339 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
340 connector->name, bpc);
341 break;
342 case 10:
343 val |= HDMI_DEEP_COLOR_ENABLE;
344 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
345 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
346 connector->name);
347 break;
348 case 12:
349 val |= HDMI_DEEP_COLOR_ENABLE;
350 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
351 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
352 connector->name);
353 break;
354 }
355
356 WREG32(HDMI_CONTROL + offset, val);
357 }
358
dce4_set_audio_packet(struct drm_encoder * encoder,u32 offset)359 void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)
360 {
361 struct drm_device *dev = encoder->dev;
362 struct radeon_device *rdev = dev->dev_private;
363
364 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
365 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
366
367 WREG32(AFMT_60958_0 + offset,
368 AFMT_60958_CS_CHANNEL_NUMBER_L(1));
369
370 WREG32(AFMT_60958_1 + offset,
371 AFMT_60958_CS_CHANNEL_NUMBER_R(2));
372
373 WREG32(AFMT_60958_2 + offset,
374 AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
375 AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
376 AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
377 AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
378 AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
379 AFMT_60958_CS_CHANNEL_NUMBER_7(8));
380
381 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
382 AFMT_AUDIO_CHANNEL_ENABLE(0xff));
383
384 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
385 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
386 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
387
388 /* allow 60958 channel status and send audio packets fields to be updated */
389 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
390 AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE);
391 }
392
393
dce4_set_mute(struct drm_encoder * encoder,u32 offset,bool mute)394 void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
395 {
396 struct drm_device *dev = encoder->dev;
397 struct radeon_device *rdev = dev->dev_private;
398
399 if (mute)
400 WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);
401 else
402 WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);
403 }
404
evergreen_hdmi_enable(struct drm_encoder * encoder,bool enable)405 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
406 {
407 struct drm_device *dev = encoder->dev;
408 struct radeon_device *rdev = dev->dev_private;
409 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
410 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
411
412 if (!dig || !dig->afmt)
413 return;
414
415 if (enable) {
416 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
417
418 if (connector && drm_detect_monitor_audio(radeon_connector_edid(connector))) {
419 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
420 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
421 HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */
422 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
423 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
424 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
425 AFMT_AUDIO_SAMPLE_SEND);
426 } else {
427 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
428 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
429 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
430 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
431 ~AFMT_AUDIO_SAMPLE_SEND);
432 }
433 } else {
434 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
435 ~AFMT_AUDIO_SAMPLE_SEND);
436 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);
437 }
438
439 dig->afmt->enabled = enable;
440
441 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
442 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
443 }
444
evergreen_dp_enable(struct drm_encoder * encoder,bool enable)445 void evergreen_dp_enable(struct drm_encoder *encoder, bool enable)
446 {
447 struct drm_device *dev = encoder->dev;
448 struct radeon_device *rdev = dev->dev_private;
449 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
450 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
451 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
452
453 if (!dig || !dig->afmt)
454 return;
455
456 if (enable && connector &&
457 drm_detect_monitor_audio(radeon_connector_edid(connector))) {
458 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
459 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
460 struct radeon_connector_atom_dig *dig_connector;
461 uint32_t val;
462
463 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
464 AFMT_AUDIO_SAMPLE_SEND);
465
466 WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
467 EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
468
469 if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) {
470 dig_connector = radeon_connector->con_priv;
471 val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);
472 val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);
473
474 if (dig_connector->dp_clock == 162000)
475 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);
476 else
477 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);
478
479 WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);
480 }
481
482 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
483 EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */
484 EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */
485 EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */
486 EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */
487 } else {
488 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
489 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
490 ~AFMT_AUDIO_SAMPLE_SEND);
491 }
492
493 dig->afmt->enabled = enable;
494 }
495