1 /* $NetBSD: amdgpu_dce110_resource.c,v 1.4 2021/12/19 11:59:30 riastradh Exp $ */
2
3 /*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce110_resource.c,v 1.4 2021/12/19 11:59:30 riastradh Exp $");
30
31 #include <linux/slab.h>
32
33 #include "dm_services.h"
34
35 #include "link_encoder.h"
36 #include "stream_encoder.h"
37
38 #include "resource.h"
39 #include "dce110/dce110_resource.h"
40 #include "include/irq_service_interface.h"
41 #include "dce/dce_audio.h"
42 #include "dce110/dce110_timing_generator.h"
43 #include "irq/dce110/irq_service_dce110.h"
44 #include "dce110/dce110_timing_generator_v.h"
45 #include "dce/dce_link_encoder.h"
46 #include "dce/dce_stream_encoder.h"
47 #include "dce/dce_mem_input.h"
48 #include "dce110/dce110_mem_input_v.h"
49 #include "dce/dce_ipp.h"
50 #include "dce/dce_transform.h"
51 #include "dce110/dce110_transform_v.h"
52 #include "dce/dce_opp.h"
53 #include "dce110/dce110_opp_v.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_hwseq.h"
56 #include "dce110/dce110_hw_sequencer.h"
57 #include "dce/dce_aux.h"
58 #include "dce/dce_abm.h"
59 #include "dce/dce_dmcu.h"
60 #include "dce/dce_i2c.h"
61
62 #define DC_LOGGER \
63 dc->ctx->logger
64
65 #include "dce110/dce110_compressor.h"
66
67 #include "reg_helper.h"
68
69 #include "dce/dce_11_0_d.h"
70 #include "dce/dce_11_0_sh_mask.h"
71
72 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
73 #include "gmc/gmc_8_2_d.h"
74 #include "gmc/gmc_8_2_sh_mask.h"
75 #endif
76
77 #ifndef mmDP_DPHY_INTERNAL_CTRL
78 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
79 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
80 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
81 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
82 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
83 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
84 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
85 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
86 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
87 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
88 #endif
89
90 #ifndef mmBIOS_SCRATCH_2
91 #define mmBIOS_SCRATCH_2 0x05CB
92 #define mmBIOS_SCRATCH_3 0x05CC
93 #define mmBIOS_SCRATCH_6 0x05CF
94 #endif
95
96 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
97 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
98 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
99 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
100 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
101 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
102 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
103 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
104 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
105 #endif
106
107 #ifndef mmDP_DPHY_FAST_TRAINING
108 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
109 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
110 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
111 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
112 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
113 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
114 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
115 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
116 #endif
117
118 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE
119 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
120 #endif
121
122 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
123 {
124 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
125 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
126 },
127 {
128 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
129 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
130 },
131 {
132 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
133 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
134 },
135 {
136 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
137 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
138 },
139 {
140 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
141 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
142 },
143 {
144 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
145 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
146 }
147 };
148
149 /* set register offset */
150 #define SR(reg_name)\
151 .reg_name = mm ## reg_name
152
153 /* set register offset with instance */
154 #define SRI(reg_name, block, id)\
155 .reg_name = mm ## block ## id ## _ ## reg_name
156
157 static const struct dce_dmcu_registers dmcu_regs = {
158 DMCU_DCE110_COMMON_REG_LIST()
159 };
160
161 static const struct dce_dmcu_shift dmcu_shift = {
162 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
163 };
164
165 static const struct dce_dmcu_mask dmcu_mask = {
166 DMCU_MASK_SH_LIST_DCE110(_MASK)
167 };
168
169 static const struct dce_abm_registers abm_regs = {
170 ABM_DCE110_COMMON_REG_LIST()
171 };
172
173 static const struct dce_abm_shift abm_shift = {
174 ABM_MASK_SH_LIST_DCE110(__SHIFT)
175 };
176
177 static const struct dce_abm_mask abm_mask = {
178 ABM_MASK_SH_LIST_DCE110(_MASK)
179 };
180
181 #define ipp_regs(id)\
182 [id] = {\
183 IPP_DCE110_REG_LIST_DCE_BASE(id)\
184 }
185
186 static const struct dce_ipp_registers ipp_regs[] = {
187 ipp_regs(0),
188 ipp_regs(1),
189 ipp_regs(2)
190 };
191
192 static const struct dce_ipp_shift ipp_shift = {
193 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
194 };
195
196 static const struct dce_ipp_mask ipp_mask = {
197 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
198 };
199
200 #define transform_regs(id)\
201 [id] = {\
202 XFM_COMMON_REG_LIST_DCE110(id)\
203 }
204
205 static const struct dce_transform_registers xfm_regs[] = {
206 transform_regs(0),
207 transform_regs(1),
208 transform_regs(2)
209 };
210
211 static const struct dce_transform_shift xfm_shift = {
212 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
213 };
214
215 static const struct dce_transform_mask xfm_mask = {
216 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
217 };
218
219 #define aux_regs(id)\
220 [id] = {\
221 AUX_REG_LIST(id)\
222 }
223
224 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
225 aux_regs(0),
226 aux_regs(1),
227 aux_regs(2),
228 aux_regs(3),
229 aux_regs(4),
230 aux_regs(5)
231 };
232
233 #define hpd_regs(id)\
234 [id] = {\
235 HPD_REG_LIST(id)\
236 }
237
238 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
239 hpd_regs(0),
240 hpd_regs(1),
241 hpd_regs(2),
242 hpd_regs(3),
243 hpd_regs(4),
244 hpd_regs(5)
245 };
246
247
248 #define link_regs(id)\
249 [id] = {\
250 LE_DCE110_REG_LIST(id)\
251 }
252
253 static const struct dce110_link_enc_registers link_enc_regs[] = {
254 link_regs(0),
255 link_regs(1),
256 link_regs(2),
257 link_regs(3),
258 link_regs(4),
259 link_regs(5),
260 link_regs(6),
261 };
262
263 #define stream_enc_regs(id)\
264 [id] = {\
265 SE_COMMON_REG_LIST(id),\
266 .TMDS_CNTL = 0,\
267 }
268
269 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
270 stream_enc_regs(0),
271 stream_enc_regs(1),
272 stream_enc_regs(2)
273 };
274
275 static const struct dce_stream_encoder_shift se_shift = {
276 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
277 };
278
279 static const struct dce_stream_encoder_mask se_mask = {
280 SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
281 };
282
283 static const struct dce110_aux_registers_shift aux_shift = {
284 DCE_AUX_MASK_SH_LIST(__SHIFT)
285 };
286
287 static const struct dce110_aux_registers_mask aux_mask = {
288 DCE_AUX_MASK_SH_LIST(_MASK)
289 };
290
291 #define opp_regs(id)\
292 [id] = {\
293 OPP_DCE_110_REG_LIST(id),\
294 }
295
296 static const struct dce_opp_registers opp_regs[] = {
297 opp_regs(0),
298 opp_regs(1),
299 opp_regs(2),
300 opp_regs(3),
301 opp_regs(4),
302 opp_regs(5)
303 };
304
305 static const struct dce_opp_shift opp_shift = {
306 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
307 };
308
309 static const struct dce_opp_mask opp_mask = {
310 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
311 };
312
313 #define aux_engine_regs(id)\
314 [id] = {\
315 AUX_COMMON_REG_LIST(id), \
316 .AUX_RESET_MASK = 0 \
317 }
318
319 static const struct dce110_aux_registers aux_engine_regs[] = {
320 aux_engine_regs(0),
321 aux_engine_regs(1),
322 aux_engine_regs(2),
323 aux_engine_regs(3),
324 aux_engine_regs(4),
325 aux_engine_regs(5)
326 };
327
328 #define audio_regs(id)\
329 [id] = {\
330 AUD_COMMON_REG_LIST(id)\
331 }
332
333 static const struct dce_audio_registers audio_regs[] = {
334 audio_regs(0),
335 audio_regs(1),
336 audio_regs(2),
337 audio_regs(3),
338 audio_regs(4),
339 audio_regs(5),
340 audio_regs(6),
341 };
342
343 static const struct dce_audio_shift audio_shift = {
344 AUD_COMMON_MASK_SH_LIST(__SHIFT)
345 };
346
347 static const struct dce_audio_mask audio_mask = {
348 AUD_COMMON_MASK_SH_LIST(_MASK)
349 };
350
351 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
352
353
354 #define clk_src_regs(id)\
355 [id] = {\
356 CS_COMMON_REG_LIST_DCE_100_110(id),\
357 }
358
359 static const struct dce110_clk_src_regs clk_src_regs[] = {
360 clk_src_regs(0),
361 clk_src_regs(1),
362 clk_src_regs(2)
363 };
364
365 static const struct dce110_clk_src_shift cs_shift = {
366 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
367 };
368
369 static const struct dce110_clk_src_mask cs_mask = {
370 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
371 };
372
373 static const struct bios_registers bios_regs = {
374 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
375 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
376 };
377
378 static const struct resource_caps carrizo_resource_cap = {
379 .num_timing_generator = 3,
380 .num_video_plane = 1,
381 .num_audio = 3,
382 .num_stream_encoder = 3,
383 .num_pll = 2,
384 .num_ddc = 3,
385 };
386
387 static const struct resource_caps stoney_resource_cap = {
388 .num_timing_generator = 2,
389 .num_video_plane = 1,
390 .num_audio = 3,
391 .num_stream_encoder = 3,
392 .num_pll = 2,
393 .num_ddc = 3,
394 };
395
396 static const struct dc_plane_cap plane_cap = {
397 .type = DC_PLANE_TYPE_DCE_RGB,
398 .blends_with_below = true,
399 .blends_with_above = true,
400 .per_pixel_alpha = 1,
401
402 .pixel_format_support = {
403 .argb8888 = true,
404 .nv12 = false,
405 .fp16 = false
406 },
407
408 .max_upscale_factor = {
409 .argb8888 = 16000,
410 .nv12 = 1,
411 .fp16 = 1
412 },
413
414 .max_downscale_factor = {
415 .argb8888 = 250,
416 .nv12 = 1,
417 .fp16 = 1
418 }
419 };
420
421 static const struct dc_plane_cap underlay_plane_cap = {
422 .type = DC_PLANE_TYPE_DCE_UNDERLAY,
423 .blends_with_above = true,
424 .per_pixel_alpha = 1,
425
426 .pixel_format_support = {
427 .argb8888 = false,
428 .nv12 = true,
429 .fp16 = false
430 },
431
432 .max_upscale_factor = {
433 .argb8888 = 1,
434 .nv12 = 16000,
435 .fp16 = 1
436 },
437
438 .max_downscale_factor = {
439 .argb8888 = 1,
440 .nv12 = 250,
441 .fp16 = 1
442 }
443 };
444
445 #define CTX ctx
446 #define REG(reg) mm ## reg
447
448 #ifndef mmCC_DC_HDMI_STRAPS
449 #define mmCC_DC_HDMI_STRAPS 0x4819
450 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
451 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
452 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
453 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
454 #endif
455
map_transmitter_id_to_phy_instance(enum transmitter transmitter)456 static int map_transmitter_id_to_phy_instance(
457 enum transmitter transmitter)
458 {
459 switch (transmitter) {
460 case TRANSMITTER_UNIPHY_A:
461 return 0;
462 break;
463 case TRANSMITTER_UNIPHY_B:
464 return 1;
465 break;
466 case TRANSMITTER_UNIPHY_C:
467 return 2;
468 break;
469 case TRANSMITTER_UNIPHY_D:
470 return 3;
471 break;
472 case TRANSMITTER_UNIPHY_E:
473 return 4;
474 break;
475 case TRANSMITTER_UNIPHY_F:
476 return 5;
477 break;
478 case TRANSMITTER_UNIPHY_G:
479 return 6;
480 break;
481 default:
482 ASSERT(0);
483 return 0;
484 }
485 }
486
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)487 static void read_dce_straps(
488 struct dc_context *ctx,
489 struct resource_straps *straps)
490 {
491 REG_GET_2(CC_DC_HDMI_STRAPS,
492 HDMI_DISABLE, &straps->hdmi_disable,
493 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
494
495 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
496 }
497
create_audio(struct dc_context * ctx,unsigned int inst)498 static struct audio *create_audio(
499 struct dc_context *ctx, unsigned int inst)
500 {
501 return dce_audio_create(ctx, inst,
502 &audio_regs[inst], &audio_shift, &audio_mask);
503 }
504
dce110_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)505 static struct timing_generator *dce110_timing_generator_create(
506 struct dc_context *ctx,
507 uint32_t instance,
508 const struct dce110_timing_generator_offsets *offsets)
509 {
510 struct dce110_timing_generator *tg110 =
511 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
512
513 if (!tg110)
514 return NULL;
515
516 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
517 return &tg110->base;
518 }
519
dce110_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)520 static struct stream_encoder *dce110_stream_encoder_create(
521 enum engine_id eng_id,
522 struct dc_context *ctx)
523 {
524 struct dce110_stream_encoder *enc110 =
525 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
526
527 if (!enc110)
528 return NULL;
529
530 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
531 &stream_enc_regs[eng_id],
532 &se_shift, &se_mask);
533 return &enc110->base;
534 }
535
536 #define SRII(reg_name, block, id)\
537 .reg_name[id] = mm ## block ## id ## _ ## reg_name
538
539 static const struct dce_hwseq_registers hwseq_stoney_reg = {
540 HWSEQ_ST_REG_LIST()
541 };
542
543 static const struct dce_hwseq_registers hwseq_cz_reg = {
544 HWSEQ_CZ_REG_LIST()
545 };
546
547 static const struct dce_hwseq_shift hwseq_shift = {
548 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
549 };
550
551 static const struct dce_hwseq_mask hwseq_mask = {
552 HWSEQ_DCE11_MASK_SH_LIST(_MASK),
553 };
554
dce110_hwseq_create(struct dc_context * ctx)555 static struct dce_hwseq *dce110_hwseq_create(
556 struct dc_context *ctx)
557 {
558 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
559
560 if (hws) {
561 hws->ctx = ctx;
562 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
563 &hwseq_stoney_reg : &hwseq_cz_reg;
564 hws->shifts = &hwseq_shift;
565 hws->masks = &hwseq_mask;
566 hws->wa.blnd_crtc_trigger = true;
567 }
568 return hws;
569 }
570
571 static const struct resource_create_funcs res_create_funcs = {
572 .read_dce_straps = read_dce_straps,
573 .create_audio = create_audio,
574 .create_stream_encoder = dce110_stream_encoder_create,
575 .create_hwseq = dce110_hwseq_create,
576 };
577
578 #define mi_inst_regs(id) { \
579 MI_DCE11_REG_LIST(id), \
580 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
581 }
582 static const struct dce_mem_input_registers mi_regs[] = {
583 mi_inst_regs(0),
584 mi_inst_regs(1),
585 mi_inst_regs(2),
586 };
587
588 static const struct dce_mem_input_shift mi_shifts = {
589 MI_DCE11_MASK_SH_LIST(__SHIFT),
590 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
591 };
592
593 static const struct dce_mem_input_mask mi_masks = {
594 MI_DCE11_MASK_SH_LIST(_MASK),
595 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
596 };
597
598
dce110_mem_input_create(struct dc_context * ctx,uint32_t inst)599 static struct mem_input *dce110_mem_input_create(
600 struct dc_context *ctx,
601 uint32_t inst)
602 {
603 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
604 GFP_KERNEL);
605
606 if (!dce_mi) {
607 BREAK_TO_DEBUGGER();
608 return NULL;
609 }
610
611 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
612 dce_mi->wa.single_head_rdreq_dmif_limit = 3;
613 return &dce_mi->base;
614 }
615
dce110_transform_destroy(struct transform ** xfm)616 static void dce110_transform_destroy(struct transform **xfm)
617 {
618 kfree(TO_DCE_TRANSFORM(*xfm));
619 *xfm = NULL;
620 }
621
dce110_transform_create(struct dc_context * ctx,uint32_t inst)622 static struct transform *dce110_transform_create(
623 struct dc_context *ctx,
624 uint32_t inst)
625 {
626 struct dce_transform *transform =
627 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
628
629 if (!transform)
630 return NULL;
631
632 dce_transform_construct(transform, ctx, inst,
633 &xfm_regs[inst], &xfm_shift, &xfm_mask);
634 return &transform->base;
635 }
636
dce110_ipp_create(struct dc_context * ctx,uint32_t inst)637 static struct input_pixel_processor *dce110_ipp_create(
638 struct dc_context *ctx, uint32_t inst)
639 {
640 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
641
642 if (!ipp) {
643 BREAK_TO_DEBUGGER();
644 return NULL;
645 }
646
647 dce_ipp_construct(ipp, ctx, inst,
648 &ipp_regs[inst], &ipp_shift, &ipp_mask);
649 return &ipp->base;
650 }
651
652 static const struct encoder_feature_support link_enc_feature = {
653 .max_hdmi_deep_color = COLOR_DEPTH_121212,
654 .max_hdmi_pixel_clock = 300000,
655 .flags.bits.IS_HBR2_CAPABLE = true,
656 .flags.bits.IS_TPS3_CAPABLE = true
657 };
658
dce110_link_encoder_create(const struct encoder_init_data * enc_init_data)659 static struct link_encoder *dce110_link_encoder_create(
660 const struct encoder_init_data *enc_init_data)
661 {
662 struct dce110_link_encoder *enc110 =
663 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
664 int link_regs_id;
665
666 if (!enc110)
667 return NULL;
668
669 link_regs_id =
670 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
671
672 dce110_link_encoder_construct(enc110,
673 enc_init_data,
674 &link_enc_feature,
675 &link_enc_regs[link_regs_id],
676 &link_enc_aux_regs[enc_init_data->channel - 1],
677 &link_enc_hpd_regs[enc_init_data->hpd_source]);
678 return &enc110->base;
679 }
680
dce110_opp_create(struct dc_context * ctx,uint32_t inst)681 static struct output_pixel_processor *dce110_opp_create(
682 struct dc_context *ctx,
683 uint32_t inst)
684 {
685 struct dce110_opp *opp =
686 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
687
688 if (!opp)
689 return NULL;
690
691 dce110_opp_construct(opp,
692 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
693 return &opp->base;
694 }
695
dce110_aux_engine_create(struct dc_context * ctx,uint32_t inst)696 struct dce_aux *dce110_aux_engine_create(
697 struct dc_context *ctx,
698 uint32_t inst)
699 {
700 struct aux_engine_dce110 *aux_engine =
701 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
702
703 if (!aux_engine)
704 return NULL;
705
706 dce110_aux_engine_construct(aux_engine, ctx, inst,
707 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
708 &aux_engine_regs[inst],
709 &aux_mask,
710 &aux_shift,
711 ctx->dc->caps.extended_aux_timeout_support);
712
713 return &aux_engine->base;
714 }
715 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
716
717 static const struct dce_i2c_registers i2c_hw_regs[] = {
718 i2c_inst_regs(1),
719 i2c_inst_regs(2),
720 i2c_inst_regs(3),
721 i2c_inst_regs(4),
722 i2c_inst_regs(5),
723 i2c_inst_regs(6),
724 };
725
726 static const struct dce_i2c_shift i2c_shifts = {
727 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
728 };
729
730 static const struct dce_i2c_mask i2c_masks = {
731 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
732 };
733
dce110_i2c_hw_create(struct dc_context * ctx,uint32_t inst)734 struct dce_i2c_hw *dce110_i2c_hw_create(
735 struct dc_context *ctx,
736 uint32_t inst)
737 {
738 struct dce_i2c_hw *dce_i2c_hw =
739 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
740
741 if (!dce_i2c_hw)
742 return NULL;
743
744 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
745 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
746
747 return dce_i2c_hw;
748 }
dce110_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)749 struct clock_source *dce110_clock_source_create(
750 struct dc_context *ctx,
751 struct dc_bios *bios,
752 enum clock_source_id id,
753 const struct dce110_clk_src_regs *regs,
754 bool dp_clk_src)
755 {
756 struct dce110_clk_src *clk_src =
757 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
758
759 if (!clk_src)
760 return NULL;
761
762 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
763 regs, &cs_shift, &cs_mask)) {
764 clk_src->base.dp_clk_src = dp_clk_src;
765 return &clk_src->base;
766 }
767
768 kfree(clk_src);
769 BREAK_TO_DEBUGGER();
770 return NULL;
771 }
772
dce110_clock_source_destroy(struct clock_source ** clk_src)773 void dce110_clock_source_destroy(struct clock_source **clk_src)
774 {
775 struct dce110_clk_src *dce110_clk_src;
776
777 if (!clk_src)
778 return;
779
780 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src);
781
782 kfree(dce110_clk_src->dp_ss_params);
783 kfree(dce110_clk_src->hdmi_ss_params);
784 kfree(dce110_clk_src->dvi_ss_params);
785
786 kfree(dce110_clk_src);
787 *clk_src = NULL;
788 }
789
dce110_resource_destruct(struct dce110_resource_pool * pool)790 static void dce110_resource_destruct(struct dce110_resource_pool *pool)
791 {
792 unsigned int i;
793
794 for (i = 0; i < pool->base.pipe_count; i++) {
795 if (pool->base.opps[i] != NULL)
796 dce110_opp_destroy(&pool->base.opps[i]);
797
798 if (pool->base.transforms[i] != NULL)
799 dce110_transform_destroy(&pool->base.transforms[i]);
800
801 if (pool->base.ipps[i] != NULL)
802 dce_ipp_destroy(&pool->base.ipps[i]);
803
804 if (pool->base.mis[i] != NULL) {
805 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
806 pool->base.mis[i] = NULL;
807 }
808
809 if (pool->base.timing_generators[i] != NULL) {
810 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
811 pool->base.timing_generators[i] = NULL;
812 }
813 }
814
815 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
816 if (pool->base.engines[i] != NULL)
817 dce110_engine_destroy(&pool->base.engines[i]);
818 if (pool->base.hw_i2cs[i] != NULL) {
819 kfree(pool->base.hw_i2cs[i]);
820 pool->base.hw_i2cs[i] = NULL;
821 }
822 if (pool->base.sw_i2cs[i] != NULL) {
823 kfree(pool->base.sw_i2cs[i]);
824 pool->base.sw_i2cs[i] = NULL;
825 }
826 }
827
828 for (i = 0; i < pool->base.stream_enc_count; i++) {
829 if (pool->base.stream_enc[i] != NULL)
830 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
831 }
832
833 for (i = 0; i < pool->base.clk_src_count; i++) {
834 if (pool->base.clock_sources[i] != NULL) {
835 dce110_clock_source_destroy(&pool->base.clock_sources[i]);
836 }
837 }
838
839 if (pool->base.dp_clock_source != NULL)
840 dce110_clock_source_destroy(&pool->base.dp_clock_source);
841
842 for (i = 0; i < pool->base.audio_count; i++) {
843 if (pool->base.audios[i] != NULL) {
844 dce_aud_destroy(&pool->base.audios[i]);
845 }
846 }
847
848 if (pool->base.abm != NULL)
849 dce_abm_destroy(&pool->base.abm);
850
851 if (pool->base.dmcu != NULL)
852 dce_dmcu_destroy(&pool->base.dmcu);
853
854 if (pool->base.irqs != NULL) {
855 dal_irq_service_destroy(&pool->base.irqs);
856 }
857 }
858
859
get_pixel_clock_parameters(const struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)860 static void get_pixel_clock_parameters(
861 const struct pipe_ctx *pipe_ctx,
862 struct pixel_clk_params *pixel_clk_params)
863 {
864 const struct dc_stream_state *stream = pipe_ctx->stream;
865
866 /*TODO: is this halved for YCbCr 420? in that case we might want to move
867 * the pixel clock normalization for hdmi up to here instead of doing it
868 * in pll_adjust_pix_clk
869 */
870 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
871 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
872 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
873 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
874 /* TODO: un-hardcode*/
875 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
876 LINK_RATE_REF_FREQ_IN_KHZ;
877 pixel_clk_params->flags.ENABLE_SS = 0;
878 pixel_clk_params->color_depth =
879 stream->timing.display_color_depth;
880 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
881 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
882 PIXEL_ENCODING_YCBCR420);
883 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
884 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
885 pixel_clk_params->color_depth = COLOR_DEPTH_888;
886 }
887 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
888 pixel_clk_params->requested_pix_clk_100hz = pixel_clk_params->requested_pix_clk_100hz / 2;
889 }
890 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
891 pixel_clk_params->requested_pix_clk_100hz *= 2;
892
893 }
894
dce110_resource_build_pipe_hw_param(struct pipe_ctx * pipe_ctx)895 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
896 {
897 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
898 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
899 pipe_ctx->clock_source,
900 &pipe_ctx->stream_res.pix_clk_params,
901 &pipe_ctx->pll_settings);
902 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
903 &pipe_ctx->stream->bit_depth_params);
904 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
905 }
906
is_surface_pixel_format_supported(struct pipe_ctx * pipe_ctx,unsigned int underlay_idx)907 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
908 {
909 if (pipe_ctx->pipe_idx != underlay_idx)
910 return true;
911 if (!pipe_ctx->plane_state)
912 return false;
913 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
914 return false;
915 return true;
916 }
917
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)918 static enum dc_status build_mapped_resource(
919 const struct dc *dc,
920 struct dc_state *context,
921 struct dc_stream_state *stream)
922 {
923 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
924
925 if (!pipe_ctx)
926 return DC_ERROR_UNEXPECTED;
927
928 if (!is_surface_pixel_format_supported(pipe_ctx,
929 dc->res_pool->underlay_pipe_index))
930 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
931
932 dce110_resource_build_pipe_hw_param(pipe_ctx);
933
934 /* TODO: validate audio ASIC caps, encoder */
935
936 resource_build_info_frame(pipe_ctx);
937
938 return DC_OK;
939 }
940
dce110_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)941 static bool dce110_validate_bandwidth(
942 struct dc *dc,
943 struct dc_state *context,
944 bool fast_validate)
945 {
946 bool result = false;
947
948 DC_LOG_BANDWIDTH_CALCS(
949 "%s: start",
950 __func__);
951
952 if (bw_calcs(
953 dc->ctx,
954 dc->bw_dceip,
955 dc->bw_vbios,
956 context->res_ctx.pipe_ctx,
957 dc->res_pool->pipe_count,
958 &context->bw_ctx.bw.dce))
959 result = true;
960
961 if (!result)
962 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n",
963 __func__,
964 context->streams[0]->timing.h_addressable,
965 context->streams[0]->timing.v_addressable,
966 context->streams[0]->timing.pix_clk_100hz / 10);
967
968 if (memcmp(&dc->current_state->bw_ctx.bw.dce,
969 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
970
971 DC_LOG_BANDWIDTH_CALCS(
972 "%s: finish,\n"
973 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
974 "stutMark_b: %d stutMark_a: %d\n"
975 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
976 "stutMark_b: %d stutMark_a: %d\n"
977 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
978 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
979 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
980 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
981 ,
982 __func__,
983 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
984 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
985 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
986 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
987 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
988 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
989 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
990 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
991 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
992 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
993 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
994 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
995 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
996 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
997 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
998 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
999 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
1000 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
1001 context->bw_ctx.bw.dce.stutter_mode_enable,
1002 context->bw_ctx.bw.dce.cpuc_state_change_enable,
1003 context->bw_ctx.bw.dce.cpup_state_change_enable,
1004 context->bw_ctx.bw.dce.nbp_state_change_enable,
1005 context->bw_ctx.bw.dce.all_displays_in_sync,
1006 context->bw_ctx.bw.dce.dispclk_khz,
1007 context->bw_ctx.bw.dce.sclk_khz,
1008 context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
1009 context->bw_ctx.bw.dce.yclk_khz,
1010 context->bw_ctx.bw.dce.blackout_recovery_time_us);
1011 }
1012 return result;
1013 }
1014
dce110_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)1015 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
1016 struct dc_caps *caps)
1017 {
1018 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
1019 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
1020 return DC_FAIL_SURFACE_VALIDATE;
1021
1022 return DC_OK;
1023 }
1024
dce110_validate_surface_sets(struct dc_state * context)1025 static bool dce110_validate_surface_sets(
1026 struct dc_state *context)
1027 {
1028 int i, j;
1029
1030 for (i = 0; i < context->stream_count; i++) {
1031 if (context->stream_status[i].plane_count == 0)
1032 continue;
1033
1034 if (context->stream_status[i].plane_count > 2)
1035 return false;
1036
1037 for (j = 0; j < context->stream_status[i].plane_count; j++) {
1038 struct dc_plane_state *plane =
1039 context->stream_status[i].plane_states[j];
1040
1041 /* underlay validation */
1042 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1043
1044 if ((plane->src_rect.width > 1920 ||
1045 plane->src_rect.height > 1080))
1046 return false;
1047
1048 /* we don't have the logic to support underlay
1049 * only yet so block the use case where we get
1050 * NV12 plane as top layer
1051 */
1052 if (j == 0)
1053 return false;
1054
1055 /* irrespective of plane format,
1056 * stream should be RGB encoded
1057 */
1058 if (context->streams[i]->timing.pixel_encoding
1059 != PIXEL_ENCODING_RGB)
1060 return false;
1061
1062 }
1063
1064 }
1065 }
1066
1067 return true;
1068 }
1069
dce110_validate_global(struct dc * dc,struct dc_state * context)1070 enum dc_status dce110_validate_global(
1071 struct dc *dc,
1072 struct dc_state *context)
1073 {
1074 if (!dce110_validate_surface_sets(context))
1075 return DC_FAIL_SURFACE_VALIDATE;
1076
1077 return DC_OK;
1078 }
1079
dce110_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1080 static enum dc_status dce110_add_stream_to_ctx(
1081 struct dc *dc,
1082 struct dc_state *new_ctx,
1083 struct dc_stream_state *dc_stream)
1084 {
1085 enum dc_status result = DC_ERROR_UNEXPECTED;
1086
1087 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1088
1089 if (result == DC_OK)
1090 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
1091
1092
1093 if (result == DC_OK)
1094 result = build_mapped_resource(dc, new_ctx, dc_stream);
1095
1096 return result;
1097 }
1098
dce110_acquire_underlay(struct dc_state * context,const struct resource_pool * pool,struct dc_stream_state * stream)1099 static struct pipe_ctx *dce110_acquire_underlay(
1100 struct dc_state *context,
1101 const struct resource_pool *pool,
1102 struct dc_stream_state *stream)
1103 {
1104 struct dc *dc = stream->ctx->dc;
1105 struct dce_hwseq *hws = dc->hwseq;
1106 struct resource_context *res_ctx = &context->res_ctx;
1107 unsigned int underlay_idx = pool->underlay_pipe_index;
1108 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
1109
1110 if (res_ctx->pipe_ctx[underlay_idx].stream)
1111 return NULL;
1112
1113 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
1114 pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
1115 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
1116 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
1117 pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
1118 pipe_ctx->pipe_idx = underlay_idx;
1119
1120 pipe_ctx->stream = stream;
1121
1122 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {
1123 struct tg_color black_color = {0};
1124 struct dc_bios *dcb = dc->ctx->dc_bios;
1125
1126 hws->funcs.enable_display_power_gating(
1127 dc,
1128 pipe_ctx->stream_res.tg->inst,
1129 dcb, PIPE_GATING_CONTROL_DISABLE);
1130
1131 /*
1132 * This is for powering on underlay, so crtc does not
1133 * need to be enabled
1134 */
1135
1136 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
1137 &stream->timing,
1138 0,
1139 0,
1140 0,
1141 0,
1142 pipe_ctx->stream->signal,
1143 false);
1144
1145 pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
1146 pipe_ctx->stream_res.tg,
1147 true,
1148 &stream->timing);
1149
1150 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
1151 stream->timing.h_total,
1152 stream->timing.v_total,
1153 stream->timing.pix_clk_100hz / 10,
1154 context->stream_count);
1155
1156 color_space_to_black_color(dc,
1157 COLOR_SPACE_YCBCR601, &black_color);
1158 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1159 pipe_ctx->stream_res.tg,
1160 &black_color);
1161 }
1162
1163 return pipe_ctx;
1164 }
1165
dce110_destroy_resource_pool(struct resource_pool ** pool)1166 static void dce110_destroy_resource_pool(struct resource_pool **pool)
1167 {
1168 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1169
1170 dce110_resource_destruct(dce110_pool);
1171 kfree(dce110_pool);
1172 *pool = NULL;
1173 }
1174
dce110_find_first_free_match_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1175 struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link(
1176 struct resource_context *res_ctx,
1177 const struct resource_pool *pool,
1178 struct dc_stream_state *stream)
1179 {
1180 int i;
1181 int j = -1;
1182 struct dc_link *link = stream->link;
1183
1184 for (i = 0; i < pool->stream_enc_count; i++) {
1185 if (!res_ctx->is_stream_enc_acquired[i] &&
1186 pool->stream_enc[i]) {
1187 /* Store first available for MST second display
1188 * in daisy chain use case
1189 */
1190 j = i;
1191 if (pool->stream_enc[i]->id ==
1192 link->link_enc->preferred_engine)
1193 return pool->stream_enc[i];
1194 }
1195 }
1196
1197 /*
1198 * For CZ and later, we can allow DIG FE and BE to differ for all display types
1199 */
1200
1201 if (j >= 0)
1202 return pool->stream_enc[j];
1203
1204 return NULL;
1205 }
1206
1207
1208 static const struct resource_funcs dce110_res_pool_funcs = {
1209 .destroy = dce110_destroy_resource_pool,
1210 .link_enc_create = dce110_link_encoder_create,
1211 .validate_bandwidth = dce110_validate_bandwidth,
1212 .validate_plane = dce110_validate_plane,
1213 .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1214 .add_stream_to_ctx = dce110_add_stream_to_ctx,
1215 .validate_global = dce110_validate_global,
1216 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1217 };
1218
underlay_create(struct dc_context * ctx,struct resource_pool * pool)1219 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
1220 {
1221 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv),
1222 GFP_KERNEL);
1223 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv),
1224 GFP_KERNEL);
1225 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv),
1226 GFP_KERNEL);
1227 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv),
1228 GFP_KERNEL);
1229
1230 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) {
1231 kfree(dce110_tgv);
1232 kfree(dce110_xfmv);
1233 kfree(dce110_miv);
1234 kfree(dce110_oppv);
1235 return false;
1236 }
1237
1238 dce110_opp_v_construct(dce110_oppv, ctx);
1239
1240 dce110_timing_generator_v_construct(dce110_tgv, ctx);
1241 dce110_mem_input_v_construct(dce110_miv, ctx);
1242 dce110_transform_v_construct(dce110_xfmv, ctx);
1243
1244 pool->opps[pool->pipe_count] = &dce110_oppv->base;
1245 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
1246 pool->mis[pool->pipe_count] = &dce110_miv->base;
1247 pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
1248 pool->pipe_count++;
1249
1250 /* update the public caps to indicate an underlay is available */
1251 ctx->dc->caps.max_slave_planes = 1;
1252 ctx->dc->caps.max_slave_planes = 1;
1253
1254 return true;
1255 }
1256
bw_calcs_data_update_from_pplib(struct dc * dc)1257 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1258 {
1259 struct dm_pp_clock_levels clks = {0};
1260
1261 /*do system clock*/
1262 dm_pp_get_clock_levels_by_type(
1263 dc->ctx,
1264 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1265 &clks);
1266 /* convert all the clock fro kHz to fix point mHz */
1267 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1268 clks.clocks_in_khz[clks.num_levels-1], 1000);
1269 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1270 clks.clocks_in_khz[clks.num_levels/8], 1000);
1271 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1272 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1273 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1274 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1275 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1276 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1277 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1278 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1279 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1280 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1281 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1282 clks.clocks_in_khz[0], 1000);
1283 dc->sclk_lvls = clks;
1284
1285 /*do display clock*/
1286 dm_pp_get_clock_levels_by_type(
1287 dc->ctx,
1288 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1289 &clks);
1290 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
1291 clks.clocks_in_khz[clks.num_levels-1], 1000);
1292 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed(
1293 clks.clocks_in_khz[clks.num_levels>>1], 1000);
1294 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed(
1295 clks.clocks_in_khz[0], 1000);
1296
1297 /*do memory clock*/
1298 dm_pp_get_clock_levels_by_type(
1299 dc->ctx,
1300 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1301 &clks);
1302
1303 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1304 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
1305 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1306 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ,
1307 1000);
1308 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1309 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ,
1310 1000);
1311 }
1312
dce110_resource_cap(struct hw_asic_id * asic_id)1313 const struct resource_caps *dce110_resource_cap(
1314 struct hw_asic_id *asic_id)
1315 {
1316 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
1317 return &stoney_resource_cap;
1318 else
1319 return &carrizo_resource_cap;
1320 }
1321
dce110_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool,struct hw_asic_id asic_id)1322 static bool dce110_resource_construct(
1323 uint8_t num_virtual_links,
1324 struct dc *dc,
1325 struct dce110_resource_pool *pool,
1326 struct hw_asic_id asic_id)
1327 {
1328 unsigned int i;
1329 struct dc_context *ctx = dc->ctx;
1330 struct dc_bios *bp;
1331
1332 ctx->dc_bios->regs = &bios_regs;
1333
1334 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
1335 pool->base.funcs = &dce110_res_pool_funcs;
1336
1337 /*************************************************
1338 * Resource + asic cap harcoding *
1339 *************************************************/
1340
1341 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1342 pool->base.underlay_pipe_index = pool->base.pipe_count;
1343 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1344 dc->caps.max_downscale_ratio = 150;
1345 dc->caps.i2c_speed_in_khz = 100;
1346 dc->caps.max_cursor_size = 128;
1347 dc->caps.is_apu = true;
1348 dc->caps.extended_aux_timeout_support = false;
1349
1350 /*************************************************
1351 * Create resources *
1352 *************************************************/
1353
1354 bp = ctx->dc_bios;
1355
1356 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1357 pool->base.dp_clock_source =
1358 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1359
1360 pool->base.clock_sources[0] =
1361 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,
1362 &clk_src_regs[0], false);
1363 pool->base.clock_sources[1] =
1364 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1,
1365 &clk_src_regs[1], false);
1366
1367 pool->base.clk_src_count = 2;
1368
1369 /* TODO: find out if CZ support 3 PLLs */
1370 }
1371
1372 if (pool->base.dp_clock_source == NULL) {
1373 dm_error("DC: failed to create dp clock source!\n");
1374 BREAK_TO_DEBUGGER();
1375 goto res_create_fail;
1376 }
1377
1378 for (i = 0; i < pool->base.clk_src_count; i++) {
1379 if (pool->base.clock_sources[i] == NULL) {
1380 dm_error("DC: failed to create clock sources!\n");
1381 BREAK_TO_DEBUGGER();
1382 goto res_create_fail;
1383 }
1384 }
1385
1386 pool->base.dmcu = dce_dmcu_create(ctx,
1387 &dmcu_regs,
1388 &dmcu_shift,
1389 &dmcu_mask);
1390 if (pool->base.dmcu == NULL) {
1391 dm_error("DC: failed to create dmcu!\n");
1392 BREAK_TO_DEBUGGER();
1393 goto res_create_fail;
1394 }
1395
1396 pool->base.abm = dce_abm_create(ctx,
1397 &abm_regs,
1398 &abm_shift,
1399 &abm_mask);
1400 if (pool->base.abm == NULL) {
1401 dm_error("DC: failed to create abm!\n");
1402 BREAK_TO_DEBUGGER();
1403 goto res_create_fail;
1404 }
1405
1406 {
1407 struct irq_service_init_data init_data;
1408 init_data.ctx = dc->ctx;
1409 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1410 if (!pool->base.irqs)
1411 goto res_create_fail;
1412 }
1413
1414 for (i = 0; i < pool->base.pipe_count; i++) {
1415 pool->base.timing_generators[i] = dce110_timing_generator_create(
1416 ctx, i, &dce110_tg_offsets[i]);
1417 if (pool->base.timing_generators[i] == NULL) {
1418 BREAK_TO_DEBUGGER();
1419 dm_error("DC: failed to create tg!\n");
1420 goto res_create_fail;
1421 }
1422
1423 pool->base.mis[i] = dce110_mem_input_create(ctx, i);
1424 if (pool->base.mis[i] == NULL) {
1425 BREAK_TO_DEBUGGER();
1426 dm_error(
1427 "DC: failed to create memory input!\n");
1428 goto res_create_fail;
1429 }
1430
1431 pool->base.ipps[i] = dce110_ipp_create(ctx, i);
1432 if (pool->base.ipps[i] == NULL) {
1433 BREAK_TO_DEBUGGER();
1434 dm_error(
1435 "DC: failed to create input pixel processor!\n");
1436 goto res_create_fail;
1437 }
1438
1439 pool->base.transforms[i] = dce110_transform_create(ctx, i);
1440 if (pool->base.transforms[i] == NULL) {
1441 BREAK_TO_DEBUGGER();
1442 dm_error(
1443 "DC: failed to create transform!\n");
1444 goto res_create_fail;
1445 }
1446
1447 pool->base.opps[i] = dce110_opp_create(ctx, i);
1448 if (pool->base.opps[i] == NULL) {
1449 BREAK_TO_DEBUGGER();
1450 dm_error(
1451 "DC: failed to create output pixel processor!\n");
1452 goto res_create_fail;
1453 }
1454 }
1455
1456 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1457 pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
1458 if (pool->base.engines[i] == NULL) {
1459 BREAK_TO_DEBUGGER();
1460 dm_error(
1461 "DC:failed to create aux engine!!\n");
1462 goto res_create_fail;
1463 }
1464 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i);
1465 if (pool->base.hw_i2cs[i] == NULL) {
1466 BREAK_TO_DEBUGGER();
1467 dm_error(
1468 "DC:failed to create i2c engine!!\n");
1469 goto res_create_fail;
1470 }
1471 pool->base.sw_i2cs[i] = NULL;
1472 }
1473
1474 if (dc->config.fbc_support)
1475 dc->fbc_compressor = dce110_compressor_create(ctx);
1476
1477 if (!underlay_create(ctx, &pool->base))
1478 goto res_create_fail;
1479
1480 if (!resource_construct(num_virtual_links, dc, &pool->base,
1481 &res_create_funcs))
1482 goto res_create_fail;
1483
1484 /* Create hardware sequencer */
1485 dce110_hw_sequencer_construct(dc);
1486
1487 dc->caps.max_planes = pool->base.pipe_count;
1488
1489 for (i = 0; i < pool->base.underlay_pipe_index; ++i)
1490 dc->caps.planes[i] = plane_cap;
1491
1492 dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;
1493
1494 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1495
1496 bw_calcs_data_update_from_pplib(dc);
1497
1498 return true;
1499
1500 res_create_fail:
1501 dce110_resource_destruct(pool);
1502 return false;
1503 }
1504
dce110_create_resource_pool(uint8_t num_virtual_links,struct dc * dc,struct hw_asic_id asic_id)1505 struct resource_pool *dce110_create_resource_pool(
1506 uint8_t num_virtual_links,
1507 struct dc *dc,
1508 struct hw_asic_id asic_id)
1509 {
1510 struct dce110_resource_pool *pool =
1511 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1512
1513 if (!pool)
1514 return NULL;
1515
1516 if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))
1517 return &pool->base;
1518
1519 kfree(pool);
1520 BREAK_TO_DEBUGGER();
1521 return NULL;
1522 }
1523