1 /* $NetBSD: amdgpu_dce100_resource.c,v 1.6 2021/12/19 12:22:49 riastradh Exp $ */
2
3 /*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce100_resource.c,v 1.6 2021/12/19 12:22:49 riastradh Exp $");
30
31 #include <linux/slab.h>
32
33 #include "dm_services.h"
34
35 #include "link_encoder.h"
36 #include "stream_encoder.h"
37
38 #include "resource.h"
39 #include "include/irq_service_interface.h"
40 #include "../virtual/virtual_stream_encoder.h"
41 #include "dce110/dce110_resource.h"
42 #include "dce110/dce110_timing_generator.h"
43 #include "irq/dce110/irq_service_dce110.h"
44 #include "dce/dce_link_encoder.h"
45 #include "dce/dce_stream_encoder.h"
46 #include "dce/dce_mem_input.h"
47 #include "dce/dce_ipp.h"
48 #include "dce/dce_transform.h"
49 #include "dce/dce_opp.h"
50 #include "dce/dce_clock_source.h"
51 #include "dce/dce_audio.h"
52 #include "dce/dce_hwseq.h"
53 #include "dce100/dce100_hw_sequencer.h"
54
55 #include "reg_helper.h"
56
57 #include "dce/dce_10_0_d.h"
58 #include "dce/dce_10_0_sh_mask.h"
59
60 #include "dce/dce_dmcu.h"
61 #include "dce/dce_aux.h"
62 #include "dce/dce_abm.h"
63 #include "dce/dce_i2c.h"
64
65 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
66 #include "gmc/gmc_8_2_d.h"
67 #include "gmc/gmc_8_2_sh_mask.h"
68 #endif
69
70 #ifndef mmDP_DPHY_INTERNAL_CTRL
71 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
73 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
74 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
75 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
76 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
77 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
78 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
79 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
80 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
81 #endif
82
83 #ifndef mmBIOS_SCRATCH_2
84 #define mmBIOS_SCRATCH_2 0x05CB
85 #define mmBIOS_SCRATCH_3 0x05CC
86 #define mmBIOS_SCRATCH_6 0x05CF
87 #endif
88
89 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
90 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
91 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
92 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
93 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
94 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
95 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
96 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
97 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
98 #endif
99
100 #ifndef mmDP_DPHY_FAST_TRAINING
101 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
102 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
103 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
104 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
105 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
106 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
107 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
108 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
109 #endif
110
111 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
112 {
113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
114 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
115 },
116 {
117 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
118 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
119 },
120 {
121 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
123 },
124 {
125 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
126 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
127 },
128 {
129 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
130 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
131 },
132 {
133 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
134 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
135 }
136 };
137
138 /* set register offset */
139 #define SR(reg_name)\
140 .reg_name = mm ## reg_name
141
142 /* set register offset with instance */
143 #define SRI(reg_name, block, id)\
144 .reg_name = mm ## block ## id ## _ ## reg_name
145
146 #define ipp_regs(id)\
147 [id] = {\
148 IPP_DCE100_REG_LIST_DCE_BASE(id)\
149 }
150
151 static const struct dce_ipp_registers ipp_regs[] = {
152 ipp_regs(0),
153 ipp_regs(1),
154 ipp_regs(2),
155 ipp_regs(3),
156 ipp_regs(4),
157 ipp_regs(5)
158 };
159
160 static const struct dce_ipp_shift ipp_shift = {
161 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
162 };
163
164 static const struct dce_ipp_mask ipp_mask = {
165 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
166 };
167
168 #define transform_regs(id)\
169 [id] = {\
170 XFM_COMMON_REG_LIST_DCE100(id)\
171 }
172
173 static const struct dce_transform_registers xfm_regs[] = {
174 transform_regs(0),
175 transform_regs(1),
176 transform_regs(2),
177 transform_regs(3),
178 transform_regs(4),
179 transform_regs(5)
180 };
181
182 static const struct dce_transform_shift xfm_shift = {
183 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
184 };
185
186 static const struct dce_transform_mask xfm_mask = {
187 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
188 };
189
190 #define aux_regs(id)\
191 [id] = {\
192 AUX_REG_LIST(id)\
193 }
194
195 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
196 aux_regs(0),
197 aux_regs(1),
198 aux_regs(2),
199 aux_regs(3),
200 aux_regs(4),
201 aux_regs(5)
202 };
203
204 #define hpd_regs(id)\
205 [id] = {\
206 HPD_REG_LIST(id)\
207 }
208
209 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
210 hpd_regs(0),
211 hpd_regs(1),
212 hpd_regs(2),
213 hpd_regs(3),
214 hpd_regs(4),
215 hpd_regs(5)
216 };
217
218 #define link_regs(id)\
219 [id] = {\
220 LE_DCE100_REG_LIST(id)\
221 }
222
223 static const struct dce110_link_enc_registers link_enc_regs[] = {
224 link_regs(0),
225 link_regs(1),
226 link_regs(2),
227 link_regs(3),
228 link_regs(4),
229 link_regs(5),
230 link_regs(6),
231 };
232
233 #define stream_enc_regs(id)\
234 [id] = {\
235 SE_COMMON_REG_LIST_DCE_BASE(id),\
236 .AFMT_CNTL = 0,\
237 }
238
239 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
240 stream_enc_regs(0),
241 stream_enc_regs(1),
242 stream_enc_regs(2),
243 stream_enc_regs(3),
244 stream_enc_regs(4),
245 stream_enc_regs(5),
246 stream_enc_regs(6)
247 };
248
249 static const struct dce_stream_encoder_shift se_shift = {
250 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
251 };
252
253 static const struct dce_stream_encoder_mask se_mask = {
254 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
255 };
256
257 #define opp_regs(id)\
258 [id] = {\
259 OPP_DCE_100_REG_LIST(id),\
260 }
261
262 static const struct dce_opp_registers opp_regs[] = {
263 opp_regs(0),
264 opp_regs(1),
265 opp_regs(2),
266 opp_regs(3),
267 opp_regs(4),
268 opp_regs(5)
269 };
270
271 static const struct dce_opp_shift opp_shift = {
272 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
273 };
274
275 static const struct dce_opp_mask opp_mask = {
276 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
277 };
278 #define aux_engine_regs(id)\
279 [id] = {\
280 AUX_COMMON_REG_LIST(id), \
281 .AUX_RESET_MASK = 0 \
282 }
283
284 static const struct dce110_aux_registers aux_engine_regs[] = {
285 aux_engine_regs(0),
286 aux_engine_regs(1),
287 aux_engine_regs(2),
288 aux_engine_regs(3),
289 aux_engine_regs(4),
290 aux_engine_regs(5)
291 };
292
293 #define audio_regs(id)\
294 [id] = {\
295 AUD_COMMON_REG_LIST(id)\
296 }
297
298 static const struct dce_audio_registers audio_regs[] = {
299 audio_regs(0),
300 audio_regs(1),
301 audio_regs(2),
302 audio_regs(3),
303 audio_regs(4),
304 audio_regs(5),
305 audio_regs(6),
306 };
307
308 static const struct dce_audio_shift audio_shift = {
309 AUD_COMMON_MASK_SH_LIST(__SHIFT)
310 };
311
312 static const struct dce_audio_mask audio_mask = {
313 AUD_COMMON_MASK_SH_LIST(_MASK)
314 };
315
316 #define clk_src_regs(id)\
317 [id] = {\
318 CS_COMMON_REG_LIST_DCE_100_110(id),\
319 }
320
321 static const struct dce110_clk_src_regs clk_src_regs[] = {
322 clk_src_regs(0),
323 clk_src_regs(1),
324 clk_src_regs(2)
325 };
326
327 static const struct dce110_clk_src_shift cs_shift = {
328 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
329 };
330
331 static const struct dce110_clk_src_mask cs_mask = {
332 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
333 };
334
335 static const struct dce_dmcu_registers dmcu_regs = {
336 DMCU_DCE110_COMMON_REG_LIST()
337 };
338
339 static const struct dce_dmcu_shift dmcu_shift = {
340 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
341 };
342
343 static const struct dce_dmcu_mask dmcu_mask = {
344 DMCU_MASK_SH_LIST_DCE110(_MASK)
345 };
346
347 static const struct dce_abm_registers abm_regs = {
348 ABM_DCE110_COMMON_REG_LIST()
349 };
350
351 static const struct dce_abm_shift abm_shift = {
352 ABM_MASK_SH_LIST_DCE110(__SHIFT)
353 };
354
355 static const struct dce_abm_mask abm_mask = {
356 ABM_MASK_SH_LIST_DCE110(_MASK)
357 };
358
359 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
360
361 static const struct bios_registers bios_regs = {
362 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
363 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
364 };
365
366 static const struct resource_caps res_cap = {
367 .num_timing_generator = 6,
368 .num_audio = 6,
369 .num_stream_encoder = 6,
370 .num_pll = 3,
371 .num_ddc = 6,
372 };
373
374 static const struct dc_plane_cap plane_cap = {
375 .type = DC_PLANE_TYPE_DCE_RGB,
376
377 .pixel_format_support = {
378 .argb8888 = true,
379 .nv12 = false,
380 .fp16 = false
381 },
382
383 .max_upscale_factor = {
384 .argb8888 = 16000,
385 .nv12 = 1,
386 .fp16 = 1
387 },
388
389 .max_downscale_factor = {
390 .argb8888 = 250,
391 .nv12 = 1,
392 .fp16 = 1
393 }
394 };
395
396 #define CTX ctx
397 #define REG(reg) mm ## reg
398
399 #ifndef mmCC_DC_HDMI_STRAPS
400 #define mmCC_DC_HDMI_STRAPS 0x1918
401 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
402 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
403 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
404 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
405 #endif
406
map_transmitter_id_to_phy_instance(enum transmitter transmitter)407 static int map_transmitter_id_to_phy_instance(
408 enum transmitter transmitter)
409 {
410 switch (transmitter) {
411 case TRANSMITTER_UNIPHY_A:
412 return 0;
413 break;
414 case TRANSMITTER_UNIPHY_B:
415 return 1;
416 break;
417 case TRANSMITTER_UNIPHY_C:
418 return 2;
419 break;
420 case TRANSMITTER_UNIPHY_D:
421 return 3;
422 break;
423 case TRANSMITTER_UNIPHY_E:
424 return 4;
425 break;
426 case TRANSMITTER_UNIPHY_F:
427 return 5;
428 break;
429 case TRANSMITTER_UNIPHY_G:
430 return 6;
431 break;
432 default:
433 ASSERT(0);
434 return 0;
435 }
436 }
437
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)438 static void read_dce_straps(
439 struct dc_context *ctx,
440 struct resource_straps *straps)
441 {
442 REG_GET_2(CC_DC_HDMI_STRAPS,
443 HDMI_DISABLE, &straps->hdmi_disable,
444 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
445
446 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
447 }
448
create_audio(struct dc_context * ctx,unsigned int inst)449 static struct audio *create_audio(
450 struct dc_context *ctx, unsigned int inst)
451 {
452 return dce_audio_create(ctx, inst,
453 &audio_regs[inst], &audio_shift, &audio_mask);
454 }
455
dce100_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)456 static struct timing_generator *dce100_timing_generator_create(
457 struct dc_context *ctx,
458 uint32_t instance,
459 const struct dce110_timing_generator_offsets *offsets)
460 {
461 struct dce110_timing_generator *tg110 =
462 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
463
464 if (!tg110)
465 return NULL;
466
467 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
468 return &tg110->base;
469 }
470
dce100_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)471 static struct stream_encoder *dce100_stream_encoder_create(
472 enum engine_id eng_id,
473 struct dc_context *ctx)
474 {
475 struct dce110_stream_encoder *enc110 =
476 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
477
478 if (!enc110)
479 return NULL;
480
481 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
482 &stream_enc_regs[eng_id], &se_shift, &se_mask);
483 return &enc110->base;
484 }
485
486 #define SRII(reg_name, block, id)\
487 .reg_name[id] = mm ## block ## id ## _ ## reg_name
488
489 static const struct dce_hwseq_registers hwseq_reg = {
490 HWSEQ_DCE10_REG_LIST()
491 };
492
493 static const struct dce_hwseq_shift hwseq_shift = {
494 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
495 };
496
497 static const struct dce_hwseq_mask hwseq_mask = {
498 HWSEQ_DCE10_MASK_SH_LIST(_MASK)
499 };
500
dce100_hwseq_create(struct dc_context * ctx)501 static struct dce_hwseq *dce100_hwseq_create(
502 struct dc_context *ctx)
503 {
504 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
505
506 if (hws) {
507 hws->ctx = ctx;
508 hws->regs = &hwseq_reg;
509 hws->shifts = &hwseq_shift;
510 hws->masks = &hwseq_mask;
511 }
512 return hws;
513 }
514
515 static const struct resource_create_funcs res_create_funcs = {
516 .read_dce_straps = read_dce_straps,
517 .create_audio = create_audio,
518 .create_stream_encoder = dce100_stream_encoder_create,
519 .create_hwseq = dce100_hwseq_create,
520 };
521
522 #define mi_inst_regs(id) { \
523 MI_DCE8_REG_LIST(id), \
524 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
525 }
526 static const struct dce_mem_input_registers mi_regs[] = {
527 mi_inst_regs(0),
528 mi_inst_regs(1),
529 mi_inst_regs(2),
530 mi_inst_regs(3),
531 mi_inst_regs(4),
532 mi_inst_regs(5),
533 };
534
535 static const struct dce_mem_input_shift mi_shifts = {
536 MI_DCE8_MASK_SH_LIST(__SHIFT),
537 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
538 };
539
540 static const struct dce_mem_input_mask mi_masks = {
541 MI_DCE8_MASK_SH_LIST(_MASK),
542 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
543 };
544
545 static const struct dce110_aux_registers_shift aux_shift = {
546 DCE10_AUX_MASK_SH_LIST(__SHIFT)
547 };
548
549 static const struct dce110_aux_registers_mask aux_mask = {
550 DCE10_AUX_MASK_SH_LIST(_MASK)
551 };
552
dce100_mem_input_create(struct dc_context * ctx,uint32_t inst)553 static struct mem_input *dce100_mem_input_create(
554 struct dc_context *ctx,
555 uint32_t inst)
556 {
557 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
558 GFP_KERNEL);
559
560 if (!dce_mi) {
561 BREAK_TO_DEBUGGER();
562 return NULL;
563 }
564
565 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
566 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
567 return &dce_mi->base;
568 }
569
dce100_transform_destroy(struct transform ** xfm)570 static void dce100_transform_destroy(struct transform **xfm)
571 {
572 kfree(TO_DCE_TRANSFORM(*xfm));
573 *xfm = NULL;
574 }
575
dce100_transform_create(struct dc_context * ctx,uint32_t inst)576 static struct transform *dce100_transform_create(
577 struct dc_context *ctx,
578 uint32_t inst)
579 {
580 struct dce_transform *transform =
581 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
582
583 if (!transform)
584 return NULL;
585
586 dce_transform_construct(transform, ctx, inst,
587 &xfm_regs[inst], &xfm_shift, &xfm_mask);
588 return &transform->base;
589 }
590
dce100_ipp_create(struct dc_context * ctx,uint32_t inst)591 static struct input_pixel_processor *dce100_ipp_create(
592 struct dc_context *ctx, uint32_t inst)
593 {
594 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
595
596 if (!ipp) {
597 BREAK_TO_DEBUGGER();
598 return NULL;
599 }
600
601 dce_ipp_construct(ipp, ctx, inst,
602 &ipp_regs[inst], &ipp_shift, &ipp_mask);
603 return &ipp->base;
604 }
605
606 static const struct encoder_feature_support link_enc_feature = {
607 .max_hdmi_deep_color = COLOR_DEPTH_121212,
608 .max_hdmi_pixel_clock = 300000,
609 .flags.bits.IS_HBR2_CAPABLE = true,
610 .flags.bits.IS_TPS3_CAPABLE = true
611 };
612
dce100_link_encoder_create(const struct encoder_init_data * enc_init_data)613 struct link_encoder *dce100_link_encoder_create(
614 const struct encoder_init_data *enc_init_data)
615 {
616 struct dce110_link_encoder *enc110 =
617 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
618 int link_regs_id;
619
620 if (!enc110)
621 return NULL;
622
623 link_regs_id =
624 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
625
626 dce110_link_encoder_construct(enc110,
627 enc_init_data,
628 &link_enc_feature,
629 &link_enc_regs[link_regs_id],
630 &link_enc_aux_regs[enc_init_data->channel - 1],
631 &link_enc_hpd_regs[enc_init_data->hpd_source]);
632 return &enc110->base;
633 }
634
dce100_opp_create(struct dc_context * ctx,uint32_t inst)635 struct output_pixel_processor *dce100_opp_create(
636 struct dc_context *ctx,
637 uint32_t inst)
638 {
639 struct dce110_opp *opp =
640 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
641
642 if (!opp)
643 return NULL;
644
645 dce110_opp_construct(opp,
646 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
647 return &opp->base;
648 }
649
dce100_aux_engine_create(struct dc_context * ctx,uint32_t inst)650 struct dce_aux *dce100_aux_engine_create(
651 struct dc_context *ctx,
652 uint32_t inst)
653 {
654 struct aux_engine_dce110 *aux_engine =
655 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
656
657 if (!aux_engine)
658 return NULL;
659
660 dce110_aux_engine_construct(aux_engine, ctx, inst,
661 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
662 &aux_engine_regs[inst],
663 &aux_mask,
664 &aux_shift,
665 ctx->dc->caps.extended_aux_timeout_support);
666
667 return &aux_engine->base;
668 }
669 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
670
671 static const struct dce_i2c_registers i2c_hw_regs[] = {
672 i2c_inst_regs(1),
673 i2c_inst_regs(2),
674 i2c_inst_regs(3),
675 i2c_inst_regs(4),
676 i2c_inst_regs(5),
677 i2c_inst_regs(6),
678 };
679
680 static const struct dce_i2c_shift i2c_shifts = {
681 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
682 };
683
684 static const struct dce_i2c_mask i2c_masks = {
685 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
686 };
687
dce100_i2c_hw_create(struct dc_context * ctx,uint32_t inst)688 struct dce_i2c_hw *dce100_i2c_hw_create(
689 struct dc_context *ctx,
690 uint32_t inst)
691 {
692 struct dce_i2c_hw *dce_i2c_hw =
693 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
694
695 if (!dce_i2c_hw)
696 return NULL;
697
698 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
699 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
700
701 return dce_i2c_hw;
702 }
dce100_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)703 struct clock_source *dce100_clock_source_create(
704 struct dc_context *ctx,
705 struct dc_bios *bios,
706 enum clock_source_id id,
707 const struct dce110_clk_src_regs *regs,
708 bool dp_clk_src)
709 {
710 struct dce110_clk_src *clk_src =
711 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
712
713 if (!clk_src)
714 return NULL;
715
716 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
717 regs, &cs_shift, &cs_mask)) {
718 clk_src->base.dp_clk_src = dp_clk_src;
719 return &clk_src->base;
720 }
721
722 kfree(clk_src);
723 BREAK_TO_DEBUGGER();
724 return NULL;
725 }
726
dce100_clock_source_destroy(struct clock_source ** clk_src)727 void dce100_clock_source_destroy(struct clock_source **clk_src)
728 {
729 kfree(TO_DCE110_CLK_SRC(*clk_src));
730 *clk_src = NULL;
731 }
732
dce100_resource_destruct(struct dce110_resource_pool * pool)733 static void dce100_resource_destruct(struct dce110_resource_pool *pool)
734 {
735 unsigned int i;
736
737 for (i = 0; i < pool->base.pipe_count; i++) {
738 if (pool->base.opps[i] != NULL)
739 dce110_opp_destroy(&pool->base.opps[i]);
740
741 if (pool->base.transforms[i] != NULL)
742 dce100_transform_destroy(&pool->base.transforms[i]);
743
744 if (pool->base.ipps[i] != NULL)
745 dce_ipp_destroy(&pool->base.ipps[i]);
746
747 if (pool->base.mis[i] != NULL) {
748 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
749 pool->base.mis[i] = NULL;
750 }
751
752 if (pool->base.timing_generators[i] != NULL) {
753 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
754 pool->base.timing_generators[i] = NULL;
755 }
756 }
757
758 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
759 if (pool->base.engines[i] != NULL)
760 dce110_engine_destroy(&pool->base.engines[i]);
761 if (pool->base.hw_i2cs[i] != NULL) {
762 kfree(pool->base.hw_i2cs[i]);
763 pool->base.hw_i2cs[i] = NULL;
764 }
765 if (pool->base.sw_i2cs[i] != NULL) {
766 kfree(pool->base.sw_i2cs[i]);
767 pool->base.sw_i2cs[i] = NULL;
768 }
769 }
770
771 for (i = 0; i < pool->base.stream_enc_count; i++) {
772 if (pool->base.stream_enc[i] != NULL)
773 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
774 }
775
776 for (i = 0; i < pool->base.clk_src_count; i++) {
777 if (pool->base.clock_sources[i] != NULL)
778 dce100_clock_source_destroy(&pool->base.clock_sources[i]);
779 }
780
781 if (pool->base.dp_clock_source != NULL)
782 dce100_clock_source_destroy(&pool->base.dp_clock_source);
783
784 for (i = 0; i < pool->base.audio_count; i++) {
785 if (pool->base.audios[i] != NULL)
786 dce_aud_destroy(&pool->base.audios[i]);
787 }
788
789 if (pool->base.abm != NULL)
790 dce_abm_destroy(&pool->base.abm);
791
792 if (pool->base.dmcu != NULL)
793 dce_dmcu_destroy(&pool->base.dmcu);
794
795 if (pool->base.irqs != NULL)
796 dal_irq_service_destroy(&pool->base.irqs);
797 }
798
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)799 static enum dc_status build_mapped_resource(
800 const struct dc *dc,
801 struct dc_state *context,
802 struct dc_stream_state *stream)
803 {
804 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
805
806 if (!pipe_ctx)
807 return DC_ERROR_UNEXPECTED;
808
809 dce110_resource_build_pipe_hw_param(pipe_ctx);
810
811 resource_build_info_frame(pipe_ctx);
812
813 return DC_OK;
814 }
815
dce100_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)816 bool dce100_validate_bandwidth(
817 struct dc *dc,
818 struct dc_state *context,
819 bool fast_validate)
820 {
821 int i;
822 bool at_least_one_pipe = false;
823
824 for (i = 0; i < dc->res_pool->pipe_count; i++) {
825 if (context->res_ctx.pipe_ctx[i].stream)
826 at_least_one_pipe = true;
827 }
828
829 if (at_least_one_pipe) {
830 /* TODO implement when needed but for now hardcode max value*/
831 context->bw_ctx.bw.dce.dispclk_khz = 681000;
832 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
833 } else {
834 context->bw_ctx.bw.dce.dispclk_khz = 0;
835 context->bw_ctx.bw.dce.yclk_khz = 0;
836 }
837
838 return true;
839 }
840
dce100_validate_surface_sets(struct dc_state * context)841 static bool dce100_validate_surface_sets(
842 struct dc_state *context)
843 {
844 int i;
845
846 for (i = 0; i < context->stream_count; i++) {
847 if (context->stream_status[i].plane_count == 0)
848 continue;
849
850 if (context->stream_status[i].plane_count > 1)
851 return false;
852
853 if (context->stream_status[i].plane_states[0]->format
854 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
855 return false;
856 }
857
858 return true;
859 }
860
dce100_validate_global(struct dc * dc,struct dc_state * context)861 enum dc_status dce100_validate_global(
862 struct dc *dc,
863 struct dc_state *context)
864 {
865 if (!dce100_validate_surface_sets(context))
866 return DC_FAIL_SURFACE_VALIDATE;
867
868 return DC_OK;
869 }
870
dce100_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)871 enum dc_status dce100_add_stream_to_ctx(
872 struct dc *dc,
873 struct dc_state *new_ctx,
874 struct dc_stream_state *dc_stream)
875 {
876 enum dc_status result = DC_ERROR_UNEXPECTED;
877
878 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
879
880 if (result == DC_OK)
881 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
882
883 if (result == DC_OK)
884 result = build_mapped_resource(dc, new_ctx, dc_stream);
885
886 return result;
887 }
888
dce100_destroy_resource_pool(struct resource_pool ** pool)889 static void dce100_destroy_resource_pool(struct resource_pool **pool)
890 {
891 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
892
893 dce100_resource_destruct(dce110_pool);
894 kfree(dce110_pool);
895 *pool = NULL;
896 }
897
dce100_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)898 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
899 {
900
901 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
902 return DC_OK;
903
904 return DC_FAIL_SURFACE_VALIDATE;
905 }
906
dce100_find_first_free_match_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)907 struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
908 struct resource_context *res_ctx,
909 const struct resource_pool *pool,
910 struct dc_stream_state *stream)
911 {
912 int i;
913 int j = -1;
914 struct dc_link *link = stream->link;
915
916 for (i = 0; i < pool->stream_enc_count; i++) {
917 if (!res_ctx->is_stream_enc_acquired[i] &&
918 pool->stream_enc[i]) {
919 /* Store first available for MST second display
920 * in daisy chain use case
921 */
922 j = i;
923 if (pool->stream_enc[i]->id ==
924 link->link_enc->preferred_engine)
925 return pool->stream_enc[i];
926 }
927 }
928
929 /*
930 * below can happen in cases when stream encoder is acquired:
931 * 1) for second MST display in chain, so preferred engine already
932 * acquired;
933 * 2) for another link, which preferred engine already acquired by any
934 * MST configuration.
935 *
936 * If signal is of DP type and preferred engine not found, return last available
937 *
938 * TODO - This is just a patch up and a generic solution is
939 * required for non DP connectors.
940 */
941
942 if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
943 return pool->stream_enc[j];
944
945 return NULL;
946 }
947
948 static const struct resource_funcs dce100_res_pool_funcs = {
949 .destroy = dce100_destroy_resource_pool,
950 .link_enc_create = dce100_link_encoder_create,
951 .validate_bandwidth = dce100_validate_bandwidth,
952 .validate_plane = dce100_validate_plane,
953 .add_stream_to_ctx = dce100_add_stream_to_ctx,
954 .validate_global = dce100_validate_global,
955 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
956 };
957
dce100_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)958 static bool dce100_resource_construct(
959 uint8_t num_virtual_links,
960 struct dc *dc,
961 struct dce110_resource_pool *pool)
962 {
963 unsigned int i;
964 struct dc_context *ctx = dc->ctx;
965 struct dc_bios *bp;
966
967 ctx->dc_bios->regs = &bios_regs;
968
969 pool->base.res_cap = &res_cap;
970 pool->base.funcs = &dce100_res_pool_funcs;
971 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
972
973 bp = ctx->dc_bios;
974
975 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
976 pool->base.dp_clock_source =
977 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
978
979 pool->base.clock_sources[0] =
980 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
981 pool->base.clock_sources[1] =
982 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
983 pool->base.clock_sources[2] =
984 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
985 pool->base.clk_src_count = 3;
986
987 } else {
988 pool->base.dp_clock_source =
989 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
990
991 pool->base.clock_sources[0] =
992 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
993 pool->base.clock_sources[1] =
994 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
995 pool->base.clk_src_count = 2;
996 }
997
998 if (pool->base.dp_clock_source == NULL) {
999 dm_error("DC: failed to create dp clock source!\n");
1000 BREAK_TO_DEBUGGER();
1001 goto res_create_fail;
1002 }
1003
1004 for (i = 0; i < pool->base.clk_src_count; i++) {
1005 if (pool->base.clock_sources[i] == NULL) {
1006 dm_error("DC: failed to create clock sources!\n");
1007 BREAK_TO_DEBUGGER();
1008 goto res_create_fail;
1009 }
1010 }
1011
1012 pool->base.dmcu = dce_dmcu_create(ctx,
1013 &dmcu_regs,
1014 &dmcu_shift,
1015 &dmcu_mask);
1016 if (pool->base.dmcu == NULL) {
1017 dm_error("DC: failed to create dmcu!\n");
1018 BREAK_TO_DEBUGGER();
1019 goto res_create_fail;
1020 }
1021
1022 pool->base.abm = dce_abm_create(ctx,
1023 &abm_regs,
1024 &abm_shift,
1025 &abm_mask);
1026 if (pool->base.abm == NULL) {
1027 dm_error("DC: failed to create abm!\n");
1028 BREAK_TO_DEBUGGER();
1029 goto res_create_fail;
1030 }
1031
1032 {
1033 struct irq_service_init_data init_data;
1034 init_data.ctx = dc->ctx;
1035 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1036 if (!pool->base.irqs)
1037 goto res_create_fail;
1038 }
1039
1040 /*************************************************
1041 * Resource + asic cap harcoding *
1042 *************************************************/
1043 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1044 pool->base.pipe_count = res_cap.num_timing_generator;
1045 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1046 dc->caps.max_downscale_ratio = 200;
1047 dc->caps.i2c_speed_in_khz = 40;
1048 dc->caps.max_cursor_size = 128;
1049 dc->caps.dual_link_dvi = true;
1050 dc->caps.disable_dp_clk_share = true;
1051 dc->caps.extended_aux_timeout_support = false;
1052
1053 for (i = 0; i < pool->base.pipe_count; i++) {
1054 pool->base.timing_generators[i] =
1055 dce100_timing_generator_create(
1056 ctx,
1057 i,
1058 &dce100_tg_offsets[i]);
1059 if (pool->base.timing_generators[i] == NULL) {
1060 BREAK_TO_DEBUGGER();
1061 dm_error("DC: failed to create tg!\n");
1062 goto res_create_fail;
1063 }
1064
1065 pool->base.mis[i] = dce100_mem_input_create(ctx, i);
1066 if (pool->base.mis[i] == NULL) {
1067 BREAK_TO_DEBUGGER();
1068 dm_error(
1069 "DC: failed to create memory input!\n");
1070 goto res_create_fail;
1071 }
1072
1073 pool->base.ipps[i] = dce100_ipp_create(ctx, i);
1074 if (pool->base.ipps[i] == NULL) {
1075 BREAK_TO_DEBUGGER();
1076 dm_error(
1077 "DC: failed to create input pixel processor!\n");
1078 goto res_create_fail;
1079 }
1080
1081 pool->base.transforms[i] = dce100_transform_create(ctx, i);
1082 if (pool->base.transforms[i] == NULL) {
1083 BREAK_TO_DEBUGGER();
1084 dm_error(
1085 "DC: failed to create transform!\n");
1086 goto res_create_fail;
1087 }
1088
1089 pool->base.opps[i] = dce100_opp_create(ctx, i);
1090 if (pool->base.opps[i] == NULL) {
1091 BREAK_TO_DEBUGGER();
1092 dm_error(
1093 "DC: failed to create output pixel processor!\n");
1094 goto res_create_fail;
1095 }
1096 }
1097
1098 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1099 pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
1100 if (pool->base.engines[i] == NULL) {
1101 BREAK_TO_DEBUGGER();
1102 dm_error(
1103 "DC:failed to create aux engine!!\n");
1104 goto res_create_fail;
1105 }
1106 pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i);
1107 if (pool->base.hw_i2cs[i] == NULL) {
1108 BREAK_TO_DEBUGGER();
1109 dm_error(
1110 "DC:failed to create i2c engine!!\n");
1111 goto res_create_fail;
1112 }
1113 pool->base.sw_i2cs[i] = NULL;
1114 }
1115
1116 dc->caps.max_planes = pool->base.pipe_count;
1117
1118 for (i = 0; i < dc->caps.max_planes; ++i)
1119 dc->caps.planes[i] = plane_cap;
1120
1121 if (!resource_construct(num_virtual_links, dc, &pool->base,
1122 &res_create_funcs))
1123 goto res_create_fail;
1124
1125 /* Create hardware sequencer */
1126 dce100_hw_sequencer_construct(dc);
1127 return true;
1128
1129 res_create_fail:
1130 dce100_resource_destruct(pool);
1131
1132 return false;
1133 }
1134
dce100_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1135 struct resource_pool *dce100_create_resource_pool(
1136 uint8_t num_virtual_links,
1137 struct dc *dc)
1138 {
1139 struct dce110_resource_pool *pool =
1140 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1141
1142 if (!pool)
1143 return NULL;
1144
1145 if (dce100_resource_construct(num_virtual_links, dc, pool))
1146 return &pool->base;
1147
1148 kfree(pool);
1149 BREAK_TO_DEBUGGER();
1150 return NULL;
1151 }
1152
1153