1 //===-- SIMCCodeEmitter.cpp - SI Code Emitter -----------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The SI code emitter produces machine code that can be executed
11 /// directly on the GPU device.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "MCTargetDesc/AMDGPUFixupKinds.h"
16 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
17 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
18 #include "SIDefines.h"
19 #include "Utils/AMDGPUBaseInfo.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24
25 using namespace llvm;
26
27 namespace {
28
29 class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
30 const MCRegisterInfo &MRI;
31
32 /// Encode an fp or int literal
33 uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo,
34 const MCSubtargetInfo &STI) const;
35
36 public:
SIMCCodeEmitter(const MCInstrInfo & mcii,const MCRegisterInfo & mri,MCContext & ctx)37 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
38 MCContext &ctx)
39 : AMDGPUMCCodeEmitter(mcii), MRI(mri) {}
40 SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
41 SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
42
43 /// Encode the instruction and write it to the OS.
44 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
45 SmallVectorImpl<MCFixup> &Fixups,
46 const MCSubtargetInfo &STI) const override;
47
48 /// \returns the encoding for an MCOperand.
49 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
50 SmallVectorImpl<MCFixup> &Fixups,
51 const MCSubtargetInfo &STI) const override;
52
53 /// Use a fixup to encode the simm16 field for SOPP branch
54 /// instructions.
55 unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
56 SmallVectorImpl<MCFixup> &Fixups,
57 const MCSubtargetInfo &STI) const override;
58
59 unsigned getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo,
60 SmallVectorImpl<MCFixup> &Fixups,
61 const MCSubtargetInfo &STI) const override;
62
63 unsigned getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
64 SmallVectorImpl<MCFixup> &Fixups,
65 const MCSubtargetInfo &STI) const override;
66
67 unsigned getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
68 SmallVectorImpl<MCFixup> &Fixups,
69 const MCSubtargetInfo &STI) const override;
70
71 unsigned getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
72 SmallVectorImpl<MCFixup> &Fixups,
73 const MCSubtargetInfo &STI) const override;
74
75 private:
76 uint64_t getImplicitOpSelHiEncoding(int Opcode) const;
77 };
78
79 } // end anonymous namespace
80
createSIMCCodeEmitter(const MCInstrInfo & MCII,const MCRegisterInfo & MRI,MCContext & Ctx)81 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
82 const MCRegisterInfo &MRI,
83 MCContext &Ctx) {
84 return new SIMCCodeEmitter(MCII, MRI, Ctx);
85 }
86
87 // Returns the encoding value to use if the given integer is an integer inline
88 // immediate value, or 0 if it is not.
89 template <typename IntTy>
getIntInlineImmEncoding(IntTy Imm)90 static uint32_t getIntInlineImmEncoding(IntTy Imm) {
91 if (Imm >= 0 && Imm <= 64)
92 return 128 + Imm;
93
94 if (Imm >= -16 && Imm <= -1)
95 return 192 + std::abs(Imm);
96
97 return 0;
98 }
99
getLit16IntEncoding(uint16_t Val,const MCSubtargetInfo & STI)100 static uint32_t getLit16IntEncoding(uint16_t Val, const MCSubtargetInfo &STI) {
101 uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
102 return IntImm == 0 ? 255 : IntImm;
103 }
104
getLit16Encoding(uint16_t Val,const MCSubtargetInfo & STI)105 static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI) {
106 uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
107 if (IntImm != 0)
108 return IntImm;
109
110 if (Val == 0x3800) // 0.5
111 return 240;
112
113 if (Val == 0xB800) // -0.5
114 return 241;
115
116 if (Val == 0x3C00) // 1.0
117 return 242;
118
119 if (Val == 0xBC00) // -1.0
120 return 243;
121
122 if (Val == 0x4000) // 2.0
123 return 244;
124
125 if (Val == 0xC000) // -2.0
126 return 245;
127
128 if (Val == 0x4400) // 4.0
129 return 246;
130
131 if (Val == 0xC400) // -4.0
132 return 247;
133
134 if (Val == 0x3118 && // 1.0 / (2.0 * pi)
135 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
136 return 248;
137
138 return 255;
139 }
140
getLit32Encoding(uint32_t Val,const MCSubtargetInfo & STI)141 static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) {
142 uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val));
143 if (IntImm != 0)
144 return IntImm;
145
146 if (Val == FloatToBits(0.5f))
147 return 240;
148
149 if (Val == FloatToBits(-0.5f))
150 return 241;
151
152 if (Val == FloatToBits(1.0f))
153 return 242;
154
155 if (Val == FloatToBits(-1.0f))
156 return 243;
157
158 if (Val == FloatToBits(2.0f))
159 return 244;
160
161 if (Val == FloatToBits(-2.0f))
162 return 245;
163
164 if (Val == FloatToBits(4.0f))
165 return 246;
166
167 if (Val == FloatToBits(-4.0f))
168 return 247;
169
170 if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi)
171 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
172 return 248;
173
174 return 255;
175 }
176
getLit64Encoding(uint64_t Val,const MCSubtargetInfo & STI)177 static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
178 uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
179 if (IntImm != 0)
180 return IntImm;
181
182 if (Val == DoubleToBits(0.5))
183 return 240;
184
185 if (Val == DoubleToBits(-0.5))
186 return 241;
187
188 if (Val == DoubleToBits(1.0))
189 return 242;
190
191 if (Val == DoubleToBits(-1.0))
192 return 243;
193
194 if (Val == DoubleToBits(2.0))
195 return 244;
196
197 if (Val == DoubleToBits(-2.0))
198 return 245;
199
200 if (Val == DoubleToBits(4.0))
201 return 246;
202
203 if (Val == DoubleToBits(-4.0))
204 return 247;
205
206 if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
207 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
208 return 248;
209
210 return 255;
211 }
212
getLitEncoding(const MCOperand & MO,const MCOperandInfo & OpInfo,const MCSubtargetInfo & STI) const213 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
214 const MCOperandInfo &OpInfo,
215 const MCSubtargetInfo &STI) const {
216 int64_t Imm;
217 if (MO.isExpr()) {
218 const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
219 if (!C)
220 return 255;
221
222 Imm = C->getValue();
223 } else {
224
225 assert(!MO.isDFPImm());
226
227 if (!MO.isImm())
228 return ~0;
229
230 Imm = MO.getImm();
231 }
232
233 switch (OpInfo.OperandType) {
234 case AMDGPU::OPERAND_REG_IMM_INT32:
235 case AMDGPU::OPERAND_REG_IMM_FP32:
236 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
237 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
238 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
239 case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
240 case AMDGPU::OPERAND_REG_IMM_V2INT32:
241 case AMDGPU::OPERAND_REG_IMM_V2FP32:
242 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
243 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
244 return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
245
246 case AMDGPU::OPERAND_REG_IMM_INT64:
247 case AMDGPU::OPERAND_REG_IMM_FP64:
248 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
249 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
250 case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
251 return getLit64Encoding(static_cast<uint64_t>(Imm), STI);
252
253 case AMDGPU::OPERAND_REG_IMM_INT16:
254 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
255 case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
256 return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI);
257 case AMDGPU::OPERAND_REG_IMM_FP16:
258 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
259 case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
260 // FIXME Is this correct? What do inline immediates do on SI for f16 src
261 // which does not have f16 support?
262 return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
263 case AMDGPU::OPERAND_REG_IMM_V2INT16:
264 case AMDGPU::OPERAND_REG_IMM_V2FP16: {
265 if (!isUInt<16>(Imm) && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal])
266 return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
267 if (OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16)
268 return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
269 LLVM_FALLTHROUGH;
270 }
271 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
272 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
273 return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI);
274 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
275 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {
276 uint16_t Lo16 = static_cast<uint16_t>(Imm);
277 uint32_t Encoding = getLit16Encoding(Lo16, STI);
278 return Encoding;
279 }
280 default:
281 llvm_unreachable("invalid operand size");
282 }
283 }
284
getImplicitOpSelHiEncoding(int Opcode) const285 uint64_t SIMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const {
286 using namespace AMDGPU::VOP3PEncoding;
287 using namespace AMDGPU::OpName;
288
289 if (AMDGPU::getNamedOperandIdx(Opcode, op_sel_hi) != -1) {
290 if (AMDGPU::getNamedOperandIdx(Opcode, src2) != -1)
291 return 0;
292 if (AMDGPU::getNamedOperandIdx(Opcode, src1) != -1)
293 return OP_SEL_HI_2;
294 if (AMDGPU::getNamedOperandIdx(Opcode, src0) != -1)
295 return OP_SEL_HI_1 | OP_SEL_HI_2;
296 }
297 return OP_SEL_HI_0 | OP_SEL_HI_1 | OP_SEL_HI_2;
298 }
299
encodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const300 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
301 SmallVectorImpl<MCFixup> &Fixups,
302 const MCSubtargetInfo &STI) const {
303 verifyInstructionPredicates(MI,
304 computeAvailableFeatures(STI.getFeatureBits()));
305
306 int Opcode = MI.getOpcode();
307 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
308 const MCInstrDesc &Desc = MCII.get(Opcode);
309 unsigned bytes = Desc.getSize();
310
311 // Set unused op_sel_hi bits to 1 for VOP3P and MAI instructions.
312 // Note that accvgpr_read/write are MAI, have src0, but do not use op_sel.
313 if ((Desc.TSFlags & SIInstrFlags::VOP3P) ||
314 Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi ||
315 Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) {
316 Encoding |= getImplicitOpSelHiEncoding(Opcode);
317 }
318
319 for (unsigned i = 0; i < bytes; i++) {
320 OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
321 }
322
323 // NSA encoding.
324 if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {
325 int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
326 AMDGPU::OpName::vaddr0);
327 int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
328 AMDGPU::OpName::srsrc);
329 assert(vaddr0 >= 0 && srsrc > vaddr0);
330 unsigned NumExtraAddrs = srsrc - vaddr0 - 1;
331 unsigned NumPadding = (-NumExtraAddrs) & 3;
332
333 for (unsigned i = 0; i < NumExtraAddrs; ++i)
334 OS.write((uint8_t)getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i),
335 Fixups, STI));
336 for (unsigned i = 0; i < NumPadding; ++i)
337 OS.write(0);
338 }
339
340 if ((bytes > 8 && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) ||
341 (bytes > 4 && !STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]))
342 return;
343
344 // Check for additional literals in SRC0/1/2 (Op 1/2/3)
345 for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) {
346
347 // Check if this operand should be encoded as [SV]Src
348 if (!AMDGPU::isSISrcOperand(Desc, i))
349 continue;
350
351 // Is this operand a literal immediate?
352 const MCOperand &Op = MI.getOperand(i);
353 if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255)
354 continue;
355
356 // Yes! Encode it
357 int64_t Imm = 0;
358
359 if (Op.isImm())
360 Imm = Op.getImm();
361 else if (Op.isExpr()) {
362 if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
363 Imm = C->getValue();
364
365 } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
366 llvm_unreachable("Must be immediate or expr");
367
368 for (unsigned j = 0; j < 4; j++) {
369 OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
370 }
371
372 // Only one literal value allowed
373 break;
374 }
375 }
376
getSOPPBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const377 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
378 SmallVectorImpl<MCFixup> &Fixups,
379 const MCSubtargetInfo &STI) const {
380 const MCOperand &MO = MI.getOperand(OpNo);
381
382 if (MO.isExpr()) {
383 const MCExpr *Expr = MO.getExpr();
384 MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
385 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
386 return 0;
387 }
388
389 return getMachineOpValue(MI, MO, Fixups, STI);
390 }
391
getSMEMOffsetEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const392 unsigned SIMCCodeEmitter::getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo,
393 SmallVectorImpl<MCFixup> &Fixups,
394 const MCSubtargetInfo &STI) const {
395 auto Offset = MI.getOperand(OpNo).getImm();
396 // VI only supports 20-bit unsigned offsets.
397 assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset));
398 return Offset;
399 }
400
401 unsigned
getSDWASrcEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const402 SIMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
403 SmallVectorImpl<MCFixup> &Fixups,
404 const MCSubtargetInfo &STI) const {
405 using namespace AMDGPU::SDWA;
406
407 uint64_t RegEnc = 0;
408
409 const MCOperand &MO = MI.getOperand(OpNo);
410
411 if (MO.isReg()) {
412 unsigned Reg = MO.getReg();
413 RegEnc |= MRI.getEncodingValue(Reg);
414 RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
415 if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {
416 RegEnc |= SDWA9EncValues::SRC_SGPR_MASK;
417 }
418 return RegEnc;
419 } else {
420 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
421 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
422 if (Enc != ~0U && Enc != 255) {
423 return Enc | SDWA9EncValues::SRC_SGPR_MASK;
424 }
425 }
426
427 llvm_unreachable("Unsupported operand kind");
428 return 0;
429 }
430
431 unsigned
getSDWAVopcDstEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const432 SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
433 SmallVectorImpl<MCFixup> &Fixups,
434 const MCSubtargetInfo &STI) const {
435 using namespace AMDGPU::SDWA;
436
437 uint64_t RegEnc = 0;
438
439 const MCOperand &MO = MI.getOperand(OpNo);
440
441 unsigned Reg = MO.getReg();
442 if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {
443 RegEnc |= MRI.getEncodingValue(Reg);
444 RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
445 RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK;
446 }
447 return RegEnc;
448 }
449
450 unsigned
getAVOperandEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const451 SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
452 SmallVectorImpl<MCFixup> &Fixups,
453 const MCSubtargetInfo &STI) const {
454 unsigned Reg = MI.getOperand(OpNo).getReg();
455 uint64_t Enc = MRI.getEncodingValue(Reg);
456
457 // VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma
458 // instructions use acc[0:1] modifier bits to distinguish. These bits are
459 // encoded as a virtual 9th bit of the register for these operands.
460 if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
461 MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||
462 MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||
463 MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||
464 MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||
465 MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||
466 MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||
467 MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))
468 Enc |= 512;
469
470 return Enc;
471 }
472
needsPCRel(const MCExpr * Expr)473 static bool needsPCRel(const MCExpr *Expr) {
474 switch (Expr->getKind()) {
475 case MCExpr::SymbolRef: {
476 auto *SE = cast<MCSymbolRefExpr>(Expr);
477 MCSymbolRefExpr::VariantKind Kind = SE->getKind();
478 return Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_LO &&
479 Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
480 }
481 case MCExpr::Binary: {
482 auto *BE = cast<MCBinaryExpr>(Expr);
483 if (BE->getOpcode() == MCBinaryExpr::Sub)
484 return false;
485 return needsPCRel(BE->getLHS()) || needsPCRel(BE->getRHS());
486 }
487 case MCExpr::Unary:
488 return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr());
489 case MCExpr::Target:
490 case MCExpr::Constant:
491 return false;
492 }
493 llvm_unreachable("invalid kind");
494 }
495
getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const496 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
497 const MCOperand &MO,
498 SmallVectorImpl<MCFixup> &Fixups,
499 const MCSubtargetInfo &STI) const {
500 if (MO.isReg())
501 return MRI.getEncodingValue(MO.getReg());
502
503 if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
504 // FIXME: If this is expression is PCRel or not should not depend on what
505 // the expression looks like. Given that this is just a general expression,
506 // it should probably be FK_Data_4 and whatever is producing
507 //
508 // s_add_u32 s2, s2, (extern_const_addrspace+16
509 //
510 // And expecting a PCRel should instead produce
511 //
512 // .Ltmp1:
513 // s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1
514 MCFixupKind Kind;
515 if (needsPCRel(MO.getExpr()))
516 Kind = FK_PCRel_4;
517 else
518 Kind = FK_Data_4;
519
520 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
521 uint32_t Offset = Desc.getSize();
522 assert(Offset == 4 || Offset == 8);
523
524 Fixups.push_back(
525 MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc()));
526 }
527
528 // Figure out the operand number, needed for isSrcOperand check
529 unsigned OpNo = 0;
530 for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
531 if (&MO == &MI.getOperand(OpNo))
532 break;
533 }
534
535 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
536 if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
537 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
538 if (Enc != ~0U &&
539 (Enc != 255 || Desc.getSize() == 4 || Desc.getSize() == 8))
540 return Enc;
541
542 } else if (MO.isImm())
543 return MO.getImm();
544
545 llvm_unreachable("Encoding of this operand type is not supported yet.");
546 return 0;
547 }
548
549 #define ENABLE_INSTR_PREDICATE_VERIFIER
550 #include "AMDGPUGenMCCodeEmitter.inc"
551