1 //===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "MCTargetDesc/PPCFixupKinds.h"
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "llvm/BinaryFormat/ELF.h"
12 #include "llvm/BinaryFormat/MachO.h"
13 #include "llvm/MC/MCAsmBackend.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCELFObjectWriter.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCMachObjectWriter.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionMachO.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/MCSymbolELF.h"
22 #include "llvm/MC/MCValue.h"
23 #include "llvm/MC/TargetRegistry.h"
24 #include "llvm/Support/ErrorHandling.h"
25 using namespace llvm;
26
adjustFixupValue(unsigned Kind,uint64_t Value)27 static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
28 switch (Kind) {
29 default:
30 llvm_unreachable("Unknown fixup kind!");
31 case FK_Data_1:
32 case FK_Data_2:
33 case FK_Data_4:
34 case FK_Data_8:
35 case PPC::fixup_ppc_nofixup:
36 return Value;
37 case PPC::fixup_ppc_brcond14:
38 case PPC::fixup_ppc_brcond14abs:
39 return Value & 0xfffc;
40 case PPC::fixup_ppc_br24:
41 case PPC::fixup_ppc_br24abs:
42 case PPC::fixup_ppc_br24_notoc:
43 return Value & 0x3fffffc;
44 case PPC::fixup_ppc_half16:
45 return Value & 0xffff;
46 case PPC::fixup_ppc_half16ds:
47 case PPC::fixup_ppc_half16dq:
48 return Value & 0xfffc;
49 case PPC::fixup_ppc_pcrel34:
50 case PPC::fixup_ppc_imm34:
51 return Value & 0x3ffffffff;
52 }
53 }
54
getFixupKindNumBytes(unsigned Kind)55 static unsigned getFixupKindNumBytes(unsigned Kind) {
56 switch (Kind) {
57 default:
58 llvm_unreachable("Unknown fixup kind!");
59 case FK_Data_1:
60 return 1;
61 case FK_Data_2:
62 case PPC::fixup_ppc_half16:
63 case PPC::fixup_ppc_half16ds:
64 case PPC::fixup_ppc_half16dq:
65 return 2;
66 case FK_Data_4:
67 case PPC::fixup_ppc_brcond14:
68 case PPC::fixup_ppc_brcond14abs:
69 case PPC::fixup_ppc_br24:
70 case PPC::fixup_ppc_br24abs:
71 case PPC::fixup_ppc_br24_notoc:
72 return 4;
73 case PPC::fixup_ppc_pcrel34:
74 case PPC::fixup_ppc_imm34:
75 case FK_Data_8:
76 return 8;
77 case PPC::fixup_ppc_nofixup:
78 return 0;
79 }
80 }
81
82 namespace {
83
84 class PPCAsmBackend : public MCAsmBackend {
85 protected:
86 Triple TT;
87 public:
PPCAsmBackend(const Target & T,const Triple & TT)88 PPCAsmBackend(const Target &T, const Triple &TT)
89 : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big),
90 TT(TT) {}
91
getNumFixupKinds() const92 unsigned getNumFixupKinds() const override {
93 return PPC::NumTargetFixupKinds;
94 }
95
getFixupKindInfo(MCFixupKind Kind) const96 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
97 const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
98 // name offset bits flags
99 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
100 { "fixup_ppc_br24_notoc", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
101 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
102 { "fixup_ppc_br24abs", 6, 24, 0 },
103 { "fixup_ppc_brcond14abs", 16, 14, 0 },
104 { "fixup_ppc_half16", 0, 16, 0 },
105 { "fixup_ppc_half16ds", 0, 14, 0 },
106 { "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
107 { "fixup_ppc_imm34", 0, 34, 0 },
108 { "fixup_ppc_nofixup", 0, 0, 0 }
109 };
110 const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
111 // name offset bits flags
112 { "fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
113 { "fixup_ppc_br24_notoc", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
114 { "fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel },
115 { "fixup_ppc_br24abs", 2, 24, 0 },
116 { "fixup_ppc_brcond14abs", 2, 14, 0 },
117 { "fixup_ppc_half16", 0, 16, 0 },
118 { "fixup_ppc_half16ds", 2, 14, 0 },
119 { "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
120 { "fixup_ppc_imm34", 0, 34, 0 },
121 { "fixup_ppc_nofixup", 0, 0, 0 }
122 };
123
124 // Fixup kinds from .reloc directive are like R_PPC_NONE/R_PPC64_NONE. They
125 // do not require any extra processing.
126 if (Kind >= FirstLiteralRelocationKind)
127 return MCAsmBackend::getFixupKindInfo(FK_NONE);
128
129 if (Kind < FirstTargetFixupKind)
130 return MCAsmBackend::getFixupKindInfo(Kind);
131
132 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
133 "Invalid kind!");
134 return (Endian == support::little
135 ? InfosLE
136 : InfosBE)[Kind - FirstTargetFixupKind];
137 }
138
applyFixup(const MCAssembler & Asm,const MCFixup & Fixup,const MCValue & Target,MutableArrayRef<char> Data,uint64_t Value,bool IsResolved,const MCSubtargetInfo * STI) const139 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
140 const MCValue &Target, MutableArrayRef<char> Data,
141 uint64_t Value, bool IsResolved,
142 const MCSubtargetInfo *STI) const override {
143 MCFixupKind Kind = Fixup.getKind();
144 if (Kind >= FirstLiteralRelocationKind)
145 return;
146 Value = adjustFixupValue(Kind, Value);
147 if (!Value) return; // Doesn't change encoding.
148
149 unsigned Offset = Fixup.getOffset();
150 unsigned NumBytes = getFixupKindNumBytes(Kind);
151
152 // For each byte of the fragment that the fixup touches, mask in the bits
153 // from the fixup value. The Value has been "split up" into the appropriate
154 // bitfields above.
155 for (unsigned i = 0; i != NumBytes; ++i) {
156 unsigned Idx = Endian == support::little ? i : (NumBytes - 1 - i);
157 Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff);
158 }
159 }
160
shouldForceRelocation(const MCAssembler & Asm,const MCFixup & Fixup,const MCValue & Target)161 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
162 const MCValue &Target) override {
163 MCFixupKind Kind = Fixup.getKind();
164 switch ((unsigned)Kind) {
165 default:
166 return Kind >= FirstLiteralRelocationKind;
167 case PPC::fixup_ppc_br24:
168 case PPC::fixup_ppc_br24abs:
169 case PPC::fixup_ppc_br24_notoc:
170 // If the target symbol has a local entry point we must not attempt
171 // to resolve the fixup directly. Emit a relocation and leave
172 // resolution of the final target address to the linker.
173 if (const MCSymbolRefExpr *A = Target.getSymA()) {
174 if (const auto *S = dyn_cast<MCSymbolELF>(&A->getSymbol())) {
175 // The "other" values are stored in the last 6 bits of the second
176 // byte. The traditional defines for STO values assume the full byte
177 // and thus the shift to pack it.
178 unsigned Other = S->getOther() << 2;
179 if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0)
180 return true;
181 }
182 }
183 return false;
184 }
185 }
186
fixupNeedsRelaxation(const MCFixup & Fixup,uint64_t Value,const MCRelaxableFragment * DF,const MCAsmLayout & Layout) const187 bool fixupNeedsRelaxation(const MCFixup &Fixup,
188 uint64_t Value,
189 const MCRelaxableFragment *DF,
190 const MCAsmLayout &Layout) const override {
191 // FIXME.
192 llvm_unreachable("relaxInstruction() unimplemented");
193 }
194
relaxInstruction(MCInst & Inst,const MCSubtargetInfo & STI) const195 void relaxInstruction(MCInst &Inst,
196 const MCSubtargetInfo &STI) const override {
197 // FIXME.
198 llvm_unreachable("relaxInstruction() unimplemented");
199 }
200
writeNopData(raw_ostream & OS,uint64_t Count,const MCSubtargetInfo * STI) const201 bool writeNopData(raw_ostream &OS, uint64_t Count,
202 const MCSubtargetInfo *STI) const override {
203 uint64_t NumNops = Count / 4;
204 for (uint64_t i = 0; i != NumNops; ++i)
205 support::endian::write<uint32_t>(OS, 0x60000000, Endian);
206
207 OS.write_zeros(Count % 4);
208
209 return true;
210 }
211 };
212 } // end anonymous namespace
213
214
215 // FIXME: This should be in a separate file.
216 namespace {
217
218 class ELFPPCAsmBackend : public PPCAsmBackend {
219 public:
ELFPPCAsmBackend(const Target & T,const Triple & TT)220 ELFPPCAsmBackend(const Target &T, const Triple &TT) : PPCAsmBackend(T, TT) {}
221
222 std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const223 createObjectTargetWriter() const override {
224 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
225 bool Is64 = TT.isPPC64();
226 return createPPCELFObjectWriter(Is64, OSABI);
227 }
228
229 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
230 };
231
232 class XCOFFPPCAsmBackend : public PPCAsmBackend {
233 public:
XCOFFPPCAsmBackend(const Target & T,const Triple & TT)234 XCOFFPPCAsmBackend(const Target &T, const Triple &TT)
235 : PPCAsmBackend(T, TT) {}
236
237 std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const238 createObjectTargetWriter() const override {
239 return createPPCXCOFFObjectWriter(TT.isArch64Bit());
240 }
241 };
242
243 } // end anonymous namespace
244
245 std::optional<MCFixupKind>
getFixupKind(StringRef Name) const246 ELFPPCAsmBackend::getFixupKind(StringRef Name) const {
247 if (TT.isOSBinFormatELF()) {
248 unsigned Type;
249 if (TT.isPPC64()) {
250 Type = llvm::StringSwitch<unsigned>(Name)
251 #define ELF_RELOC(X, Y) .Case(#X, Y)
252 #include "llvm/BinaryFormat/ELFRelocs/PowerPC64.def"
253 #undef ELF_RELOC
254 .Case("BFD_RELOC_NONE", ELF::R_PPC64_NONE)
255 .Case("BFD_RELOC_16", ELF::R_PPC64_ADDR16)
256 .Case("BFD_RELOC_32", ELF::R_PPC64_ADDR32)
257 .Case("BFD_RELOC_64", ELF::R_PPC64_ADDR64)
258 .Default(-1u);
259 } else {
260 Type = llvm::StringSwitch<unsigned>(Name)
261 #define ELF_RELOC(X, Y) .Case(#X, Y)
262 #include "llvm/BinaryFormat/ELFRelocs/PowerPC.def"
263 #undef ELF_RELOC
264 .Case("BFD_RELOC_NONE", ELF::R_PPC_NONE)
265 .Case("BFD_RELOC_16", ELF::R_PPC_ADDR16)
266 .Case("BFD_RELOC_32", ELF::R_PPC_ADDR32)
267 .Default(-1u);
268 }
269 if (Type != -1u)
270 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
271 }
272 return std::nullopt;
273 }
274
createPPCAsmBackend(const Target & T,const MCSubtargetInfo & STI,const MCRegisterInfo & MRI,const MCTargetOptions & Options)275 MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
276 const MCSubtargetInfo &STI,
277 const MCRegisterInfo &MRI,
278 const MCTargetOptions &Options) {
279 const Triple &TT = STI.getTargetTriple();
280 if (TT.isOSBinFormatXCOFF())
281 return new XCOFFPPCAsmBackend(T, TT);
282
283 return new ELFPPCAsmBackend(T, TT);
284 }
285