1 /* $NetBSD: cpu_subr.c,v 1.110 2024/09/08 10:16:04 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.110 2024/09/08 10:16:04 andvar Exp $"); 38 39 #include "sysmon_envsys.h" 40 41 #ifdef _KERNEL_OPT 42 #include "opt_altivec.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_ppcarch.h" 45 #include "opt_ppccache.h" 46 #include "opt_ppcparam.h" 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/types.h> 53 #include <sys/lwp.h> 54 #include <sys/xcall.h> 55 56 #include <uvm/uvm.h> 57 58 #include <powerpc/pcb.h> 59 #include <powerpc/psl.h> 60 #include <powerpc/spr.h> 61 #include <powerpc/oea/hid.h> 62 #include <powerpc/oea/hid_601.h> 63 #include <powerpc/oea/spr.h> 64 #include <powerpc/oea/cpufeat.h> 65 66 #include <dev/sysmon/sysmonvar.h> 67 68 static void cpu_enable_l2cr(register_t); 69 static void cpu_enable_l3cr(register_t); 70 static void cpu_config_l2cr(int); 71 static void cpu_config_l3cr(int); 72 static void cpu_probe_speed(struct cpu_info *); 73 static void cpu_idlespin(void); 74 static void cpu_set_dfs_xcall(void *, void *); 75 #if NSYSMON_ENVSYS > 0 76 static void cpu_tau_setup(struct cpu_info *); 77 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 78 #endif 79 80 extern void init_scom_speedctl(void); 81 82 int cpu = -1; 83 int ncpus; 84 85 struct fmttab { 86 register_t fmt_mask; 87 register_t fmt_value; 88 const char *fmt_string; 89 }; 90 91 /* 92 * This should be one per CPU but since we only support it on 750 variants it 93 * doesn't really matter since none of them support SMP 94 */ 95 envsys_data_t sensor; 96 97 static const struct fmttab cpu_7450_l2cr_formats[] = { 98 { L2CR_L2E, 0, " disabled" }, 99 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 100 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 102 { L2CR_L2E, ~0, " 256KB L2 cache" }, 103 { L2CR_L2PE, 0, " no parity" }, 104 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 105 { 0, 0, NULL } 106 }; 107 108 static const struct fmttab cpu_7448_l2cr_formats[] = { 109 { L2CR_L2E, 0, " disabled" }, 110 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 111 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 112 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 113 { L2CR_L2E, ~0, " 1MB L2 cache" }, 114 { L2CR_L2PE, 0, " no parity" }, 115 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 116 { 0, 0, NULL } 117 }; 118 119 static const struct fmttab cpu_7457_l2cr_formats[] = { 120 { L2CR_L2E, 0, " disabled" }, 121 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 122 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 123 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 124 { L2CR_L2E, ~0, " 512KB L2 cache" }, 125 { L2CR_L2PE, 0, " no parity" }, 126 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 127 { 0, 0, NULL } 128 }; 129 130 static const struct fmttab cpu_7450_l3cr_formats[] = { 131 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 132 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 133 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 134 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 135 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 136 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 137 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 138 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 139 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 140 { L3CR_L3SIZ, ~0, " L3 cache" }, 141 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 142 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 143 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 144 { L3CR_L3CLK, ~0, " at" }, 145 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 146 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 147 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 148 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 149 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 150 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 151 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 152 { L3CR_L3CLK, ~0, " ratio" }, 153 { 0, 0, NULL }, 154 }; 155 156 static const struct fmttab cpu_ibm750cl_l2cr_formats[] = { 157 { L2CR_L2E, 0, " disabled" }, 158 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 159 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 160 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 161 { 0, ~0, " 256KB" }, 162 { L2CR_L2WT, L2CR_L2WT, " WT" }, 163 { L2CR_L2WT, 0, " WB" }, 164 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 165 { 0, ~0, " L2 cache" }, 166 { 0, 0, NULL } 167 }; 168 169 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 170 { L2CR_L2E, 0, " disabled" }, 171 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 172 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 173 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 174 { 0, ~0, " 512KB" }, 175 { L2CR_L2WT, L2CR_L2WT, " WT" }, 176 { L2CR_L2WT, 0, " WB" }, 177 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 178 { 0, ~0, " L2 cache" }, 179 { 0, 0, NULL } 180 }; 181 182 static const struct fmttab cpu_l2cr_formats[] = { 183 { L2CR_L2E, 0, " disabled" }, 184 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 185 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 186 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 187 { L2CR_L2PE, L2CR_L2PE, " parity" }, 188 { L2CR_L2PE, 0, " no-parity" }, 189 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 190 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 191 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 192 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 193 { L2CR_L2WT, L2CR_L2WT, " WT" }, 194 { L2CR_L2WT, 0, " WB" }, 195 { L2CR_L2E, ~0, " L2 cache" }, 196 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 197 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 198 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 199 { L2CR_L2CLK, ~0, " at" }, 200 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 201 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 202 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 203 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 204 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 205 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 206 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 207 { L2CR_L2CLK, ~0, " ratio" }, 208 { 0, 0, NULL } 209 }; 210 211 static void cpu_fmttab_print(const struct fmttab *, register_t); 212 213 struct cputab { 214 const char name[8]; 215 uint16_t version; 216 uint16_t revfmt; 217 }; 218 #define REVFMT_MAJMIN 1 /* %u.%u */ 219 #define REVFMT_HEX 2 /* 0x%04x */ 220 #define REVFMT_DEC 3 /* %u */ 221 static const struct cputab models[] = { 222 { "601", MPC601, REVFMT_DEC }, 223 { "602", MPC602, REVFMT_DEC }, 224 { "603", MPC603, REVFMT_MAJMIN }, 225 { "603e", MPC603e, REVFMT_MAJMIN }, 226 { "603ev", MPC603ev, REVFMT_MAJMIN }, 227 { "G2", MPCG2, REVFMT_MAJMIN }, 228 { "604", MPC604, REVFMT_MAJMIN }, 229 { "604e", MPC604e, REVFMT_MAJMIN }, 230 { "604ev", MPC604ev, REVFMT_MAJMIN }, 231 { "620", MPC620, REVFMT_HEX }, 232 { "750", MPC750, REVFMT_MAJMIN }, 233 { "750FX", IBM750FX, REVFMT_MAJMIN }, 234 { "750GX", IBM750GX, REVFMT_MAJMIN }, 235 { "7400", MPC7400, REVFMT_MAJMIN }, 236 { "7410", MPC7410, REVFMT_MAJMIN }, 237 { "7450", MPC7450, REVFMT_MAJMIN }, 238 { "7455", MPC7455, REVFMT_MAJMIN }, 239 { "7457", MPC7457, REVFMT_MAJMIN }, 240 { "7447A", MPC7447A, REVFMT_MAJMIN }, 241 { "7448", MPC7448, REVFMT_MAJMIN }, 242 { "8240", MPC8240, REVFMT_MAJMIN }, 243 { "8245", MPC8245, REVFMT_MAJMIN }, 244 { "970", IBM970, REVFMT_MAJMIN }, 245 { "970FX", IBM970FX, REVFMT_MAJMIN }, 246 { "970MP", IBM970MP, REVFMT_MAJMIN }, 247 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 248 { "", 0, REVFMT_HEX } 249 }; 250 251 #include <powerpc/oea/bat.h> 252 extern struct bat battable[]; 253 254 #ifdef MULTIPROCESSOR 255 struct cpu_info cpu_info[CPU_MAXNUM] = { 256 [0] = { 257 .ci_curlwp = &lwp0, 258 .ci_battable = battable, 259 }, 260 }; 261 volatile struct cpu_hatch_data *cpu_hatch_data; 262 volatile int cpu_hatch_stack; 263 #define HATCH_STACK_SIZE 0x1000 264 extern int ticks_per_intr; 265 #include <powerpc/pic/picvar.h> 266 #include <powerpc/pic/ipivar.h> 267 #else 268 struct cpu_info cpu_info[1] = { 269 [0] = { 270 .ci_curlwp = &lwp0, 271 .ci_battable = battable, 272 }, 273 }; 274 #endif /*MULTIPROCESSOR*/ 275 276 int cpu_altivec; 277 register_t cpu_psluserset; 278 register_t cpu_pslusermod; 279 register_t cpu_pslusermask = 0xffff; 280 281 unsigned long oeacpufeat; 282 283 void 284 cpu_features_probe(void) 285 { 286 static bool feature_probe_done; 287 288 u_int pvr, vers; 289 290 if (feature_probe_done) { 291 return; 292 } 293 294 pvr = mfpvr(); 295 vers = pvr >> 16; 296 297 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 298 vers == IBMCELL || vers == IBMPOWER6P5) { 299 oeacpufeat |= OEACPU_64; 300 oeacpufeat |= OEACPU_64_BRIDGE; 301 oeacpufeat |= OEACPU_NOBAT; 302 303 } else if (vers == MPC601) { 304 oeacpufeat |= OEACPU_601; 305 306 } else if (MPC745X_P(vers)) { 307 if (vers != MPC7450) { 308 /* Enable more SPRG registers */ 309 oeacpufeat |= OEACPU_HIGHSPRG; 310 311 /* Enable more BAT registers */ 312 oeacpufeat |= OEACPU_HIGHBAT; 313 314 /* Enable larger BAT registers */ 315 oeacpufeat |= OEACPU_XBSEN; 316 } 317 318 } else if (vers == IBM750FX || vers == IBM750GX) { 319 oeacpufeat |= OEACPU_HIGHBAT; 320 } 321 322 feature_probe_done = true; 323 } 324 325 void 326 cpu_features_enable(void) 327 { 328 static bool feature_enable_done; 329 330 if (feature_enable_done) { 331 return; 332 } 333 334 u_int pvr, vers; 335 336 pvr = mfpvr(); 337 vers = pvr >> 16; 338 339 if (MPC745X_P(vers)) { 340 register_t hid0 = mfspr(SPR_HID0); 341 register_t hid1 = mfspr(SPR_HID1); 342 343 const register_t ohid0 = hid0; 344 345 if (oeacpufeat & OEACPU_HIGHBAT) { 346 hid0 |= HID0_HIGH_BAT_EN; 347 } 348 349 if (oeacpufeat & OEACPU_XBSEN) { 350 hid0 |= HID0_XBSEN; 351 } 352 353 if (hid0 != ohid0) { 354 mtspr(SPR_HID0, hid0); 355 __asm volatile("sync;isync"); 356 } 357 358 /* Enable address broadcasting for MP systems */ 359 hid1 |= HID1_SYNCBE | HID1_ABE; 360 361 mtspr(SPR_HID1, hid1); 362 __asm volatile("sync;isync"); 363 } 364 365 feature_enable_done = true; 366 } 367 368 /* This is to be called from locore.S, and nowhere else. */ 369 370 void 371 cpu_model_init(void) 372 { 373 /* 374 * This is just a wrapper for backwards-compatibility, and will 375 * probably be garbage-collected in the near future. 376 */ 377 cpu_features_probe(); 378 cpu_features_enable(); 379 } 380 381 void 382 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 383 { 384 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 385 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 386 (data & fmt->fmt_mask) == fmt->fmt_value) 387 aprint_normal("%s", fmt->fmt_string); 388 } 389 } 390 391 void 392 cpu_idlespin(void) 393 { 394 register_t msr; 395 396 if (powersave <= 0) 397 return; 398 399 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 400 if (cpu_altivec) 401 __asm volatile("dssall"); 402 #endif 403 404 __asm volatile( 405 "sync;" 406 "mfmsr %0;" 407 "oris %0,%0,%1@h;" /* enter power saving mode */ 408 "mtmsr %0;" 409 "isync;" 410 : "=r"(msr) 411 : "J"(PSL_POW)); 412 } 413 414 void 415 cpu_probe_cache(void) 416 { 417 u_int assoc, pvr, vers; 418 419 pvr = mfpvr(); 420 vers = pvr >> 16; 421 422 423 /* Presently common across almost all implementations. */ 424 curcpu()->ci_ci.dcache_line_size = 32; 425 curcpu()->ci_ci.icache_line_size = 32; 426 427 428 switch (vers) { 429 #define K *1024 430 case IBM750FX: 431 case IBM750GX: 432 case MPC601: 433 case MPC750: 434 case MPC7400: 435 case MPC7447A: 436 case MPC7448: 437 case MPC7450: 438 case MPC7455: 439 case MPC7457: 440 curcpu()->ci_ci.dcache_size = 32 K; 441 curcpu()->ci_ci.icache_size = 32 K; 442 assoc = 8; 443 break; 444 case MPC603: 445 curcpu()->ci_ci.dcache_size = 8 K; 446 curcpu()->ci_ci.icache_size = 8 K; 447 assoc = 2; 448 break; 449 case MPC603e: 450 case MPC603ev: 451 case MPC604: 452 case MPC8240: 453 case MPC8245: 454 case MPCG2: 455 curcpu()->ci_ci.dcache_size = 16 K; 456 curcpu()->ci_ci.icache_size = 16 K; 457 assoc = 4; 458 break; 459 case MPC604e: 460 case MPC604ev: 461 curcpu()->ci_ci.dcache_size = 32 K; 462 curcpu()->ci_ci.icache_size = 32 K; 463 assoc = 4; 464 break; 465 case IBMPOWER3II: 466 curcpu()->ci_ci.dcache_size = 64 K; 467 curcpu()->ci_ci.icache_size = 32 K; 468 curcpu()->ci_ci.dcache_line_size = 128; 469 curcpu()->ci_ci.icache_line_size = 128; 470 assoc = 128; /* not a typo */ 471 break; 472 case IBM970: 473 case IBM970FX: 474 case IBM970MP: 475 curcpu()->ci_ci.dcache_size = 32 K; 476 curcpu()->ci_ci.icache_size = 64 K; 477 curcpu()->ci_ci.dcache_line_size = 128; 478 curcpu()->ci_ci.icache_line_size = 128; 479 assoc = 2; 480 break; 481 482 default: 483 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 484 curcpu()->ci_ci.icache_size = PAGE_SIZE; 485 assoc = 1; 486 #undef K 487 } 488 489 /* 490 * Possibly recolor. 491 */ 492 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 493 } 494 495 struct cpu_info * 496 cpu_attach_common(device_t self, int id) 497 { 498 struct cpu_info *ci; 499 u_int pvr, vers; 500 501 ci = &cpu_info[id]; 502 #ifndef MULTIPROCESSOR 503 /* 504 * If this isn't the primary CPU, print an error message 505 * and just bail out. 506 */ 507 if (id != 0) { 508 aprint_naive("\n"); 509 aprint_normal(": ID %d\n", id); 510 aprint_normal_dev(self, 511 "processor off-line; " 512 "multiprocessor support not present in kernel\n"); 513 return (NULL); 514 } 515 #endif 516 517 ci->ci_cpuid = id; 518 ci->ci_idepth = -1; 519 ci->ci_dev = self; 520 ci->ci_idlespin = cpu_idlespin; 521 522 #ifdef MULTIPROCESSOR 523 /* Register IPI Interrupt */ 524 if ((ipiops.ppc_establish_ipi) && (id == 0)) 525 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 526 #endif 527 528 pvr = mfpvr(); 529 vers = (pvr >> 16) & 0xffff; 530 531 switch (id) { 532 case 0: 533 /* load my cpu_number to PIR */ 534 switch (vers) { 535 case MPC601: 536 case MPC604: 537 case MPC604e: 538 case MPC604ev: 539 case MPC7400: 540 case MPC7410: 541 case MPC7447A: 542 case MPC7448: 543 case MPC7450: 544 case MPC7455: 545 case MPC7457: 546 mtspr(SPR_PIR, id); 547 } 548 cpu_setup(self, ci); 549 break; 550 default: 551 aprint_naive("\n"); 552 if (id >= CPU_MAXNUM) { 553 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 554 panic("cpuattach"); 555 } 556 #ifndef MULTIPROCESSOR 557 aprint_normal(" not configured\n"); 558 return NULL; 559 #else 560 mi_cpu_attach(ci); 561 break; 562 #endif 563 } 564 return (ci); 565 } 566 567 void 568 cpu_setup(device_t self, struct cpu_info *ci) 569 { 570 u_int pvr, vers; 571 const char * const xname = device_xname(self); 572 const char *bitmask; 573 char hidbuf[128]; 574 char model[80]; 575 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 576 char hidbuf_u[128]; 577 const char *bitmasku = NULL; 578 volatile uint64_t hid64_0, hid64_0_save; 579 #endif 580 #if !defined(_ARCH_PPC64) 581 register_t hid0 = 0, hid0_save = 0; 582 #endif 583 584 pvr = mfpvr(); 585 vers = (pvr >> 16) & 0xffff; 586 587 cpu_identify(model, sizeof(model)); 588 aprint_naive("\n"); 589 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 590 cpu_number() == 0 ? " (primary)" : ""); 591 592 /* set the cpu number */ 593 ci->ci_cpuid = cpu_number(); 594 #if defined(_ARCH_PPC64) 595 __asm volatile("mfspr %0,%1" : "=r"(hid64_0) : "K"(SPR_HID0)); 596 hid64_0_save = hid64_0; 597 #else 598 #if defined(PPC_OEA64_BRIDGE) 599 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) 600 hid64_0_save = hid64_0 = mfspr(SPR_HID0); 601 else 602 #endif 603 hid0_save = hid0 = mfspr(SPR_HID0); 604 #endif 605 606 607 cpu_probe_cache(); 608 609 /* 610 * Configure power-saving mode. 611 */ 612 switch (vers) { 613 #if !defined(_ARCH_PPC64) 614 case MPC604: 615 case MPC604e: 616 case MPC604ev: 617 /* 618 * Do not have HID0 support settings, but can support 619 * MSR[POW] off 620 */ 621 powersave = 1; 622 break; 623 624 case MPC603: 625 case MPC603e: 626 case MPC603ev: 627 case MPC7400: 628 case MPC7410: 629 case MPC8240: 630 case MPC8245: 631 case MPCG2: 632 /* Select DOZE mode. */ 633 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 634 hid0 |= HID0_DOZE | HID0_DPM; 635 powersave = 1; 636 break; 637 638 case MPC750: 639 case IBM750FX: 640 case IBM750GX: 641 /* Select NAP mode. */ 642 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 643 hid0 |= HID0_NAP | HID0_DPM; 644 powersave = 1; 645 break; 646 647 case MPC7447A: 648 case MPC7448: 649 case MPC7457: 650 case MPC7455: 651 case MPC7450: 652 /* Enable the 7450 branch caches */ 653 hid0 |= HID0_SGE | HID0_BTIC; 654 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 655 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 656 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 657 hid0 &= ~HID0_BTIC; 658 /* Select NAP mode. */ 659 hid0 &= ~HID0_SLEEP; 660 /* XXX my quicksilver hangs if nap is enabled */ 661 if (vers != MPC7450) { 662 hid0 |= HID0_NAP | HID0_DPM; 663 powersave = 1; 664 } 665 break; 666 #endif 667 668 case IBM970: 669 case IBM970FX: 670 case IBM970MP: 671 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 672 #if !defined(_ARCH_PPC64) 673 KASSERT((oeacpufeat & OEACPU_64_BRIDGE) != 0); 674 #endif 675 hid64_0 &= ~(HID0_64_DOZE | HID0_64_NAP | HID0_64_DEEPNAP); 676 hid64_0 |= HID0_64_NAP | HID0_64_DPM | HID0_64_EX_TBEN | 677 HID0_64_TB_CTRL | HID0_64_EN_MCHK; 678 powersave = 1; 679 break; 680 #endif 681 case IBMPOWER3II: 682 default: 683 /* No power-saving mode is available. */ ; 684 } 685 686 #ifdef NAPMODE 687 switch (vers) { 688 case IBM750FX: 689 case IBM750GX: 690 case MPC750: 691 case MPC7400: 692 /* Select NAP mode. */ 693 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 694 hid0 |= HID0_NAP; 695 break; 696 } 697 #endif 698 699 switch (vers) { 700 case IBM750FX: 701 case IBM750GX: 702 case MPC750: 703 hid0 &= ~HID0_DBP; /* XXX correct? */ 704 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 705 break; 706 707 case MPC7400: 708 case MPC7410: 709 hid0 &= ~HID0_SPD; 710 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 711 hid0 |= HID0_EIEC; 712 break; 713 } 714 715 /* 716 * according to the 603e manual this is necessary for an external L2 717 * cache to work properly 718 */ 719 switch (vers) { 720 case MPC603e: 721 hid0 |= HID0_ABE; 722 } 723 724 #if defined(_ARCH_PPC64) || defined(PPC_OEA64_BRIDGE) 725 #if defined(PPC_OEA64_BRIDGE) 726 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 727 #endif 728 if (hid64_0 != hid64_0_save) { 729 mtspr64(SPR_HID0, hid64_0); 730 } 731 #if defined(PPC_OEA64_BRIDGE) 732 } else { 733 #endif 734 #endif 735 736 #if !defined(_ARCH_PPC64) 737 if (hid0 != hid0_save) { 738 mtspr(SPR_HID0, hid0); 739 __asm volatile("sync;isync"); 740 } 741 #endif 742 #if defined(PPC_OEA64_BRIDGE) 743 } 744 #endif 745 746 switch (vers) { 747 case MPC601: 748 bitmask = HID0_601_BITMASK; 749 break; 750 case MPC7447A: 751 case MPC7448: 752 case MPC7450: 753 case MPC7455: 754 case MPC7457: 755 bitmask = HID0_7450_BITMASK; 756 break; 757 case IBM970: 758 case IBM970FX: 759 case IBM970MP: 760 bitmask = HID0_970_BITMASK; 761 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 762 bitmasku = HID0_970_BITMASK_U; 763 #endif 764 break; 765 default: 766 bitmask = HID0_BITMASK; 767 break; 768 } 769 770 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 771 if (bitmasku != NULL) { 772 snprintb(hidbuf, sizeof hidbuf, bitmask, hid64_0 & 0xffffffff); 773 snprintb(hidbuf_u, sizeof hidbuf_u, bitmasku, hid64_0 >> 32); 774 aprint_normal_dev(self, "HID0 %s %s, powersave: %d\n", 775 hidbuf_u, hidbuf, powersave); 776 } else 777 #endif 778 { 779 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 780 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", 781 hidbuf, powersave); 782 } 783 784 ci->ci_khz = 0; 785 786 /* 787 * Display speed and cache configuration. 788 */ 789 switch (vers) { 790 case MPC604: 791 case MPC604e: 792 case MPC604ev: 793 case MPC750: 794 case IBM750FX: 795 case IBM750GX: 796 case MPC7400: 797 case MPC7410: 798 case MPC7447A: 799 case MPC7448: 800 case MPC7450: 801 case MPC7455: 802 case MPC7457: 803 aprint_normal_dev(self, ""); 804 cpu_probe_speed(ci); 805 aprint_normal("%u.%02u MHz", 806 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 807 switch (vers) { 808 case MPC7450: /* 7441 does not have L3! */ 809 case MPC7455: /* 7445 does not have L3! */ 810 case MPC7457: /* 7447 does not have L3! */ 811 cpu_config_l3cr(vers); 812 break; 813 case IBM750FX: 814 case IBM750GX: 815 case MPC750: 816 case MPC7400: 817 case MPC7410: 818 case MPC7447A: 819 case MPC7448: 820 cpu_config_l2cr(pvr); 821 break; 822 default: 823 break; 824 } 825 aprint_normal("\n"); 826 break; 827 } 828 829 #if NSYSMON_ENVSYS > 0 830 /* 831 * Attach MPC750 temperature sensor to the envsys subsystem. 832 * XXX the 74xx series also has this sensor, but it is not 833 * XXX supported by Motorola and may return values that are off by 834 * XXX 35-55 degrees C. 835 */ 836 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 837 cpu_tau_setup(ci); 838 #endif 839 840 #if defined(PPC_OEA64) || defined(PPC_OEA64_BRIDGE) 841 if (vers == IBM970MP) 842 init_scom_speedctl(); 843 #endif 844 845 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 846 NULL, xname, "clock"); 847 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 848 NULL, xname, "traps"); 849 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 850 &ci->ci_ev_traps, xname, "kernel DSI traps"); 851 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 852 &ci->ci_ev_traps, xname, "user DSI traps"); 853 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 854 &ci->ci_ev_udsi, xname, "user DSI failures"); 855 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 856 &ci->ci_ev_traps, xname, "kernel ISI traps"); 857 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 858 &ci->ci_ev_traps, xname, "user ISI traps"); 859 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 860 &ci->ci_ev_isi, xname, "user ISI failures"); 861 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 862 &ci->ci_ev_traps, xname, "system call traps"); 863 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 864 &ci->ci_ev_traps, xname, "PGM traps"); 865 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 866 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 867 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 868 &ci->ci_ev_fpu, xname, "FPU context switches"); 869 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 870 &ci->ci_ev_traps, xname, "user alignment traps"); 871 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 872 &ci->ci_ev_ali, xname, "user alignment failures"); 873 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 874 &ci->ci_ev_umchk, xname, "user MCHK failures"); 875 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 876 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 877 #ifdef ALTIVEC 878 if (cpu_altivec) { 879 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 880 &ci->ci_ev_vec, xname, "AltiVec context switches"); 881 } 882 #endif 883 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 884 NULL, xname, "IPIs"); 885 } 886 887 /* 888 * According to a document labeled "PVR Register Settings": 889 ** For integrated microprocessors the PVR register inside the device 890 ** will identify the version of the microprocessor core. You must also 891 ** read the Device ID, PCI register 02, to identify the part and the 892 ** Revision ID, PCI register 08, to identify the revision of the 893 ** integrated microprocessor. 894 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 895 */ 896 897 void 898 cpu_identify(char *str, size_t len) 899 { 900 u_int pvr, major, minor; 901 uint16_t vers, rev, revfmt; 902 const struct cputab *cp; 903 size_t n; 904 905 pvr = mfpvr(); 906 vers = pvr >> 16; 907 rev = pvr; 908 909 switch (vers) { 910 case MPC7410: 911 minor = (pvr >> 0) & 0xff; 912 major = minor <= 4 ? 1 : 2; 913 break; 914 case MPCG2: /*XXX see note above */ 915 major = (pvr >> 4) & 0xf; 916 minor = (pvr >> 0) & 0xf; 917 break; 918 default: 919 major = (pvr >> 8) & 0xf; 920 minor = (pvr >> 0) & 0xf; 921 } 922 923 for (cp = models; cp->name[0] != '\0'; cp++) { 924 if (cp->version == vers) 925 break; 926 } 927 928 if (cpu == -1) 929 cpu = vers; 930 931 revfmt = cp->revfmt; 932 if (rev == MPC750 && pvr == 15) { 933 revfmt = REVFMT_HEX; 934 } 935 936 if (cp->name[0] != '\0') { 937 n = snprintf(str, len, "%s (Revision ", cp->name); 938 } else { 939 n = snprintf(str, len, "Version %#x (Revision ", vers); 940 } 941 if (len > n) { 942 switch (revfmt) { 943 case REVFMT_MAJMIN: 944 snprintf(str + n, len - n, "%u.%u)", major, minor); 945 break; 946 case REVFMT_HEX: 947 snprintf(str + n, len - n, "0x%04x)", rev); 948 break; 949 case REVFMT_DEC: 950 snprintf(str + n, len - n, "%u)", rev); 951 break; 952 } 953 } 954 } 955 956 #ifdef L2CR_CONFIG 957 u_int l2cr_config = L2CR_CONFIG; 958 #else 959 u_int l2cr_config = 0; 960 #endif 961 962 #ifdef L3CR_CONFIG 963 u_int l3cr_config = L3CR_CONFIG; 964 #else 965 u_int l3cr_config = 0; 966 #endif 967 968 void 969 cpu_enable_l2cr(register_t l2cr) 970 { 971 register_t msr, x; 972 uint16_t vers; 973 974 vers = mfpvr() >> 16; 975 976 /* Disable interrupts and set the cache config bits. */ 977 msr = mfmsr(); 978 mtmsr(msr & ~PSL_EE); 979 #ifdef ALTIVEC 980 if (cpu_altivec) 981 __asm volatile("dssall"); 982 #endif 983 __asm volatile("sync"); 984 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 985 __asm volatile("sync"); 986 987 /* Wait for L2 clock to be stable (640 L2 clocks). */ 988 delay(100); 989 990 /* Invalidate all L2 contents. */ 991 if (MPC745X_P(vers)) { 992 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 993 do { 994 x = mfspr(SPR_L2CR); 995 } while (x & L2CR_L2I); 996 } else { 997 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 998 do { 999 x = mfspr(SPR_L2CR); 1000 } while (x & L2CR_L2IP); 1001 } 1002 /* Enable L2 cache. */ 1003 l2cr |= L2CR_L2E; 1004 mtspr(SPR_L2CR, l2cr); 1005 mtmsr(msr); 1006 } 1007 1008 void 1009 cpu_enable_l3cr(register_t l3cr) 1010 { 1011 register_t x; 1012 1013 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 1014 1015 /* 1016 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 1017 * L3CLKEN. (also mask off reserved bits in case they were included 1018 * in L3CR_CONFIG) 1019 */ 1020 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 1021 mtspr(SPR_L3CR, l3cr); 1022 1023 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 1024 l3cr |= 0x04000000; 1025 mtspr(SPR_L3CR, l3cr); 1026 1027 /* 3: Set L3CLKEN to 1*/ 1028 l3cr |= L3CR_L3CLKEN; 1029 mtspr(SPR_L3CR, l3cr); 1030 1031 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 1032 __asm volatile("dssall;sync"); 1033 /* L3 cache is already disabled, no need to clear L3E */ 1034 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 1035 do { 1036 x = mfspr(SPR_L3CR); 1037 } while (x & L3CR_L3I); 1038 1039 /* 6: Clear L3CLKEN to 0 */ 1040 l3cr &= ~L3CR_L3CLKEN; 1041 mtspr(SPR_L3CR, l3cr); 1042 1043 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 1044 __asm volatile("sync"); 1045 delay(100); 1046 1047 /* 8: Set L3E and L3CLKEN */ 1048 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 1049 mtspr(SPR_L3CR, l3cr); 1050 1051 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 1052 __asm volatile("sync"); 1053 delay(100); 1054 } 1055 1056 void 1057 cpu_config_l2cr(int pvr) 1058 { 1059 register_t l2cr; 1060 u_int vers = (pvr >> 16) & 0xffff; 1061 1062 l2cr = mfspr(SPR_L2CR); 1063 1064 /* 1065 * For MP systems, the firmware may only configure the L2 cache 1066 * on the first CPU. In this case, assume that the other CPUs 1067 * should use the same value for L2CR. 1068 */ 1069 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1070 l2cr_config = l2cr; 1071 } 1072 1073 /* 1074 * Configure L2 cache if not enabled. 1075 */ 1076 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1077 cpu_enable_l2cr(l2cr_config); 1078 l2cr = mfspr(SPR_L2CR); 1079 } 1080 1081 if ((l2cr & L2CR_L2E) == 0) { 1082 aprint_normal(" L2 cache present but not enabled "); 1083 return; 1084 } 1085 aprint_normal(","); 1086 1087 switch (vers) { 1088 case IBM750FX: 1089 case IBM750GX: 1090 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1091 break; 1092 case MPC750: 1093 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 1094 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 1095 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1096 } else if ((pvr & 0xfffff0e0) == 0x00087000 /* IBM750CL */) { 1097 cpu_fmttab_print(cpu_ibm750cl_l2cr_formats, l2cr); 1098 } else { 1099 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1100 } 1101 break; 1102 case MPC7447A: 1103 case MPC7457: 1104 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1105 return; 1106 case MPC7448: 1107 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1108 return; 1109 case MPC7450: 1110 case MPC7455: 1111 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1112 break; 1113 default: 1114 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1115 break; 1116 } 1117 } 1118 1119 void 1120 cpu_config_l3cr(int vers) 1121 { 1122 register_t l2cr; 1123 register_t l3cr; 1124 1125 l2cr = mfspr(SPR_L2CR); 1126 1127 /* 1128 * For MP systems, the firmware may only configure the L2 cache 1129 * on the first CPU. In this case, assume that the other CPUs 1130 * should use the same value for L2CR. 1131 */ 1132 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1133 l2cr_config = l2cr; 1134 } 1135 1136 /* 1137 * Configure L2 cache if not enabled. 1138 */ 1139 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1140 cpu_enable_l2cr(l2cr_config); 1141 l2cr = mfspr(SPR_L2CR); 1142 } 1143 1144 aprint_normal(","); 1145 switch (vers) { 1146 case MPC7447A: 1147 case MPC7457: 1148 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1149 return; 1150 case MPC7448: 1151 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1152 return; 1153 default: 1154 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1155 break; 1156 } 1157 1158 l3cr = mfspr(SPR_L3CR); 1159 1160 /* 1161 * For MP systems, the firmware may only configure the L3 cache 1162 * on the first CPU. In this case, assume that the other CPUs 1163 * should use the same value for L3CR. 1164 */ 1165 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 1166 l3cr_config = l3cr; 1167 } 1168 1169 /* 1170 * Configure L3 cache if not enabled. 1171 */ 1172 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1173 cpu_enable_l3cr(l3cr_config); 1174 l3cr = mfspr(SPR_L3CR); 1175 } 1176 1177 if (l3cr & L3CR_L3E) { 1178 aprint_normal(","); 1179 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1180 } 1181 } 1182 1183 void 1184 cpu_probe_speed(struct cpu_info *ci) 1185 { 1186 uint64_t cps; 1187 1188 mtspr(SPR_MMCR0, MMCR0_FC); 1189 mtspr(SPR_PMC1, 0); 1190 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1191 delay(100000); 1192 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1193 1194 mtspr(SPR_MMCR0, MMCR0_FC); 1195 1196 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1197 } 1198 1199 /* 1200 * Read the Dynamic Frequency Switching state and return a divisor for 1201 * the maximum frequency. 1202 */ 1203 int 1204 cpu_get_dfs(void) 1205 { 1206 u_int pvr, vers; 1207 1208 pvr = mfpvr(); 1209 vers = pvr >> 16; 1210 1211 switch (vers) { 1212 case MPC7448: 1213 if (mfspr(SPR_HID1) & HID1_DFS4) 1214 return 4; 1215 /* FALLTHROUGH */ 1216 case MPC7447A: 1217 if (mfspr(SPR_HID1) & HID1_DFS2) 1218 return 2; 1219 } 1220 return 1; 1221 } 1222 1223 /* 1224 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1225 */ 1226 void 1227 cpu_set_dfs(int div) 1228 { 1229 u_int dfs_mask, pvr, vers; 1230 1231 pvr = mfpvr(); 1232 vers = pvr >> 16; 1233 dfs_mask = 0; 1234 1235 switch (vers) { 1236 case MPC7448: 1237 dfs_mask |= HID1_DFS4; 1238 /* FALLTHROUGH */ 1239 case MPC7447A: 1240 dfs_mask |= HID1_DFS2; 1241 break; 1242 default: 1243 printf("cpu_set_dfs: DFS not supported\n"); 1244 return; 1245 1246 } 1247 #ifdef MULTIPROCESSOR 1248 uint64_t where; 1249 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1250 xc_wait(where); 1251 #else 1252 cpu_set_dfs_xcall(&div, &dfs_mask); 1253 #endif 1254 } 1255 1256 static void 1257 cpu_set_dfs_xcall(void *arg1, void *arg2) 1258 { 1259 u_int dfs_mask, hid1, old_hid1; 1260 int *divisor, s; 1261 1262 divisor = arg1; 1263 dfs_mask = *(u_int *)arg2; 1264 1265 s = splhigh(); 1266 hid1 = old_hid1 = mfspr(SPR_HID1); 1267 1268 switch (*divisor) { 1269 case 1: 1270 hid1 &= ~dfs_mask; 1271 break; 1272 case 2: 1273 hid1 &= ~(dfs_mask & HID1_DFS4); 1274 hid1 |= dfs_mask & HID1_DFS2; 1275 break; 1276 case 4: 1277 hid1 &= ~(dfs_mask & HID1_DFS2); 1278 hid1 |= dfs_mask & HID1_DFS4; 1279 break; 1280 } 1281 1282 if (hid1 != old_hid1) { 1283 __asm volatile("sync"); 1284 mtspr(SPR_HID1, hid1); 1285 __asm volatile("sync;isync"); 1286 } 1287 1288 splx(s); 1289 } 1290 1291 #if NSYSMON_ENVSYS > 0 1292 void 1293 cpu_tau_setup(struct cpu_info *ci) 1294 { 1295 struct sysmon_envsys *sme; 1296 int error, therm_delay; 1297 1298 mtspr(SPR_THRM1, SPR_THRM_VALID); 1299 mtspr(SPR_THRM2, 0); 1300 1301 /* 1302 * we need to figure out how much 20+us in units of CPU clock cycles 1303 * are 1304 */ 1305 1306 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1307 1308 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1309 1310 sme = sysmon_envsys_create(); 1311 1312 sensor.units = ENVSYS_STEMP; 1313 sensor.state = ENVSYS_SINVALID; 1314 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1315 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1316 sysmon_envsys_destroy(sme); 1317 return; 1318 } 1319 1320 sme->sme_name = device_xname(ci->ci_dev); 1321 sme->sme_cookie = ci; 1322 sme->sme_refresh = cpu_tau_refresh; 1323 1324 if ((error = sysmon_envsys_register(sme)) != 0) { 1325 aprint_error_dev(ci->ci_dev, 1326 " unable to register with sysmon (%d)\n", error); 1327 sysmon_envsys_destroy(sme); 1328 } 1329 } 1330 1331 /* Find the temperature of the CPU. */ 1332 void 1333 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1334 { 1335 int i, threshold, count; 1336 1337 threshold = 64; /* Half of the 7-bit sensor range */ 1338 1339 /* Successive-approximation code adapted from Motorola 1340 * application note AN1800/D, "Programming the Thermal Assist 1341 * Unit in the MPC750 Microprocessor". 1342 */ 1343 for (i = 5; i >= 0 ; i--) { 1344 mtspr(SPR_THRM1, 1345 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1346 count = 0; 1347 while ((count < 100000) && 1348 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1349 count++; 1350 delay(1); 1351 } 1352 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1353 /* The interrupt bit was set, meaning the 1354 * temperature was above the threshold 1355 */ 1356 threshold += 1 << i; 1357 } else { 1358 /* Temperature was below the threshold */ 1359 threshold -= 1 << i; 1360 } 1361 } 1362 threshold += 2; 1363 1364 /* Convert the temperature in degrees C to microkelvin */ 1365 edata->value_cur = (threshold * 1000000) + 273150000; 1366 edata->state = ENVSYS_SVALID; 1367 } 1368 #endif /* NSYSMON_ENVSYS > 0 */ 1369 1370 #ifdef MULTIPROCESSOR 1371 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1372 1373 int 1374 cpu_spinup(device_t self, struct cpu_info *ci) 1375 { 1376 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1377 struct pglist mlist; 1378 int i, error; 1379 char *hp; 1380 1381 KASSERT(ci != curcpu()); 1382 1383 /* Now allocate a hatch stack */ 1384 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1385 &mlist, 1, 1); 1386 if (error) { 1387 aprint_error(": unable to allocate hatch stack\n"); 1388 return -1; 1389 } 1390 1391 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1392 memset(hp, 0, HATCH_STACK_SIZE); 1393 1394 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1395 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1396 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1397 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1398 ci->ci_battable = battable; 1399 1400 cpu_hatch_data = h; 1401 h->hatch_running = 0; 1402 h->hatch_self = self; 1403 h->hatch_ci = ci; 1404 h->hatch_pir = ci->ci_cpuid; 1405 1406 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1407 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1408 1409 /* copy special registers */ 1410 1411 h->hatch_hid0 = mfspr(SPR_HID0); 1412 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 1413 h->hatch_hid1 = mfspr(SPR_HID1); 1414 h->hatch_hid4 = mfspr(SPR_HID4); 1415 h->hatch_hid5 = mfspr(SPR_HID5); 1416 #endif 1417 1418 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1419 for (i = 0; i < 16; i++) { 1420 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1421 "r"(i << ADDR_SR_SHFT)); 1422 } 1423 if (oeacpufeat & OEACPU_64) 1424 h->hatch_asr = mfspr(SPR_ASR); 1425 else 1426 h->hatch_asr = 0; 1427 1428 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1429 /* copy the bat regs */ 1430 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1431 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1432 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1433 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1434 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1435 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1436 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1437 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1438 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1439 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1440 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1441 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1442 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1443 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1444 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1445 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1446 __asm volatile ("sync; isync"); 1447 } 1448 1449 if (md_setup_trampoline(h, ci) == -1) 1450 return -1; 1451 md_presync_timebase(h); 1452 md_start_timebase(h); 1453 1454 /* wait for secondary printf */ 1455 1456 delay(200000); 1457 1458 #ifdef CACHE_PROTO_MEI 1459 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1460 __asm volatile ("sync; isync"); 1461 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1462 __asm volatile ("sync; isync"); 1463 #endif 1464 int hatch_bail = 0; 1465 while ((h->hatch_running < 1) && (hatch_bail < 100000)) { 1466 delay(1); 1467 hatch_bail++; 1468 #ifdef CACHE_PROTO_MEI 1469 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1470 __asm volatile ("sync; isync"); 1471 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1472 __asm volatile ("sync; isync"); 1473 #endif 1474 } 1475 if (h->hatch_running < 1) { 1476 #ifdef CACHE_PROTO_MEI 1477 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1478 __asm volatile ("sync; isync"); 1479 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1480 __asm volatile ("sync; isync"); 1481 #endif 1482 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1483 ci->ci_cpuid, cpu_spinstart_ack); 1484 console_debugger(); 1485 return -1; 1486 } 1487 1488 return 0; 1489 } 1490 1491 static volatile int start_secondary_cpu; 1492 1493 register_t 1494 cpu_hatch(void) 1495 { 1496 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1497 struct cpu_info * const ci = h->hatch_ci; 1498 struct pcb *pcb; 1499 u_int msr; 1500 int i; 1501 1502 /* Initialize timebase. */ 1503 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1504 1505 /* 1506 * Set PIR (Processor Identification Register). i.e. whoami 1507 * Note that PIR is read-only on some CPU versions, so we write to it 1508 * only if it has a different value than we need. 1509 */ 1510 1511 msr = mfspr(SPR_PIR); 1512 if (msr != h->hatch_pir) 1513 mtspr(SPR_PIR, h->hatch_pir); 1514 1515 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1516 curlwp = ci->ci_curlwp; 1517 cpu_spinstart_ack = 0; 1518 1519 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1520 /* Initialize MMU. */ 1521 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1522 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1523 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1524 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1525 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1526 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1527 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1528 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1529 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1530 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1531 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1532 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1533 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1534 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1535 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1536 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1537 } 1538 1539 #ifdef PPC_OEA64_BRIDGE 1540 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 1541 1542 mtspr64(SPR_HID0, h->hatch_hid0); 1543 mtspr64(SPR_HID1, h->hatch_hid1); 1544 mtspr64(SPR_HID4, h->hatch_hid4); 1545 mtspr64(SPR_HID5, h->hatch_hid5); 1546 mtspr64(SPR_HIOR, 0); 1547 } else 1548 #endif 1549 mtspr(SPR_HID0, h->hatch_hid0); 1550 1551 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1552 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1553 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1554 } 1555 1556 __asm volatile ("sync"); 1557 for (i = 0; i < 16; i++) 1558 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1559 __asm volatile ("sync; isync"); 1560 1561 if (oeacpufeat & OEACPU_64) 1562 mtspr(SPR_ASR, h->hatch_asr); 1563 1564 cpu_spinstart_ack = 1; 1565 __asm ("ptesync"); 1566 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1567 __asm volatile ("sync; isync"); 1568 1569 cpu_spinstart_ack = 5; 1570 for (i = 0; i < 16; i++) 1571 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1572 "r"(i << ADDR_SR_SHFT)); 1573 1574 /* Enable I/D address translations. */ 1575 msr = mfmsr(); 1576 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1577 mtmsr(msr); 1578 __asm volatile ("sync; isync"); 1579 cpu_spinstart_ack = 2; 1580 1581 md_sync_timebase(h); 1582 1583 cpu_setup(h->hatch_self, ci); 1584 1585 h->hatch_running = 1; 1586 __asm volatile ("sync; isync"); 1587 1588 while (start_secondary_cpu == 0) 1589 ; 1590 1591 __asm volatile ("sync; isync"); 1592 1593 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1594 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1595 1596 md_setup_interrupts(); 1597 1598 ci->ci_ipending = 0; 1599 ci->ci_cpl = 0; 1600 1601 mtmsr(mfmsr() | PSL_EE); 1602 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1603 return pcb->pcb_sp; 1604 } 1605 1606 void 1607 cpu_boot_secondary_processors(void) 1608 { 1609 start_secondary_cpu = 1; 1610 __asm volatile ("sync"); 1611 } 1612 1613 #endif /*MULTIPROCESSOR*/ 1614