1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/agp_backend.h> 64 #include <linux/atomic.h> 65 #include <linux/wait.h> 66 #include <linux/list.h> 67 #include <linux/kref.h> 68 #include <linux/interval_tree.h> 69 #include <linux/hashtable.h> 70 #include <linux/dma-fence.h> 71 72 #ifdef CONFIG_MMU_NOTIFIER 73 #include <linux/mmu_notifier.h> 74 #endif 75 76 #include <drm/ttm/ttm_bo.h> 77 #include <drm/ttm/ttm_placement.h> 78 #include <drm/ttm/ttm_execbuf_util.h> 79 80 #include <drm/drm_gem.h> 81 #include <drm/drm_audio_component.h> 82 #include <drm/drm_suballoc.h> 83 #include <drm/drm_legacy.h> 84 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/rasops/rasops.h> 88 89 #include <dev/pci/pcivar.h> 90 91 #ifdef __sparc64__ 92 #include <machine/fbvar.h> 93 #endif 94 95 #include "radeon_family.h" 96 #include "radeon_mode.h" 97 #include "radeon_reg.h" 98 99 /* 100 * Modules parameters. 101 */ 102 extern int radeon_no_wb; 103 extern int radeon_modeset; 104 extern int radeon_dynclks; 105 extern int radeon_r4xx_atom; 106 extern int radeon_agpmode; 107 extern int radeon_vram_limit; 108 extern int radeon_gart_size; 109 extern int radeon_benchmarking; 110 extern int radeon_testing; 111 extern int radeon_connector_table; 112 extern int radeon_tv; 113 extern int radeon_audio; 114 extern int radeon_disp_priority; 115 extern int radeon_hw_i2c; 116 extern int radeon_pcie_gen2; 117 extern int radeon_msi; 118 extern int radeon_lockup_timeout; 119 extern int radeon_fastfb; 120 extern int radeon_dpm; 121 extern int radeon_aspm; 122 extern int radeon_runtime_pm; 123 extern int radeon_hard_reset; 124 extern int radeon_vm_size; 125 extern int radeon_vm_block_size; 126 extern int radeon_deep_color; 127 extern int radeon_use_pflipirq; 128 extern int radeon_bapm; 129 extern int radeon_backlight; 130 extern int radeon_auxch; 131 extern int radeon_uvd; 132 extern int radeon_vce; 133 extern int radeon_si_support; 134 extern int radeon_cik_support; 135 136 /* 137 * Copy from radeon_drv.h so we don't have to include both and have conflicting 138 * symbol; 139 */ 140 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 141 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 142 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 143 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 144 #define RADEON_IB_POOL_SIZE 16 145 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 146 #define RADEON_BIOS_NUM_SCRATCH 8 147 148 /* internal ring indices */ 149 /* r1xx+ has gfx CP ring */ 150 #define RADEON_RING_TYPE_GFX_INDEX 0 151 152 /* cayman has 2 compute CP rings */ 153 #define CAYMAN_RING_TYPE_CP1_INDEX 1 154 #define CAYMAN_RING_TYPE_CP2_INDEX 2 155 156 /* R600+ has an async dma ring */ 157 #define R600_RING_TYPE_DMA_INDEX 3 158 /* cayman add a second async dma ring */ 159 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 160 161 /* R600+ */ 162 #define R600_RING_TYPE_UVD_INDEX 5 163 164 /* TN+ */ 165 #define TN_RING_TYPE_VCE1_INDEX 6 166 #define TN_RING_TYPE_VCE2_INDEX 7 167 168 /* max number of rings */ 169 #define RADEON_NUM_RINGS 8 170 171 /* number of hw syncs before falling back on blocking */ 172 #define RADEON_NUM_SYNCS 4 173 174 /* hardcode those limit for now */ 175 #define RADEON_VA_IB_OFFSET (1 << 20) 176 #define RADEON_VA_RESERVED_SIZE (8 << 20) 177 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 178 179 /* hard reset data */ 180 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 181 182 /* reset flags */ 183 #define RADEON_RESET_GFX (1 << 0) 184 #define RADEON_RESET_COMPUTE (1 << 1) 185 #define RADEON_RESET_DMA (1 << 2) 186 #define RADEON_RESET_CP (1 << 3) 187 #define RADEON_RESET_GRBM (1 << 4) 188 #define RADEON_RESET_DMA1 (1 << 5) 189 #define RADEON_RESET_RLC (1 << 6) 190 #define RADEON_RESET_SEM (1 << 7) 191 #define RADEON_RESET_IH (1 << 8) 192 #define RADEON_RESET_VMC (1 << 9) 193 #define RADEON_RESET_MC (1 << 10) 194 #define RADEON_RESET_DISPLAY (1 << 11) 195 196 /* CG block flags */ 197 #define RADEON_CG_BLOCK_GFX (1 << 0) 198 #define RADEON_CG_BLOCK_MC (1 << 1) 199 #define RADEON_CG_BLOCK_SDMA (1 << 2) 200 #define RADEON_CG_BLOCK_UVD (1 << 3) 201 #define RADEON_CG_BLOCK_VCE (1 << 4) 202 #define RADEON_CG_BLOCK_HDP (1 << 5) 203 #define RADEON_CG_BLOCK_BIF (1 << 6) 204 205 /* CG flags */ 206 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 207 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 208 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 209 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 210 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 211 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 212 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 213 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 214 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 215 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 216 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 217 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 218 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 219 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 220 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 221 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 222 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 223 224 /* PG flags */ 225 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 226 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 227 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 228 #define RADEON_PG_SUPPORT_UVD (1 << 3) 229 #define RADEON_PG_SUPPORT_VCE (1 << 4) 230 #define RADEON_PG_SUPPORT_CP (1 << 5) 231 #define RADEON_PG_SUPPORT_GDS (1 << 6) 232 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 233 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 234 #define RADEON_PG_SUPPORT_ACP (1 << 9) 235 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 236 237 /* max cursor sizes (in pixels) */ 238 #define CURSOR_WIDTH 64 239 #define CURSOR_HEIGHT 64 240 241 #define CIK_CURSOR_WIDTH 128 242 #define CIK_CURSOR_HEIGHT 128 243 244 /* 245 * Errata workarounds. 246 */ 247 enum radeon_pll_errata { 248 CHIP_ERRATA_R300_CG = 0x00000001, 249 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 250 CHIP_ERRATA_PLL_DELAY = 0x00000004 251 }; 252 253 254 struct radeon_device; 255 256 257 /* 258 * BIOS. 259 */ 260 bool radeon_get_bios(struct radeon_device *rdev); 261 262 /* 263 * Dummy page 264 */ 265 struct radeon_dummy_page { 266 uint64_t entry; 267 struct drm_dmamem *dmah; 268 dma_addr_t addr; 269 }; 270 int radeon_dummy_page_init(struct radeon_device *rdev); 271 void radeon_dummy_page_fini(struct radeon_device *rdev); 272 273 274 /* 275 * Clocks 276 */ 277 struct radeon_clock { 278 struct radeon_pll p1pll; 279 struct radeon_pll p2pll; 280 struct radeon_pll dcpll; 281 struct radeon_pll spll; 282 struct radeon_pll mpll; 283 /* 10 Khz units */ 284 uint32_t default_mclk; 285 uint32_t default_sclk; 286 uint32_t default_dispclk; 287 uint32_t current_dispclk; 288 uint32_t dp_extclk; 289 uint32_t max_pixel_clock; 290 uint32_t vco_freq; 291 }; 292 293 /* 294 * Power management 295 */ 296 int radeon_pm_init(struct radeon_device *rdev); 297 int radeon_pm_late_init(struct radeon_device *rdev); 298 void radeon_pm_fini(struct radeon_device *rdev); 299 void radeon_pm_compute_clocks(struct radeon_device *rdev); 300 void radeon_pm_suspend(struct radeon_device *rdev); 301 void radeon_pm_resume(struct radeon_device *rdev); 302 void radeon_combios_get_power_modes(struct radeon_device *rdev); 303 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 304 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 305 u8 clock_type, 306 u32 clock, 307 bool strobe_mode, 308 struct atom_clock_dividers *dividers); 309 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 310 u32 clock, 311 bool strobe_mode, 312 struct atom_mpll_param *mpll_param); 313 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 314 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 315 u16 voltage_level, u8 voltage_type, 316 u32 *gpio_value, u32 *gpio_mask); 317 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 318 u32 eng_clock, u32 mem_clock); 319 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 320 u8 voltage_type, u16 *voltage_step); 321 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 322 u16 voltage_id, u16 *voltage); 323 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 324 u16 *voltage, 325 u16 leakage_idx); 326 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 327 u16 *leakage_id); 328 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 329 u16 *vddc, u16 *vddci, 330 u16 virtual_voltage_id, 331 u16 vbios_voltage_id); 332 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 333 u16 virtual_voltage_id, 334 u16 *voltage); 335 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 336 u8 voltage_type, 337 u16 nominal_voltage, 338 u16 *true_voltage); 339 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 340 u8 voltage_type, u16 *min_voltage); 341 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 342 u8 voltage_type, u16 *max_voltage); 343 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 344 u8 voltage_type, u8 voltage_mode, 345 struct atom_voltage_table *voltage_table); 346 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 347 u8 voltage_type, u8 voltage_mode); 348 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 349 u8 voltage_type, 350 u8 *svd_gpio_id, u8 *svc_gpio_id); 351 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 352 u32 mem_clock); 353 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 354 u32 mem_clock); 355 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 356 u8 module_index, 357 struct atom_mc_reg_table *reg_table); 358 int radeon_atom_get_memory_info(struct radeon_device *rdev, 359 u8 module_index, struct atom_memory_info *mem_info); 360 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 361 bool gddr5, u8 module_index, 362 struct atom_memory_clock_range_table *mclk_range_table); 363 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 364 u16 voltage_id, u16 *voltage); 365 void rs690_pm_info(struct radeon_device *rdev); 366 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 367 unsigned *bankh, unsigned *mtaspect, 368 unsigned *tile_split); 369 370 /* 371 * Fences. 372 */ 373 struct radeon_fence_driver { 374 struct radeon_device *rdev; 375 uint32_t scratch_reg; 376 uint64_t gpu_addr; 377 volatile uint32_t *cpu_addr; 378 /* sync_seq is protected by ring emission lock */ 379 uint64_t sync_seq[RADEON_NUM_RINGS]; 380 atomic64_t last_seq; 381 bool initialized, delayed_irq; 382 struct delayed_work lockup_work; 383 }; 384 385 struct radeon_fence { 386 struct dma_fence base; 387 388 struct radeon_device *rdev; 389 uint64_t seq; 390 /* RB, DMA, etc. */ 391 unsigned ring; 392 bool is_vm_update; 393 394 wait_queue_entry_t fence_wake; 395 }; 396 397 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 398 void radeon_fence_driver_init(struct radeon_device *rdev); 399 void radeon_fence_driver_fini(struct radeon_device *rdev); 400 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 401 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 402 void radeon_fence_process(struct radeon_device *rdev, int ring); 403 bool radeon_fence_signaled(struct radeon_fence *fence); 404 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 405 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 406 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 407 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 408 int radeon_fence_wait_any(struct radeon_device *rdev, 409 struct radeon_fence **fences, 410 bool intr); 411 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 412 void radeon_fence_unref(struct radeon_fence **fence); 413 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 414 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 415 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 416 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 417 struct radeon_fence *b) 418 { 419 if (!a) { 420 return b; 421 } 422 423 if (!b) { 424 return a; 425 } 426 427 BUG_ON(a->ring != b->ring); 428 429 if (a->seq > b->seq) { 430 return a; 431 } else { 432 return b; 433 } 434 } 435 436 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 437 struct radeon_fence *b) 438 { 439 if (!a) { 440 return false; 441 } 442 443 if (!b) { 444 return true; 445 } 446 447 BUG_ON(a->ring != b->ring); 448 449 return a->seq < b->seq; 450 } 451 452 /* 453 * Tiling registers 454 */ 455 struct radeon_surface_reg { 456 struct radeon_bo *bo; 457 }; 458 459 #define RADEON_GEM_MAX_SURFACES 8 460 461 /* 462 * TTM. 463 */ 464 struct radeon_mman { 465 struct ttm_device bdev; 466 bool initialized; 467 }; 468 469 struct radeon_bo_list { 470 struct radeon_bo *robj; 471 struct ttm_validate_buffer tv; 472 uint64_t gpu_offset; 473 unsigned preferred_domains; 474 unsigned allowed_domains; 475 uint32_t tiling_flags; 476 }; 477 478 /* bo virtual address in a specific vm */ 479 struct radeon_bo_va { 480 /* protected by bo being reserved */ 481 struct list_head bo_list; 482 uint32_t flags; 483 struct radeon_fence *last_pt_update; 484 unsigned ref_count; 485 486 /* protected by vm mutex */ 487 struct interval_tree_node it; 488 struct list_head vm_status; 489 490 /* constant after initialization */ 491 struct radeon_vm *vm; 492 struct radeon_bo *bo; 493 }; 494 495 struct radeon_bo { 496 /* Protected by gem.mutex */ 497 struct list_head list; 498 /* Protected by tbo.reserved */ 499 u32 initial_domain; 500 struct ttm_place placements[4]; 501 struct ttm_placement placement; 502 struct ttm_buffer_object tbo; 503 struct ttm_bo_kmap_obj kmap; 504 u32 flags; 505 void *kptr; 506 u32 tiling_flags; 507 u32 pitch; 508 int surface_reg; 509 unsigned prime_shared_count; 510 /* list of all virtual address to which this bo 511 * is associated to 512 */ 513 struct list_head va; 514 /* Constant after initialization */ 515 struct radeon_device *rdev; 516 517 pid_t pid; 518 519 #ifdef CONFIG_MMU_NOTIFIER 520 struct mmu_interval_notifier notifier; 521 #endif 522 }; 523 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base) 524 525 struct radeon_sa_manager { 526 struct drm_suballoc_manager base; 527 struct radeon_bo *bo; 528 uint64_t gpu_addr; 529 void *cpu_ptr; 530 u32 domain; 531 }; 532 533 /* 534 * GEM objects. 535 */ 536 struct radeon_gem { 537 struct rwlock mutex; 538 struct list_head objects; 539 }; 540 541 extern const struct drm_gem_object_funcs radeon_gem_object_funcs; 542 543 int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled); 544 545 int radeon_gem_init(struct radeon_device *rdev); 546 void radeon_gem_fini(struct radeon_device *rdev); 547 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 548 int alignment, int initial_domain, 549 u32 flags, bool kernel, 550 struct drm_gem_object **obj); 551 552 int radeon_mode_dumb_create(struct drm_file *file_priv, 553 struct drm_device *dev, 554 struct drm_mode_create_dumb *args); 555 int radeon_mode_dumb_mmap(struct drm_file *filp, 556 struct drm_device *dev, 557 uint32_t handle, uint64_t *offset_p); 558 559 /* 560 * Semaphores. 561 */ 562 struct radeon_semaphore { 563 struct drm_suballoc *sa_bo; 564 signed waiters; 565 uint64_t gpu_addr; 566 }; 567 568 int radeon_semaphore_create(struct radeon_device *rdev, 569 struct radeon_semaphore **semaphore); 570 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 571 struct radeon_semaphore *semaphore); 572 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 573 struct radeon_semaphore *semaphore); 574 void radeon_semaphore_free(struct radeon_device *rdev, 575 struct radeon_semaphore **semaphore, 576 struct radeon_fence *fence); 577 578 /* 579 * Synchronization 580 */ 581 struct radeon_sync { 582 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 583 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 584 struct radeon_fence *last_vm_update; 585 }; 586 587 void radeon_sync_create(struct radeon_sync *sync); 588 void radeon_sync_fence(struct radeon_sync *sync, 589 struct radeon_fence *fence); 590 int radeon_sync_resv(struct radeon_device *rdev, 591 struct radeon_sync *sync, 592 struct dma_resv *resv, 593 bool shared); 594 int radeon_sync_rings(struct radeon_device *rdev, 595 struct radeon_sync *sync, 596 int waiting_ring); 597 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 598 struct radeon_fence *fence); 599 600 /* 601 * GART structures, functions & helpers 602 */ 603 struct radeon_mc; 604 605 #define RADEON_GPU_PAGE_SIZE 4096 606 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 607 #define RADEON_GPU_PAGE_SHIFT 12 608 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 609 610 #define RADEON_GART_PAGE_DUMMY 0 611 #define RADEON_GART_PAGE_VALID (1 << 0) 612 #define RADEON_GART_PAGE_READ (1 << 1) 613 #define RADEON_GART_PAGE_WRITE (1 << 2) 614 #define RADEON_GART_PAGE_SNOOP (1 << 3) 615 616 struct radeon_gart { 617 dma_addr_t table_addr; 618 struct drm_dmamem *dmah; 619 struct radeon_bo *robj; 620 void *ptr; 621 unsigned num_gpu_pages; 622 unsigned num_cpu_pages; 623 unsigned table_size; 624 struct vm_page **pages; 625 uint64_t *pages_entry; 626 bool ready; 627 }; 628 629 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 630 void radeon_gart_table_ram_free(struct radeon_device *rdev); 631 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 632 void radeon_gart_table_vram_free(struct radeon_device *rdev); 633 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 634 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 635 int radeon_gart_init(struct radeon_device *rdev); 636 void radeon_gart_fini(struct radeon_device *rdev); 637 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 638 int pages); 639 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 640 int pages, struct vm_page **pagelist, 641 dma_addr_t *dma_addr, uint32_t flags); 642 643 644 /* 645 * GPU MC structures, functions & helpers 646 */ 647 struct radeon_mc { 648 resource_size_t aper_size; 649 resource_size_t aper_base; 650 resource_size_t agp_base; 651 /* for some chips with <= 32MB we need to lie 652 * about vram size near mc fb location */ 653 u64 mc_vram_size; 654 u64 visible_vram_size; 655 u64 gtt_size; 656 u64 gtt_start; 657 u64 gtt_end; 658 u64 vram_start; 659 u64 vram_end; 660 unsigned vram_width; 661 u64 real_vram_size; 662 int vram_mtrr; 663 bool vram_is_ddr; 664 bool igp_sideport_enabled; 665 u64 gtt_base_align; 666 u64 mc_mask; 667 }; 668 669 bool radeon_combios_sideport_present(struct radeon_device *rdev); 670 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 671 672 /* 673 * GPU scratch registers structures, functions & helpers 674 */ 675 struct radeon_scratch { 676 unsigned num_reg; 677 uint32_t reg_base; 678 bool free[32]; 679 uint32_t reg[32]; 680 }; 681 682 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 683 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 684 685 /* 686 * GPU doorbell structures, functions & helpers 687 */ 688 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 689 690 struct radeon_doorbell { 691 /* doorbell mmio */ 692 resource_size_t base; 693 resource_size_t size; 694 u32 __iomem *ptr; 695 bus_space_handle_t bsh; 696 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 697 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 698 }; 699 700 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 701 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 702 703 /* 704 * IRQS. 705 */ 706 707 struct radeon_flip_work { 708 struct work_struct flip_work; 709 struct work_struct unpin_work; 710 struct radeon_device *rdev; 711 int crtc_id; 712 u32 target_vblank; 713 uint64_t base; 714 struct drm_pending_vblank_event *event; 715 struct radeon_bo *old_rbo; 716 struct dma_fence *fence; 717 bool async; 718 }; 719 720 struct r500_irq_stat_regs { 721 u32 disp_int; 722 u32 hdmi0_status; 723 }; 724 725 struct r600_irq_stat_regs { 726 u32 disp_int; 727 u32 disp_int_cont; 728 u32 disp_int_cont2; 729 u32 d1grph_int; 730 u32 d2grph_int; 731 u32 hdmi0_status; 732 u32 hdmi1_status; 733 }; 734 735 struct evergreen_irq_stat_regs { 736 u32 disp_int[6]; 737 u32 grph_int[6]; 738 u32 afmt_status[6]; 739 }; 740 741 struct cik_irq_stat_regs { 742 u32 disp_int; 743 u32 disp_int_cont; 744 u32 disp_int_cont2; 745 u32 disp_int_cont3; 746 u32 disp_int_cont4; 747 u32 disp_int_cont5; 748 u32 disp_int_cont6; 749 u32 d1grph_int; 750 u32 d2grph_int; 751 u32 d3grph_int; 752 u32 d4grph_int; 753 u32 d5grph_int; 754 u32 d6grph_int; 755 }; 756 757 union radeon_irq_stat_regs { 758 struct r500_irq_stat_regs r500; 759 struct r600_irq_stat_regs r600; 760 struct evergreen_irq_stat_regs evergreen; 761 struct cik_irq_stat_regs cik; 762 }; 763 764 struct radeon_irq { 765 bool installed; 766 spinlock_t lock; 767 atomic_t ring_int[RADEON_NUM_RINGS]; 768 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 769 atomic_t pflip[RADEON_MAX_CRTCS]; 770 wait_queue_head_t vblank_queue; 771 bool hpd[RADEON_MAX_HPD_PINS]; 772 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 773 union radeon_irq_stat_regs stat_regs; 774 bool dpm_thermal; 775 }; 776 777 int radeon_irq_kms_init(struct radeon_device *rdev); 778 void radeon_irq_kms_fini(struct radeon_device *rdev); 779 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 780 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 781 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 782 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 783 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 784 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 785 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 786 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 787 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 788 789 /* 790 * CP & rings. 791 */ 792 793 struct radeon_ib { 794 struct drm_suballoc *sa_bo; 795 uint32_t length_dw; 796 uint64_t gpu_addr; 797 uint32_t *ptr; 798 int ring; 799 struct radeon_fence *fence; 800 struct radeon_vm *vm; 801 bool is_const_ib; 802 struct radeon_sync sync; 803 }; 804 805 struct radeon_ring { 806 struct radeon_device *rdev; 807 struct radeon_bo *ring_obj; 808 volatile uint32_t *ring; 809 unsigned rptr_offs; 810 unsigned rptr_save_reg; 811 u64 next_rptr_gpu_addr; 812 volatile u32 *next_rptr_cpu_addr; 813 unsigned wptr; 814 unsigned wptr_old; 815 unsigned ring_size; 816 unsigned ring_free_dw; 817 int count_dw; 818 atomic_t last_rptr; 819 atomic64_t last_activity; 820 uint64_t gpu_addr; 821 uint32_t align_mask; 822 uint32_t ptr_mask; 823 bool ready; 824 u32 nop; 825 u32 idx; 826 u64 last_semaphore_signal_addr; 827 u64 last_semaphore_wait_addr; 828 /* for CIK queues */ 829 u32 me; 830 u32 pipe; 831 u32 queue; 832 struct radeon_bo *mqd_obj; 833 u32 doorbell_index; 834 unsigned wptr_offs; 835 }; 836 837 struct radeon_mec { 838 struct radeon_bo *hpd_eop_obj; 839 u64 hpd_eop_gpu_addr; 840 u32 num_pipe; 841 u32 num_mec; 842 u32 num_queue; 843 }; 844 845 /* 846 * VM 847 */ 848 849 /* maximum number of VMIDs */ 850 #define RADEON_NUM_VM 16 851 852 /* number of entries in page table */ 853 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 854 855 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 856 #define RADEON_VM_PTB_ALIGN_SIZE 32768 857 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 858 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 859 860 #define R600_PTE_VALID (1 << 0) 861 #define R600_PTE_SYSTEM (1 << 1) 862 #define R600_PTE_SNOOPED (1 << 2) 863 #define R600_PTE_READABLE (1 << 5) 864 #define R600_PTE_WRITEABLE (1 << 6) 865 866 /* PTE (Page Table Entry) fragment field for different page sizes */ 867 #define R600_PTE_FRAG_4KB (0 << 7) 868 #define R600_PTE_FRAG_64KB (4 << 7) 869 #define R600_PTE_FRAG_256KB (6 << 7) 870 871 /* flags needed to be set so we can copy directly from the GART table */ 872 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 873 R600_PTE_SYSTEM | R600_PTE_VALID ) 874 875 struct radeon_vm_pt { 876 struct radeon_bo *bo; 877 uint64_t addr; 878 }; 879 880 struct radeon_vm_id { 881 unsigned id; 882 uint64_t pd_gpu_addr; 883 /* last flushed PD/PT update */ 884 struct radeon_fence *flushed_updates; 885 /* last use of vmid */ 886 struct radeon_fence *last_id_use; 887 }; 888 889 struct radeon_vm { 890 struct rwlock mutex; 891 892 struct rb_root_cached va; 893 894 /* protecting invalidated and freed */ 895 spinlock_t status_lock; 896 897 /* BOs moved, but not yet updated in the PT */ 898 struct list_head invalidated; 899 900 /* BOs freed, but not yet updated in the PT */ 901 struct list_head freed; 902 903 /* BOs cleared in the PT */ 904 struct list_head cleared; 905 906 /* contains the page directory */ 907 struct radeon_bo *page_directory; 908 unsigned max_pde_used; 909 910 /* array of page tables, one for each page directory entry */ 911 struct radeon_vm_pt *page_tables; 912 913 struct radeon_bo_va *ib_bo_va; 914 915 /* for id and flush management per ring */ 916 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 917 }; 918 919 struct radeon_vm_manager { 920 struct radeon_fence *active[RADEON_NUM_VM]; 921 uint32_t max_pfn; 922 /* number of VMIDs */ 923 unsigned nvm; 924 /* vram base address for page table entry */ 925 u64 vram_base_offset; 926 /* is vm enabled? */ 927 bool enabled; 928 /* for hw to save the PD addr on suspend/resume */ 929 uint32_t saved_table_addr[RADEON_NUM_VM]; 930 }; 931 932 /* 933 * file private structure 934 */ 935 struct radeon_fpriv { 936 struct radeon_vm vm; 937 }; 938 939 /* 940 * R6xx+ IH ring 941 */ 942 struct r600_ih { 943 struct radeon_bo *ring_obj; 944 volatile uint32_t *ring; 945 unsigned rptr; 946 unsigned ring_size; 947 uint64_t gpu_addr; 948 uint32_t ptr_mask; 949 atomic_t lock; 950 bool enabled; 951 }; 952 953 /* 954 * RLC stuff 955 */ 956 #include "clearstate_defs.h" 957 958 struct radeon_rlc { 959 /* for power gating */ 960 struct radeon_bo *save_restore_obj; 961 uint64_t save_restore_gpu_addr; 962 volatile uint32_t *sr_ptr; 963 const u32 *reg_list; 964 u32 reg_list_size; 965 /* for clear state */ 966 struct radeon_bo *clear_state_obj; 967 uint64_t clear_state_gpu_addr; 968 volatile uint32_t *cs_ptr; 969 const struct cs_section_def *cs_data; 970 u32 clear_state_size; 971 /* for cp tables */ 972 struct radeon_bo *cp_table_obj; 973 uint64_t cp_table_gpu_addr; 974 volatile uint32_t *cp_table_ptr; 975 u32 cp_table_size; 976 }; 977 978 int radeon_ib_get(struct radeon_device *rdev, int ring, 979 struct radeon_ib *ib, struct radeon_vm *vm, 980 unsigned size); 981 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 982 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 983 struct radeon_ib *const_ib, bool hdp_flush); 984 int radeon_ib_pool_init(struct radeon_device *rdev); 985 void radeon_ib_pool_fini(struct radeon_device *rdev); 986 int radeon_ib_ring_tests(struct radeon_device *rdev); 987 /* Ring access between begin & end cannot sleep */ 988 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 989 struct radeon_ring *ring); 990 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 991 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 992 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 993 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 994 bool hdp_flush); 995 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 996 bool hdp_flush); 997 void radeon_ring_undo(struct radeon_ring *ring); 998 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 999 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1000 void radeon_ring_lockup_update(struct radeon_device *rdev, 1001 struct radeon_ring *ring); 1002 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1003 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1004 uint32_t **data); 1005 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1006 unsigned size, uint32_t *data); 1007 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1008 unsigned rptr_offs, u32 nop); 1009 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1010 1011 1012 /* r600 async dma */ 1013 void r600_dma_stop(struct radeon_device *rdev); 1014 int r600_dma_resume(struct radeon_device *rdev); 1015 void r600_dma_fini(struct radeon_device *rdev); 1016 1017 void cayman_dma_stop(struct radeon_device *rdev); 1018 int cayman_dma_resume(struct radeon_device *rdev); 1019 void cayman_dma_fini(struct radeon_device *rdev); 1020 1021 /* 1022 * CS. 1023 */ 1024 struct radeon_cs_chunk { 1025 uint32_t length_dw; 1026 uint32_t *kdata; 1027 void __user *user_ptr; 1028 }; 1029 1030 struct radeon_cs_parser { 1031 struct device *dev; 1032 struct radeon_device *rdev; 1033 struct drm_file *filp; 1034 /* chunks */ 1035 unsigned nchunks; 1036 struct radeon_cs_chunk *chunks; 1037 uint64_t *chunks_array; 1038 /* IB */ 1039 unsigned idx; 1040 /* relocations */ 1041 unsigned nrelocs; 1042 struct radeon_bo_list *relocs; 1043 struct radeon_bo_list *vm_bos; 1044 struct list_head validated; 1045 unsigned dma_reloc_idx; 1046 /* indices of various chunks */ 1047 struct radeon_cs_chunk *chunk_ib; 1048 struct radeon_cs_chunk *chunk_relocs; 1049 struct radeon_cs_chunk *chunk_flags; 1050 struct radeon_cs_chunk *chunk_const_ib; 1051 struct radeon_ib ib; 1052 struct radeon_ib const_ib; 1053 void *track; 1054 unsigned family; 1055 int parser_error; 1056 u32 cs_flags; 1057 u32 ring; 1058 s32 priority; 1059 struct ww_acquire_ctx ticket; 1060 }; 1061 1062 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1063 { 1064 struct radeon_cs_chunk *ibc = p->chunk_ib; 1065 1066 if (ibc->kdata) 1067 return ibc->kdata[idx]; 1068 return p->ib.ptr[idx]; 1069 } 1070 1071 1072 struct radeon_cs_packet { 1073 unsigned idx; 1074 unsigned type; 1075 unsigned reg; 1076 unsigned opcode; 1077 int count; 1078 unsigned one_reg_wr; 1079 }; 1080 1081 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1082 struct radeon_cs_packet *pkt, 1083 unsigned idx, unsigned reg); 1084 1085 /* 1086 * AGP 1087 */ 1088 1089 struct radeon_agp_mode { 1090 unsigned long mode; /**< AGP mode */ 1091 }; 1092 1093 struct radeon_agp_info { 1094 int agp_version_major; 1095 int agp_version_minor; 1096 unsigned long mode; 1097 unsigned long aperture_base; /* physical address */ 1098 unsigned long aperture_size; /* bytes */ 1099 unsigned long memory_allowed; /* bytes */ 1100 unsigned long memory_used; 1101 1102 /* PCI information */ 1103 unsigned short id_vendor; 1104 unsigned short id_device; 1105 }; 1106 1107 struct radeon_agp_head { 1108 #ifdef notyet 1109 struct agp_kern_info agp_info; 1110 #endif 1111 struct list_head memory; 1112 unsigned long mode; 1113 struct agp_bridge_data *bridge; 1114 int enabled; 1115 int acquired; 1116 unsigned long base; 1117 int agp_mtrr; 1118 int cant_use_aperture; 1119 unsigned long page_mask; 1120 }; 1121 1122 #if IS_ENABLED(CONFIG_AGP) 1123 struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev); 1124 #else 1125 static inline struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev) 1126 { 1127 return NULL; 1128 } 1129 #endif 1130 int radeon_agp_init(struct radeon_device *rdev); 1131 void radeon_agp_resume(struct radeon_device *rdev); 1132 void radeon_agp_suspend(struct radeon_device *rdev); 1133 void radeon_agp_fini(struct radeon_device *rdev); 1134 1135 1136 /* 1137 * Writeback 1138 */ 1139 struct radeon_wb { 1140 struct radeon_bo *wb_obj; 1141 volatile uint32_t *wb; 1142 uint64_t gpu_addr; 1143 bool enabled; 1144 bool use_event; 1145 }; 1146 1147 #define RADEON_WB_SCRATCH_OFFSET 0 1148 #define RADEON_WB_RING0_NEXT_RPTR 256 1149 #define RADEON_WB_CP_RPTR_OFFSET 1024 1150 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1151 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1152 #define R600_WB_DMA_RPTR_OFFSET 1792 1153 #define R600_WB_IH_WPTR_OFFSET 2048 1154 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1155 #define R600_WB_EVENT_OFFSET 3072 1156 #define CIK_WB_CP1_WPTR_OFFSET 3328 1157 #define CIK_WB_CP2_WPTR_OFFSET 3584 1158 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1159 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1160 1161 /** 1162 * struct radeon_pm - power management datas 1163 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1164 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1165 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1166 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1167 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1168 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1169 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1170 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1171 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1172 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1173 * @needed_bandwidth: current bandwidth needs 1174 * 1175 * It keeps track of various data needed to take powermanagement decision. 1176 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1177 * Equation between gpu/memory clock and available bandwidth is hw dependent 1178 * (type of memory, bus size, efficiency, ...) 1179 */ 1180 1181 enum radeon_pm_method { 1182 PM_METHOD_PROFILE, 1183 PM_METHOD_DYNPM, 1184 PM_METHOD_DPM, 1185 }; 1186 1187 enum radeon_dynpm_state { 1188 DYNPM_STATE_DISABLED, 1189 DYNPM_STATE_MINIMUM, 1190 DYNPM_STATE_PAUSED, 1191 DYNPM_STATE_ACTIVE, 1192 DYNPM_STATE_SUSPENDED, 1193 }; 1194 enum radeon_dynpm_action { 1195 DYNPM_ACTION_NONE, 1196 DYNPM_ACTION_MINIMUM, 1197 DYNPM_ACTION_DOWNCLOCK, 1198 DYNPM_ACTION_UPCLOCK, 1199 DYNPM_ACTION_DEFAULT 1200 }; 1201 1202 enum radeon_voltage_type { 1203 VOLTAGE_NONE = 0, 1204 VOLTAGE_GPIO, 1205 VOLTAGE_VDDC, 1206 VOLTAGE_SW 1207 }; 1208 1209 enum radeon_pm_state_type { 1210 /* not used for dpm */ 1211 POWER_STATE_TYPE_DEFAULT, 1212 POWER_STATE_TYPE_POWERSAVE, 1213 /* user selectable states */ 1214 POWER_STATE_TYPE_BATTERY, 1215 POWER_STATE_TYPE_BALANCED, 1216 POWER_STATE_TYPE_PERFORMANCE, 1217 /* internal states */ 1218 POWER_STATE_TYPE_INTERNAL_UVD, 1219 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1220 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1221 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1222 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1223 POWER_STATE_TYPE_INTERNAL_BOOT, 1224 POWER_STATE_TYPE_INTERNAL_THERMAL, 1225 POWER_STATE_TYPE_INTERNAL_ACPI, 1226 POWER_STATE_TYPE_INTERNAL_ULV, 1227 POWER_STATE_TYPE_INTERNAL_3DPERF, 1228 }; 1229 1230 enum radeon_pm_profile_type { 1231 PM_PROFILE_DEFAULT, 1232 PM_PROFILE_AUTO, 1233 PM_PROFILE_LOW, 1234 PM_PROFILE_MID, 1235 PM_PROFILE_HIGH, 1236 }; 1237 1238 #define PM_PROFILE_DEFAULT_IDX 0 1239 #define PM_PROFILE_LOW_SH_IDX 1 1240 #define PM_PROFILE_MID_SH_IDX 2 1241 #define PM_PROFILE_HIGH_SH_IDX 3 1242 #define PM_PROFILE_LOW_MH_IDX 4 1243 #define PM_PROFILE_MID_MH_IDX 5 1244 #define PM_PROFILE_HIGH_MH_IDX 6 1245 #define PM_PROFILE_MAX 7 1246 1247 struct radeon_pm_profile { 1248 int dpms_off_ps_idx; 1249 int dpms_on_ps_idx; 1250 int dpms_off_cm_idx; 1251 int dpms_on_cm_idx; 1252 }; 1253 1254 enum radeon_int_thermal_type { 1255 THERMAL_TYPE_NONE, 1256 THERMAL_TYPE_EXTERNAL, 1257 THERMAL_TYPE_EXTERNAL_GPIO, 1258 THERMAL_TYPE_RV6XX, 1259 THERMAL_TYPE_RV770, 1260 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1261 THERMAL_TYPE_EVERGREEN, 1262 THERMAL_TYPE_SUMO, 1263 THERMAL_TYPE_NI, 1264 THERMAL_TYPE_SI, 1265 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1266 THERMAL_TYPE_CI, 1267 THERMAL_TYPE_KV, 1268 }; 1269 1270 struct radeon_voltage { 1271 enum radeon_voltage_type type; 1272 /* gpio voltage */ 1273 struct radeon_gpio_rec gpio; 1274 u32 delay; /* delay in usec from voltage drop to sclk change */ 1275 bool active_high; /* voltage drop is active when bit is high */ 1276 /* VDDC voltage */ 1277 u8 vddc_id; /* index into vddc voltage table */ 1278 u8 vddci_id; /* index into vddci voltage table */ 1279 bool vddci_enabled; 1280 /* r6xx+ sw */ 1281 u16 voltage; 1282 /* evergreen+ vddci */ 1283 u16 vddci; 1284 }; 1285 1286 /* clock mode flags */ 1287 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1288 1289 struct radeon_pm_clock_info { 1290 /* memory clock */ 1291 u32 mclk; 1292 /* engine clock */ 1293 u32 sclk; 1294 /* voltage info */ 1295 struct radeon_voltage voltage; 1296 /* standardized clock flags */ 1297 u32 flags; 1298 }; 1299 1300 /* state flags */ 1301 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1302 1303 struct radeon_power_state { 1304 enum radeon_pm_state_type type; 1305 struct radeon_pm_clock_info *clock_info; 1306 /* number of valid clock modes in this power state */ 1307 int num_clock_modes; 1308 struct radeon_pm_clock_info *default_clock_mode; 1309 /* standardized state flags */ 1310 u32 flags; 1311 u32 misc; /* vbios specific flags */ 1312 u32 misc2; /* vbios specific flags */ 1313 int pcie_lanes; /* pcie lanes */ 1314 }; 1315 1316 /* 1317 * Some modes are overclocked by very low value, accept them 1318 */ 1319 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1320 1321 enum radeon_dpm_auto_throttle_src { 1322 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1323 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1324 }; 1325 1326 enum radeon_dpm_event_src { 1327 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1328 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1329 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1330 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1331 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1332 }; 1333 1334 #define RADEON_MAX_VCE_LEVELS 6 1335 1336 enum radeon_vce_level { 1337 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1338 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1339 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1340 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1341 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1342 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1343 }; 1344 1345 struct radeon_ps { 1346 u32 caps; /* vbios flags */ 1347 u32 class; /* vbios flags */ 1348 u32 class2; /* vbios flags */ 1349 /* UVD clocks */ 1350 u32 vclk; 1351 u32 dclk; 1352 /* VCE clocks */ 1353 u32 evclk; 1354 u32 ecclk; 1355 bool vce_active; 1356 enum radeon_vce_level vce_level; 1357 /* asic priv */ 1358 void *ps_priv; 1359 }; 1360 1361 struct radeon_dpm_thermal { 1362 /* thermal interrupt work */ 1363 struct work_struct work; 1364 /* low temperature threshold */ 1365 int min_temp; 1366 /* high temperature threshold */ 1367 int max_temp; 1368 /* was interrupt low to high or high to low */ 1369 bool high_to_low; 1370 }; 1371 1372 enum radeon_clk_action 1373 { 1374 RADEON_SCLK_UP = 1, 1375 RADEON_SCLK_DOWN 1376 }; 1377 1378 struct radeon_blacklist_clocks 1379 { 1380 u32 sclk; 1381 u32 mclk; 1382 enum radeon_clk_action action; 1383 }; 1384 1385 struct radeon_clock_and_voltage_limits { 1386 u32 sclk; 1387 u32 mclk; 1388 u16 vddc; 1389 u16 vddci; 1390 }; 1391 1392 struct radeon_clock_array { 1393 u32 count; 1394 u32 *values; 1395 }; 1396 1397 struct radeon_clock_voltage_dependency_entry { 1398 u32 clk; 1399 u16 v; 1400 }; 1401 1402 struct radeon_clock_voltage_dependency_table { 1403 u32 count; 1404 struct radeon_clock_voltage_dependency_entry *entries; 1405 }; 1406 1407 union radeon_cac_leakage_entry { 1408 struct { 1409 u16 vddc; 1410 u32 leakage; 1411 }; 1412 struct { 1413 u16 vddc1; 1414 u16 vddc2; 1415 u16 vddc3; 1416 }; 1417 }; 1418 1419 struct radeon_cac_leakage_table { 1420 u32 count; 1421 union radeon_cac_leakage_entry *entries; 1422 }; 1423 1424 struct radeon_phase_shedding_limits_entry { 1425 u16 voltage; 1426 u32 sclk; 1427 u32 mclk; 1428 }; 1429 1430 struct radeon_phase_shedding_limits_table { 1431 u32 count; 1432 struct radeon_phase_shedding_limits_entry *entries; 1433 }; 1434 1435 struct radeon_uvd_clock_voltage_dependency_entry { 1436 u32 vclk; 1437 u32 dclk; 1438 u16 v; 1439 }; 1440 1441 struct radeon_uvd_clock_voltage_dependency_table { 1442 u8 count; 1443 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1444 }; 1445 1446 struct radeon_vce_clock_voltage_dependency_entry { 1447 u32 ecclk; 1448 u32 evclk; 1449 u16 v; 1450 }; 1451 1452 struct radeon_vce_clock_voltage_dependency_table { 1453 u8 count; 1454 struct radeon_vce_clock_voltage_dependency_entry *entries; 1455 }; 1456 1457 struct radeon_ppm_table { 1458 u8 ppm_design; 1459 u16 cpu_core_number; 1460 u32 platform_tdp; 1461 u32 small_ac_platform_tdp; 1462 u32 platform_tdc; 1463 u32 small_ac_platform_tdc; 1464 u32 apu_tdp; 1465 u32 dgpu_tdp; 1466 u32 dgpu_ulv_power; 1467 u32 tj_max; 1468 }; 1469 1470 struct radeon_cac_tdp_table { 1471 u16 tdp; 1472 u16 configurable_tdp; 1473 u16 tdc; 1474 u16 battery_power_limit; 1475 u16 small_power_limit; 1476 u16 low_cac_leakage; 1477 u16 high_cac_leakage; 1478 u16 maximum_power_delivery_limit; 1479 }; 1480 1481 struct radeon_dpm_dynamic_state { 1482 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1483 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1484 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1485 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1486 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1487 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1488 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1489 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1490 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1491 struct radeon_clock_array valid_sclk_values; 1492 struct radeon_clock_array valid_mclk_values; 1493 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1494 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1495 u32 mclk_sclk_ratio; 1496 u32 sclk_mclk_delta; 1497 u16 vddc_vddci_delta; 1498 u16 min_vddc_for_pcie_gen2; 1499 struct radeon_cac_leakage_table cac_leakage_table; 1500 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1501 struct radeon_ppm_table *ppm_table; 1502 struct radeon_cac_tdp_table *cac_tdp_table; 1503 }; 1504 1505 struct radeon_dpm_fan { 1506 u16 t_min; 1507 u16 t_med; 1508 u16 t_high; 1509 u16 pwm_min; 1510 u16 pwm_med; 1511 u16 pwm_high; 1512 u8 t_hyst; 1513 u32 cycle_delay; 1514 u16 t_max; 1515 u8 control_mode; 1516 u16 default_max_fan_pwm; 1517 u16 default_fan_output_sensitivity; 1518 u16 fan_output_sensitivity; 1519 bool ucode_fan_control; 1520 }; 1521 1522 enum radeon_pcie_gen { 1523 RADEON_PCIE_GEN1 = 0, 1524 RADEON_PCIE_GEN2 = 1, 1525 RADEON_PCIE_GEN3 = 2, 1526 RADEON_PCIE_GEN_INVALID = 0xffff 1527 }; 1528 1529 enum radeon_dpm_forced_level { 1530 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1531 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1532 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1533 }; 1534 1535 struct radeon_vce_state { 1536 /* vce clocks */ 1537 u32 evclk; 1538 u32 ecclk; 1539 /* gpu clocks */ 1540 u32 sclk; 1541 u32 mclk; 1542 u8 clk_idx; 1543 u8 pstate; 1544 }; 1545 1546 struct radeon_dpm { 1547 struct radeon_ps *ps; 1548 /* number of valid power states */ 1549 int num_ps; 1550 /* current power state that is active */ 1551 struct radeon_ps *current_ps; 1552 /* requested power state */ 1553 struct radeon_ps *requested_ps; 1554 /* boot up power state */ 1555 struct radeon_ps *boot_ps; 1556 /* default uvd power state */ 1557 struct radeon_ps *uvd_ps; 1558 /* vce requirements */ 1559 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1560 enum radeon_vce_level vce_level; 1561 enum radeon_pm_state_type state; 1562 enum radeon_pm_state_type user_state; 1563 u32 platform_caps; 1564 u32 voltage_response_time; 1565 u32 backbias_response_time; 1566 void *priv; 1567 u32 new_active_crtcs; 1568 int new_active_crtc_count; 1569 int high_pixelclock_count; 1570 u32 current_active_crtcs; 1571 int current_active_crtc_count; 1572 bool single_display; 1573 struct radeon_dpm_dynamic_state dyn_state; 1574 struct radeon_dpm_fan fan; 1575 u32 tdp_limit; 1576 u32 near_tdp_limit; 1577 u32 near_tdp_limit_adjusted; 1578 u32 sq_ramping_threshold; 1579 u32 cac_leakage; 1580 u16 tdp_od_limit; 1581 u32 tdp_adjustment; 1582 u16 load_line_slope; 1583 bool power_control; 1584 bool ac_power; 1585 /* special states active */ 1586 bool thermal_active; 1587 bool uvd_active; 1588 bool vce_active; 1589 /* thermal handling */ 1590 struct radeon_dpm_thermal thermal; 1591 /* forced levels */ 1592 enum radeon_dpm_forced_level forced_level; 1593 /* track UVD streams */ 1594 unsigned sd; 1595 unsigned hd; 1596 }; 1597 1598 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1599 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1600 1601 struct radeon_pm { 1602 struct rwlock mutex; 1603 /* write locked while reprogramming mclk */ 1604 struct rwlock mclk_lock; 1605 u32 active_crtcs; 1606 int active_crtc_count; 1607 int req_vblank; 1608 bool vblank_sync; 1609 fixed20_12 max_bandwidth; 1610 fixed20_12 igp_sideport_mclk; 1611 fixed20_12 igp_system_mclk; 1612 fixed20_12 igp_ht_link_clk; 1613 fixed20_12 igp_ht_link_width; 1614 fixed20_12 k8_bandwidth; 1615 fixed20_12 sideport_bandwidth; 1616 fixed20_12 ht_bandwidth; 1617 fixed20_12 core_bandwidth; 1618 fixed20_12 sclk; 1619 fixed20_12 mclk; 1620 fixed20_12 needed_bandwidth; 1621 struct radeon_power_state *power_state; 1622 /* number of valid power states */ 1623 int num_power_states; 1624 int current_power_state_index; 1625 int current_clock_mode_index; 1626 int requested_power_state_index; 1627 int requested_clock_mode_index; 1628 int default_power_state_index; 1629 u32 current_sclk; 1630 u32 current_mclk; 1631 u16 current_vddc; 1632 u16 current_vddci; 1633 u32 default_sclk; 1634 u32 default_mclk; 1635 u16 default_vddc; 1636 u16 default_vddci; 1637 struct radeon_i2c_chan *i2c_bus; 1638 /* selected pm method */ 1639 enum radeon_pm_method pm_method; 1640 /* dynpm power management */ 1641 struct delayed_work dynpm_idle_work; 1642 enum radeon_dynpm_state dynpm_state; 1643 enum radeon_dynpm_action dynpm_planned_action; 1644 unsigned long dynpm_action_timeout; 1645 bool dynpm_can_upclock; 1646 bool dynpm_can_downclock; 1647 /* profile-based power management */ 1648 enum radeon_pm_profile_type profile; 1649 int profile_index; 1650 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1651 /* internal thermal controller on rv6xx+ */ 1652 enum radeon_int_thermal_type int_thermal_type; 1653 struct device *int_hwmon_dev; 1654 /* fan control parameters */ 1655 bool no_fan; 1656 u8 fan_pulses_per_revolution; 1657 u8 fan_min_rpm; 1658 u8 fan_max_rpm; 1659 /* dpm */ 1660 bool dpm_enabled; 1661 bool sysfs_initialized; 1662 struct radeon_dpm dpm; 1663 }; 1664 1665 #define RADEON_PCIE_SPEED_25 1 1666 #define RADEON_PCIE_SPEED_50 2 1667 #define RADEON_PCIE_SPEED_80 4 1668 1669 int radeon_pm_get_type_index(struct radeon_device *rdev, 1670 enum radeon_pm_state_type ps_type, 1671 int instance); 1672 /* 1673 * UVD 1674 */ 1675 #define RADEON_DEFAULT_UVD_HANDLES 10 1676 #define RADEON_MAX_UVD_HANDLES 30 1677 #define RADEON_UVD_STACK_SIZE (200*1024) 1678 #define RADEON_UVD_HEAP_SIZE (256*1024) 1679 #define RADEON_UVD_SESSION_SIZE (50*1024) 1680 1681 struct radeon_uvd { 1682 bool fw_header_present; 1683 struct radeon_bo *vcpu_bo; 1684 void *cpu_addr; 1685 uint64_t gpu_addr; 1686 unsigned max_handles; 1687 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1688 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1689 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1690 struct delayed_work idle_work; 1691 }; 1692 1693 int radeon_uvd_init(struct radeon_device *rdev); 1694 void radeon_uvd_fini(struct radeon_device *rdev); 1695 int radeon_uvd_suspend(struct radeon_device *rdev); 1696 int radeon_uvd_resume(struct radeon_device *rdev); 1697 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1698 uint32_t handle, struct radeon_fence **fence); 1699 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1700 uint32_t handle, struct radeon_fence **fence); 1701 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1702 uint32_t allowed_domains); 1703 void radeon_uvd_free_handles(struct radeon_device *rdev, 1704 struct drm_file *filp); 1705 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1706 void radeon_uvd_note_usage(struct radeon_device *rdev); 1707 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1708 unsigned vclk, unsigned dclk, 1709 unsigned vco_min, unsigned vco_max, 1710 unsigned fb_factor, unsigned fb_mask, 1711 unsigned pd_min, unsigned pd_max, 1712 unsigned pd_even, 1713 unsigned *optimal_fb_div, 1714 unsigned *optimal_vclk_div, 1715 unsigned *optimal_dclk_div); 1716 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1717 unsigned cg_upll_func_cntl); 1718 1719 /* 1720 * VCE 1721 */ 1722 #define RADEON_MAX_VCE_HANDLES 16 1723 1724 struct radeon_vce { 1725 struct radeon_bo *vcpu_bo; 1726 uint64_t gpu_addr; 1727 unsigned fw_version; 1728 unsigned fb_version; 1729 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1730 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1731 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1732 struct delayed_work idle_work; 1733 uint32_t keyselect; 1734 }; 1735 1736 int radeon_vce_init(struct radeon_device *rdev); 1737 void radeon_vce_fini(struct radeon_device *rdev); 1738 int radeon_vce_suspend(struct radeon_device *rdev); 1739 int radeon_vce_resume(struct radeon_device *rdev); 1740 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1741 uint32_t handle, struct radeon_fence **fence); 1742 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1743 uint32_t handle, struct radeon_fence **fence); 1744 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1745 void radeon_vce_note_usage(struct radeon_device *rdev); 1746 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1747 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1748 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1749 struct radeon_ring *ring, 1750 struct radeon_semaphore *semaphore, 1751 bool emit_wait); 1752 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1753 void radeon_vce_fence_emit(struct radeon_device *rdev, 1754 struct radeon_fence *fence); 1755 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1756 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1757 1758 struct r600_audio_pin { 1759 int channels; 1760 int rate; 1761 int bits_per_sample; 1762 u8 status_bits; 1763 u8 category_code; 1764 u32 offset; 1765 bool connected; 1766 u32 id; 1767 }; 1768 1769 struct r600_audio { 1770 bool enabled; 1771 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1772 int num_pins; 1773 struct radeon_audio_funcs *hdmi_funcs; 1774 struct radeon_audio_funcs *dp_funcs; 1775 struct radeon_audio_basic_funcs *funcs; 1776 struct drm_audio_component *component; 1777 bool component_registered; 1778 struct rwlock component_mutex; 1779 }; 1780 1781 /* 1782 * Benchmarking 1783 */ 1784 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1785 1786 1787 /* 1788 * Testing 1789 */ 1790 void radeon_test_moves(struct radeon_device *rdev); 1791 void radeon_test_ring_sync(struct radeon_device *rdev, 1792 struct radeon_ring *cpA, 1793 struct radeon_ring *cpB); 1794 void radeon_test_syncing(struct radeon_device *rdev); 1795 1796 /* 1797 * MMU Notifier 1798 */ 1799 #if defined(CONFIG_MMU_NOTIFIER) 1800 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1801 void radeon_mn_unregister(struct radeon_bo *bo); 1802 #else 1803 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1804 { 1805 return -ENODEV; 1806 } 1807 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1808 #endif 1809 1810 /* 1811 * Debugfs 1812 */ 1813 void radeon_debugfs_fence_init(struct radeon_device *rdev); 1814 void radeon_gem_debugfs_init(struct radeon_device *rdev); 1815 1816 /* 1817 * ASIC ring specific functions. 1818 */ 1819 struct radeon_asic_ring { 1820 /* ring read/write ptr handling */ 1821 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1822 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1823 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1824 1825 /* validating and patching of IBs */ 1826 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1827 int (*cs_parse)(struct radeon_cs_parser *p); 1828 1829 /* command emmit functions */ 1830 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1831 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1832 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1833 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1834 struct radeon_semaphore *semaphore, bool emit_wait); 1835 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1836 unsigned vm_id, uint64_t pd_addr); 1837 1838 /* testing functions */ 1839 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1840 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1841 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1842 1843 /* deprecated */ 1844 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1845 }; 1846 1847 /* 1848 * ASIC specific functions. 1849 */ 1850 struct radeon_asic { 1851 int (*init)(struct radeon_device *rdev); 1852 void (*fini)(struct radeon_device *rdev); 1853 int (*resume)(struct radeon_device *rdev); 1854 int (*suspend)(struct radeon_device *rdev); 1855 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1856 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1857 /* Flush the HDP cache via MMIO */ 1858 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1859 /* check if 3D engine is idle */ 1860 bool (*gui_idle)(struct radeon_device *rdev); 1861 /* wait for mc_idle */ 1862 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1863 /* get the reference clock */ 1864 u32 (*get_xclk)(struct radeon_device *rdev); 1865 /* get the gpu clock counter */ 1866 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1867 /* get register for info ioctl */ 1868 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1869 /* gart */ 1870 struct { 1871 void (*tlb_flush)(struct radeon_device *rdev); 1872 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1873 void (*set_page)(struct radeon_device *rdev, unsigned i, 1874 uint64_t entry); 1875 } gart; 1876 struct { 1877 int (*init)(struct radeon_device *rdev); 1878 void (*fini)(struct radeon_device *rdev); 1879 void (*copy_pages)(struct radeon_device *rdev, 1880 struct radeon_ib *ib, 1881 uint64_t pe, uint64_t src, 1882 unsigned count); 1883 void (*write_pages)(struct radeon_device *rdev, 1884 struct radeon_ib *ib, 1885 uint64_t pe, 1886 uint64_t addr, unsigned count, 1887 uint32_t incr, uint32_t flags); 1888 void (*set_pages)(struct radeon_device *rdev, 1889 struct radeon_ib *ib, 1890 uint64_t pe, 1891 uint64_t addr, unsigned count, 1892 uint32_t incr, uint32_t flags); 1893 void (*pad_ib)(struct radeon_ib *ib); 1894 } vm; 1895 /* ring specific callbacks */ 1896 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1897 /* irqs */ 1898 struct { 1899 int (*set)(struct radeon_device *rdev); 1900 int (*process)(struct radeon_device *rdev); 1901 } irq; 1902 /* displays */ 1903 struct { 1904 /* display watermarks */ 1905 void (*bandwidth_update)(struct radeon_device *rdev); 1906 /* get frame count */ 1907 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1908 /* wait for vblank */ 1909 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1910 /* set backlight level */ 1911 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1912 /* get backlight level */ 1913 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1914 /* audio callbacks */ 1915 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1916 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1917 } display; 1918 /* copy functions for bo handling */ 1919 struct { 1920 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1921 uint64_t src_offset, 1922 uint64_t dst_offset, 1923 unsigned num_gpu_pages, 1924 struct dma_resv *resv); 1925 u32 blit_ring_index; 1926 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1927 uint64_t src_offset, 1928 uint64_t dst_offset, 1929 unsigned num_gpu_pages, 1930 struct dma_resv *resv); 1931 u32 dma_ring_index; 1932 /* method used for bo copy */ 1933 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1934 uint64_t src_offset, 1935 uint64_t dst_offset, 1936 unsigned num_gpu_pages, 1937 struct dma_resv *resv); 1938 /* ring used for bo copies */ 1939 u32 copy_ring_index; 1940 } copy; 1941 /* surfaces */ 1942 struct { 1943 int (*set_reg)(struct radeon_device *rdev, int reg, 1944 uint32_t tiling_flags, uint32_t pitch, 1945 uint32_t offset, uint32_t obj_size); 1946 void (*clear_reg)(struct radeon_device *rdev, int reg); 1947 } surface; 1948 /* hotplug detect */ 1949 struct { 1950 void (*init)(struct radeon_device *rdev); 1951 void (*fini)(struct radeon_device *rdev); 1952 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1953 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1954 } hpd; 1955 /* static power management */ 1956 struct { 1957 void (*misc)(struct radeon_device *rdev); 1958 void (*prepare)(struct radeon_device *rdev); 1959 void (*finish)(struct radeon_device *rdev); 1960 void (*init_profile)(struct radeon_device *rdev); 1961 void (*get_dynpm_state)(struct radeon_device *rdev); 1962 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1963 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1964 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1965 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1966 int (*get_pcie_lanes)(struct radeon_device *rdev); 1967 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1968 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1969 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1970 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1971 int (*get_temperature)(struct radeon_device *rdev); 1972 } pm; 1973 /* dynamic power management */ 1974 struct { 1975 int (*init)(struct radeon_device *rdev); 1976 void (*setup_asic)(struct radeon_device *rdev); 1977 int (*enable)(struct radeon_device *rdev); 1978 int (*late_enable)(struct radeon_device *rdev); 1979 void (*disable)(struct radeon_device *rdev); 1980 int (*pre_set_power_state)(struct radeon_device *rdev); 1981 int (*set_power_state)(struct radeon_device *rdev); 1982 void (*post_set_power_state)(struct radeon_device *rdev); 1983 void (*display_configuration_changed)(struct radeon_device *rdev); 1984 void (*fini)(struct radeon_device *rdev); 1985 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1986 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1987 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1988 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1989 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1990 bool (*vblank_too_short)(struct radeon_device *rdev); 1991 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1992 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1993 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 1994 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 1995 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 1996 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 1997 u32 (*get_current_sclk)(struct radeon_device *rdev); 1998 u32 (*get_current_mclk)(struct radeon_device *rdev); 1999 u16 (*get_current_vddc)(struct radeon_device *rdev); 2000 } dpm; 2001 /* pageflipping */ 2002 struct { 2003 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 2004 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2005 } pflip; 2006 }; 2007 2008 /* 2009 * Asic structures 2010 */ 2011 struct r100_asic { 2012 const unsigned *reg_safe_bm; 2013 unsigned reg_safe_bm_size; 2014 u32 hdp_cntl; 2015 }; 2016 2017 struct r300_asic { 2018 const unsigned *reg_safe_bm; 2019 unsigned reg_safe_bm_size; 2020 u32 resync_scratch; 2021 u32 hdp_cntl; 2022 }; 2023 2024 struct r600_asic { 2025 unsigned max_pipes; 2026 unsigned max_tile_pipes; 2027 unsigned max_simds; 2028 unsigned max_backends; 2029 unsigned max_gprs; 2030 unsigned max_threads; 2031 unsigned max_stack_entries; 2032 unsigned max_hw_contexts; 2033 unsigned max_gs_threads; 2034 unsigned sx_max_export_size; 2035 unsigned sx_max_export_pos_size; 2036 unsigned sx_max_export_smx_size; 2037 unsigned sq_num_cf_insts; 2038 unsigned tiling_nbanks; 2039 unsigned tiling_npipes; 2040 unsigned tiling_group_size; 2041 unsigned tile_config; 2042 unsigned backend_map; 2043 unsigned active_simds; 2044 }; 2045 2046 struct rv770_asic { 2047 unsigned max_pipes; 2048 unsigned max_tile_pipes; 2049 unsigned max_simds; 2050 unsigned max_backends; 2051 unsigned max_gprs; 2052 unsigned max_threads; 2053 unsigned max_stack_entries; 2054 unsigned max_hw_contexts; 2055 unsigned max_gs_threads; 2056 unsigned sx_max_export_size; 2057 unsigned sx_max_export_pos_size; 2058 unsigned sx_max_export_smx_size; 2059 unsigned sq_num_cf_insts; 2060 unsigned sx_num_of_sets; 2061 unsigned sc_prim_fifo_size; 2062 unsigned sc_hiz_tile_fifo_size; 2063 unsigned sc_earlyz_tile_fifo_fize; 2064 unsigned tiling_nbanks; 2065 unsigned tiling_npipes; 2066 unsigned tiling_group_size; 2067 unsigned tile_config; 2068 unsigned backend_map; 2069 unsigned active_simds; 2070 }; 2071 2072 struct evergreen_asic { 2073 unsigned num_ses; 2074 unsigned max_pipes; 2075 unsigned max_tile_pipes; 2076 unsigned max_simds; 2077 unsigned max_backends; 2078 unsigned max_gprs; 2079 unsigned max_threads; 2080 unsigned max_stack_entries; 2081 unsigned max_hw_contexts; 2082 unsigned max_gs_threads; 2083 unsigned sx_max_export_size; 2084 unsigned sx_max_export_pos_size; 2085 unsigned sx_max_export_smx_size; 2086 unsigned sq_num_cf_insts; 2087 unsigned sx_num_of_sets; 2088 unsigned sc_prim_fifo_size; 2089 unsigned sc_hiz_tile_fifo_size; 2090 unsigned sc_earlyz_tile_fifo_size; 2091 unsigned tiling_nbanks; 2092 unsigned tiling_npipes; 2093 unsigned tiling_group_size; 2094 unsigned tile_config; 2095 unsigned backend_map; 2096 unsigned active_simds; 2097 }; 2098 2099 struct cayman_asic { 2100 unsigned max_shader_engines; 2101 unsigned max_pipes_per_simd; 2102 unsigned max_tile_pipes; 2103 unsigned max_simds_per_se; 2104 unsigned max_backends_per_se; 2105 unsigned max_texture_channel_caches; 2106 unsigned max_gprs; 2107 unsigned max_threads; 2108 unsigned max_gs_threads; 2109 unsigned max_stack_entries; 2110 unsigned sx_num_of_sets; 2111 unsigned sx_max_export_size; 2112 unsigned sx_max_export_pos_size; 2113 unsigned sx_max_export_smx_size; 2114 unsigned max_hw_contexts; 2115 unsigned sq_num_cf_insts; 2116 unsigned sc_prim_fifo_size; 2117 unsigned sc_hiz_tile_fifo_size; 2118 unsigned sc_earlyz_tile_fifo_size; 2119 2120 unsigned num_shader_engines; 2121 unsigned num_shader_pipes_per_simd; 2122 unsigned num_tile_pipes; 2123 unsigned num_simds_per_se; 2124 unsigned num_backends_per_se; 2125 unsigned backend_disable_mask_per_asic; 2126 unsigned backend_map; 2127 unsigned num_texture_channel_caches; 2128 unsigned mem_max_burst_length_bytes; 2129 unsigned mem_row_size_in_kb; 2130 unsigned shader_engine_tile_size; 2131 unsigned num_gpus; 2132 unsigned multi_gpu_tile_size; 2133 2134 unsigned tile_config; 2135 unsigned active_simds; 2136 }; 2137 2138 struct si_asic { 2139 unsigned max_shader_engines; 2140 unsigned max_tile_pipes; 2141 unsigned max_cu_per_sh; 2142 unsigned max_sh_per_se; 2143 unsigned max_backends_per_se; 2144 unsigned max_texture_channel_caches; 2145 unsigned max_gprs; 2146 unsigned max_gs_threads; 2147 unsigned max_hw_contexts; 2148 unsigned sc_prim_fifo_size_frontend; 2149 unsigned sc_prim_fifo_size_backend; 2150 unsigned sc_hiz_tile_fifo_size; 2151 unsigned sc_earlyz_tile_fifo_size; 2152 2153 unsigned num_tile_pipes; 2154 unsigned backend_enable_mask; 2155 unsigned backend_disable_mask_per_asic; 2156 unsigned backend_map; 2157 unsigned num_texture_channel_caches; 2158 unsigned mem_max_burst_length_bytes; 2159 unsigned mem_row_size_in_kb; 2160 unsigned shader_engine_tile_size; 2161 unsigned num_gpus; 2162 unsigned multi_gpu_tile_size; 2163 2164 unsigned tile_config; 2165 uint32_t tile_mode_array[32]; 2166 uint32_t active_cus; 2167 }; 2168 2169 struct cik_asic { 2170 unsigned max_shader_engines; 2171 unsigned max_tile_pipes; 2172 unsigned max_cu_per_sh; 2173 unsigned max_sh_per_se; 2174 unsigned max_backends_per_se; 2175 unsigned max_texture_channel_caches; 2176 unsigned max_gprs; 2177 unsigned max_gs_threads; 2178 unsigned max_hw_contexts; 2179 unsigned sc_prim_fifo_size_frontend; 2180 unsigned sc_prim_fifo_size_backend; 2181 unsigned sc_hiz_tile_fifo_size; 2182 unsigned sc_earlyz_tile_fifo_size; 2183 2184 unsigned num_tile_pipes; 2185 unsigned backend_enable_mask; 2186 unsigned backend_disable_mask_per_asic; 2187 unsigned backend_map; 2188 unsigned num_texture_channel_caches; 2189 unsigned mem_max_burst_length_bytes; 2190 unsigned mem_row_size_in_kb; 2191 unsigned shader_engine_tile_size; 2192 unsigned num_gpus; 2193 unsigned multi_gpu_tile_size; 2194 2195 unsigned tile_config; 2196 uint32_t tile_mode_array[32]; 2197 uint32_t macrotile_mode_array[16]; 2198 uint32_t active_cus; 2199 }; 2200 2201 union radeon_asic_config { 2202 struct r300_asic r300; 2203 struct r100_asic r100; 2204 struct r600_asic r600; 2205 struct rv770_asic rv770; 2206 struct evergreen_asic evergreen; 2207 struct cayman_asic cayman; 2208 struct si_asic si; 2209 struct cik_asic cik; 2210 }; 2211 2212 /* 2213 * asic initizalization from radeon_asic.c 2214 */ 2215 void radeon_agp_disable(struct radeon_device *rdev); 2216 int radeon_asic_init(struct radeon_device *rdev); 2217 2218 2219 /* 2220 * IOCTL. 2221 */ 2222 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2223 struct drm_file *filp); 2224 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2225 struct drm_file *filp); 2226 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2227 struct drm_file *filp); 2228 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2229 struct drm_file *file_priv); 2230 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2231 struct drm_file *file_priv); 2232 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2233 struct drm_file *filp); 2234 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2235 struct drm_file *filp); 2236 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2237 struct drm_file *filp); 2238 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2239 struct drm_file *filp); 2240 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2241 struct drm_file *filp); 2242 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2243 struct drm_file *filp); 2244 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2245 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2246 struct drm_file *filp); 2247 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2248 struct drm_file *filp); 2249 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2250 2251 /* VRAM scratch page for HDP bug, default vram page */ 2252 struct r600_vram_scratch { 2253 struct radeon_bo *robj; 2254 volatile uint32_t *ptr; 2255 u64 gpu_addr; 2256 }; 2257 2258 /* 2259 * ACPI 2260 */ 2261 struct radeon_atif_notification_cfg { 2262 bool enabled; 2263 int command_code; 2264 }; 2265 2266 struct radeon_atif_notifications { 2267 bool display_switch; 2268 bool expansion_mode_change; 2269 bool thermal_state; 2270 bool forced_power_state; 2271 bool system_power_state; 2272 bool display_conf_change; 2273 bool px_gfx_switch; 2274 bool brightness_change; 2275 bool dgpu_display_event; 2276 }; 2277 2278 struct radeon_atif_functions { 2279 bool system_params; 2280 bool sbios_requests; 2281 bool select_active_disp; 2282 bool lid_state; 2283 bool get_tv_standard; 2284 bool set_tv_standard; 2285 bool get_panel_expansion_mode; 2286 bool set_panel_expansion_mode; 2287 bool temperature_change; 2288 bool graphics_device_types; 2289 }; 2290 2291 struct radeon_atif { 2292 struct radeon_atif_notifications notifications; 2293 struct radeon_atif_functions functions; 2294 struct radeon_atif_notification_cfg notification_cfg; 2295 struct radeon_encoder *encoder_for_bl; 2296 }; 2297 2298 struct radeon_atcs_functions { 2299 bool get_ext_state; 2300 bool pcie_perf_req; 2301 bool pcie_dev_rdy; 2302 bool pcie_bus_width; 2303 }; 2304 2305 struct radeon_atcs { 2306 struct radeon_atcs_functions functions; 2307 }; 2308 2309 /* 2310 * Core structure, functions and helpers. 2311 */ 2312 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2313 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2314 2315 struct radeon_device { 2316 struct device self; 2317 struct device *dev; 2318 struct drm_device *ddev; 2319 struct pci_dev *pdev; 2320 #ifdef __alpha__ 2321 struct pci_controller *hose; 2322 #endif 2323 struct radeon_agp_head *agp; 2324 struct rwlock exclusive_lock; 2325 2326 pci_chipset_tag_t pc; 2327 pcitag_t pa_tag; 2328 pci_intr_handle_t intrh; 2329 bus_space_tag_t iot; 2330 bus_space_tag_t memt; 2331 bus_dma_tag_t dmat; 2332 void *irqh; 2333 2334 void (*switchcb)(void *, int, int); 2335 void *switchcbarg; 2336 void *switchcookie; 2337 struct task switchtask; 2338 struct rasops_info ro; 2339 int console; 2340 int primary; 2341 2342 struct task burner_task; 2343 int burner_fblank; 2344 2345 #ifdef __sparc64__ 2346 struct sunfb sf; 2347 bus_size_t fb_offset; 2348 bus_space_handle_t memh; 2349 #endif 2350 2351 unsigned long fb_aper_offset; 2352 unsigned long fb_aper_size; 2353 2354 /* ASIC */ 2355 union radeon_asic_config config; 2356 enum radeon_family family; 2357 unsigned long flags; 2358 int usec_timeout; 2359 enum radeon_pll_errata pll_errata; 2360 int num_gb_pipes; 2361 int num_z_pipes; 2362 int disp_priority; 2363 /* BIOS */ 2364 uint8_t *bios; 2365 bool is_atom_bios; 2366 uint16_t bios_header_start; 2367 struct radeon_bo *stolen_vga_memory; 2368 /* Register mmio */ 2369 resource_size_t rmmio_base; 2370 resource_size_t rmmio_size; 2371 /* protects concurrent MM_INDEX/DATA based register access */ 2372 spinlock_t mmio_idx_lock; 2373 /* protects concurrent SMC based register access */ 2374 spinlock_t smc_idx_lock; 2375 /* protects concurrent PLL register access */ 2376 spinlock_t pll_idx_lock; 2377 /* protects concurrent MC register access */ 2378 spinlock_t mc_idx_lock; 2379 /* protects concurrent PCIE register access */ 2380 spinlock_t pcie_idx_lock; 2381 /* protects concurrent PCIE_PORT register access */ 2382 spinlock_t pciep_idx_lock; 2383 /* protects concurrent PIF register access */ 2384 spinlock_t pif_idx_lock; 2385 /* protects concurrent CG register access */ 2386 spinlock_t cg_idx_lock; 2387 /* protects concurrent UVD register access */ 2388 spinlock_t uvd_idx_lock; 2389 /* protects concurrent RCU register access */ 2390 spinlock_t rcu_idx_lock; 2391 /* protects concurrent DIDT register access */ 2392 spinlock_t didt_idx_lock; 2393 /* protects concurrent ENDPOINT (audio) register access */ 2394 spinlock_t end_idx_lock; 2395 bus_space_handle_t rmmio_bsh; 2396 void __iomem *rmmio; 2397 radeon_rreg_t mc_rreg; 2398 radeon_wreg_t mc_wreg; 2399 radeon_rreg_t pll_rreg; 2400 radeon_wreg_t pll_wreg; 2401 uint32_t pcie_reg_mask; 2402 radeon_rreg_t pciep_rreg; 2403 radeon_wreg_t pciep_wreg; 2404 /* io port */ 2405 bus_space_handle_t rio_mem; 2406 resource_size_t rio_mem_size; 2407 struct radeon_clock clock; 2408 struct radeon_mc mc; 2409 struct radeon_gart gart; 2410 struct radeon_mode_info mode_info; 2411 struct radeon_scratch scratch; 2412 struct radeon_doorbell doorbell; 2413 struct radeon_mman mman; 2414 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2415 wait_queue_head_t fence_queue; 2416 u64 fence_context; 2417 struct rwlock ring_lock; 2418 struct radeon_ring ring[RADEON_NUM_RINGS]; 2419 bool ib_pool_ready; 2420 struct radeon_sa_manager ring_tmp_bo; 2421 struct radeon_irq irq; 2422 struct radeon_asic *asic; 2423 struct radeon_gem gem; 2424 struct radeon_pm pm; 2425 struct radeon_uvd uvd; 2426 struct radeon_vce vce; 2427 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2428 struct radeon_wb wb; 2429 struct radeon_dummy_page dummy_page; 2430 bool shutdown; 2431 bool need_swiotlb; 2432 bool accel_working; 2433 bool fastfb_working; /* IGP feature*/ 2434 bool needs_reset, in_reset; 2435 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2436 const struct firmware *me_fw; /* all family ME firmware */ 2437 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2438 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2439 const struct firmware *mc_fw; /* NI MC firmware */ 2440 const struct firmware *ce_fw; /* SI CE firmware */ 2441 const struct firmware *mec_fw; /* CIK MEC firmware */ 2442 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2443 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2444 const struct firmware *smc_fw; /* SMC firmware */ 2445 const struct firmware *uvd_fw; /* UVD firmware */ 2446 const struct firmware *vce_fw; /* VCE firmware */ 2447 bool new_fw; 2448 struct r600_vram_scratch vram_scratch; 2449 int msi_enabled; /* msi enabled */ 2450 struct r600_ih ih; /* r6/700 interrupt ring */ 2451 struct radeon_rlc rlc; 2452 struct radeon_mec mec; 2453 struct delayed_work hotplug_work; 2454 struct work_struct dp_work; 2455 struct work_struct audio_work; 2456 int num_crtc; /* number of crtcs */ 2457 struct rwlock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2458 bool has_uvd; 2459 bool has_vce; 2460 struct r600_audio audio; /* audio stuff */ 2461 struct notifier_block acpi_nb; 2462 /* only one userspace can use Hyperz features or CMASK at a time */ 2463 struct drm_file *hyperz_filp; 2464 struct drm_file *cmask_filp; 2465 /* i2c buses */ 2466 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2467 /* virtual memory */ 2468 struct radeon_vm_manager vm_manager; 2469 struct rwlock gpu_clock_mutex; 2470 /* memory stats */ 2471 atomic64_t num_bytes_moved; 2472 atomic_t gpu_reset_counter; 2473 /* ACPI interface */ 2474 struct radeon_atif atif; 2475 struct radeon_atcs atcs; 2476 /* srbm instance registers */ 2477 struct rwlock srbm_mutex; 2478 /* clock, powergating flags */ 2479 u32 cg_flags; 2480 u32 pg_flags; 2481 2482 struct dev_pm_domain vga_pm_domain; 2483 bool have_disp_power_ref; 2484 u32 px_quirk_flags; 2485 2486 /* tracking pinned memory */ 2487 u64 vram_pin_size; 2488 u64 gart_pin_size; 2489 }; 2490 2491 bool radeon_is_px(struct drm_device *dev); 2492 int radeon_device_init(struct radeon_device *rdev, 2493 struct drm_device *ddev, 2494 struct pci_dev *pdev, 2495 uint32_t flags); 2496 void radeon_device_fini(struct radeon_device *rdev); 2497 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2498 2499 #define RADEON_MIN_MMIO_SIZE 0x10000 2500 2501 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2502 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2503 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2504 bool always_indirect) 2505 { 2506 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2507 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2508 return readl(((void __iomem *)rdev->rmmio) + reg); 2509 else 2510 return r100_mm_rreg_slow(rdev, reg); 2511 } 2512 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2513 bool always_indirect) 2514 { 2515 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2516 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2517 else 2518 r100_mm_wreg_slow(rdev, reg, v); 2519 } 2520 2521 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2522 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2523 2524 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2525 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2526 2527 static inline struct drm_device *rdev_to_drm(struct radeon_device *rdev) 2528 { 2529 return rdev->ddev; 2530 } 2531 2532 /* 2533 * Cast helper 2534 */ 2535 extern const struct dma_fence_ops radeon_fence_ops; 2536 2537 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) 2538 { 2539 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2540 2541 if (__f->base.ops == &radeon_fence_ops) 2542 return __f; 2543 2544 return NULL; 2545 } 2546 2547 /* 2548 * Registers read & write functions. 2549 */ 2550 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2551 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2552 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2553 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2554 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2555 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2556 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ 2557 r100_mm_rreg(rdev, (reg), false)) 2558 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2559 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2560 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2561 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2562 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2563 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2564 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2565 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2566 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2567 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2568 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2569 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2570 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2571 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2572 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2573 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2574 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2575 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2576 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2577 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2578 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2579 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2580 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2581 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2582 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2583 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2584 #define WREG32_P(reg, val, mask) \ 2585 do { \ 2586 uint32_t tmp_ = RREG32(reg); \ 2587 tmp_ &= (mask); \ 2588 tmp_ |= ((val) & ~(mask)); \ 2589 WREG32(reg, tmp_); \ 2590 } while (0) 2591 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2592 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2593 #define WREG32_PLL_P(reg, val, mask) \ 2594 do { \ 2595 uint32_t tmp_ = RREG32_PLL(reg); \ 2596 tmp_ &= (mask); \ 2597 tmp_ |= ((val) & ~(mask)); \ 2598 WREG32_PLL(reg, tmp_); \ 2599 } while (0) 2600 #define WREG32_SMC_P(reg, val, mask) \ 2601 do { \ 2602 uint32_t tmp_ = RREG32_SMC(reg); \ 2603 tmp_ &= (mask); \ 2604 tmp_ |= ((val) & ~(mask)); \ 2605 WREG32_SMC(reg, tmp_); \ 2606 } while (0) 2607 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2608 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2609 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2610 2611 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2612 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2613 2614 /* 2615 * Indirect registers accessors. 2616 * They used to be inlined, but this increases code size by ~65 kbytes. 2617 * Since each performs a pair of MMIO ops 2618 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2619 * the cost of call+ret is almost negligible. MMIO and locking 2620 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2621 */ 2622 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2623 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2624 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2625 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2626 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2627 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2628 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2629 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2630 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2631 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2632 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2633 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2634 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2635 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2636 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2637 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2638 2639 void r100_pll_errata_after_index(struct radeon_device *rdev); 2640 2641 2642 /* 2643 * ASICs helpers. 2644 */ 2645 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2646 (rdev->pdev->device == 0x5969)) 2647 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2648 (rdev->family == CHIP_RV200) || \ 2649 (rdev->family == CHIP_RS100) || \ 2650 (rdev->family == CHIP_RS200) || \ 2651 (rdev->family == CHIP_RV250) || \ 2652 (rdev->family == CHIP_RV280) || \ 2653 (rdev->family == CHIP_RS300)) 2654 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2655 (rdev->family == CHIP_RV350) || \ 2656 (rdev->family == CHIP_R350) || \ 2657 (rdev->family == CHIP_RV380) || \ 2658 (rdev->family == CHIP_R420) || \ 2659 (rdev->family == CHIP_R423) || \ 2660 (rdev->family == CHIP_RV410) || \ 2661 (rdev->family == CHIP_RS400) || \ 2662 (rdev->family == CHIP_RS480)) 2663 #define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \ 2664 (rdev->pdev->device == 0x9443) || \ 2665 (rdev->pdev->device == 0x944B) || \ 2666 (rdev->pdev->device == 0x9506) || \ 2667 (rdev->pdev->device == 0x9509) || \ 2668 (rdev->pdev->device == 0x950F) || \ 2669 (rdev->pdev->device == 0x689C) || \ 2670 (rdev->pdev->device == 0x689D)) 2671 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2672 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2673 (rdev->family == CHIP_RS690) || \ 2674 (rdev->family == CHIP_RS740) || \ 2675 (rdev->family >= CHIP_R600)) 2676 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2677 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2678 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2679 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2680 (rdev->flags & RADEON_IS_IGP)) 2681 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2682 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2683 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2684 (rdev->flags & RADEON_IS_IGP)) 2685 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2686 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2687 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2688 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2689 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2690 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2691 (rdev->family == CHIP_MULLINS)) 2692 2693 #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \ 2694 (rdev->pdev->device == 0x6850) || \ 2695 (rdev->pdev->device == 0x6858) || \ 2696 (rdev->pdev->device == 0x6859) || \ 2697 (rdev->pdev->device == 0x6840) || \ 2698 (rdev->pdev->device == 0x6841) || \ 2699 (rdev->pdev->device == 0x6842) || \ 2700 (rdev->pdev->device == 0x6843)) 2701 2702 /* 2703 * BIOS helpers. 2704 */ 2705 #define RBIOS8(i) (rdev->bios[i]) 2706 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2707 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2708 2709 int radeon_combios_init(struct radeon_device *rdev); 2710 void radeon_combios_fini(struct radeon_device *rdev); 2711 int radeon_atombios_init(struct radeon_device *rdev); 2712 void radeon_atombios_fini(struct radeon_device *rdev); 2713 2714 2715 /* 2716 * RING helpers. 2717 */ 2718 2719 /** 2720 * radeon_ring_write - write a value to the ring 2721 * 2722 * @ring: radeon_ring structure holding ring information 2723 * @v: dword (dw) value to write 2724 * 2725 * Write a value to the requested ring buffer (all asics). 2726 */ 2727 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2728 { 2729 if (ring->count_dw <= 0) 2730 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2731 2732 ring->ring[ring->wptr++] = v; 2733 ring->wptr &= ring->ptr_mask; 2734 ring->count_dw--; 2735 ring->ring_free_dw--; 2736 } 2737 2738 /* 2739 * ASICs macro. 2740 */ 2741 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2742 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2743 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2744 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2745 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2746 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2747 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2748 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2749 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2750 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2751 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2752 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2753 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2754 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2755 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2756 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2757 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2758 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2759 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2760 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2761 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2762 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2763 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2764 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2765 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2766 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2767 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2768 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2769 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2770 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2771 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2772 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2773 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2774 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2775 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2776 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2777 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2778 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2779 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2780 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2781 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2782 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2783 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2784 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2785 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2786 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2787 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2788 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2789 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2790 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2791 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2792 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2793 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2794 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2795 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2796 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2797 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2798 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2799 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2800 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2801 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2802 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2803 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2804 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2805 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2806 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2807 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2808 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2809 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2810 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2811 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2812 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2813 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2814 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2815 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2816 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2817 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2818 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2819 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2820 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2821 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2822 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2823 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2824 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2825 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2826 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2827 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2828 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2829 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2830 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2831 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2832 2833 /* Common functions */ 2834 /* AGP */ 2835 extern int radeon_gpu_reset(struct radeon_device *rdev); 2836 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2837 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2838 extern void radeon_agp_disable(struct radeon_device *rdev); 2839 extern int radeon_modeset_init(struct radeon_device *rdev); 2840 extern void radeon_modeset_fini(struct radeon_device *rdev); 2841 extern bool radeon_card_posted(struct radeon_device *rdev); 2842 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2843 extern void radeon_update_display_priority(struct radeon_device *rdev); 2844 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2845 extern void radeon_scratch_init(struct radeon_device *rdev); 2846 extern void radeon_wb_fini(struct radeon_device *rdev); 2847 extern int radeon_wb_init(struct radeon_device *rdev); 2848 extern void radeon_wb_disable(struct radeon_device *rdev); 2849 extern void radeon_surface_init(struct radeon_device *rdev); 2850 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2851 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2852 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2853 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2854 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2855 extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev, 2856 struct ttm_tt *ttm, uint64_t addr, 2857 uint32_t flags); 2858 extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm); 2859 extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm); 2860 bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm); 2861 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2862 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2863 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2864 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2865 bool fbcon, bool freeze); 2866 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2867 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2868 const u32 *registers, 2869 const u32 array_size); 2870 struct radeon_device *radeon_get_rdev(struct ttm_device *bdev); 2871 2872 /* KMS */ 2873 2874 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc); 2875 int radeon_enable_vblank_kms(struct drm_crtc *crtc); 2876 void radeon_disable_vblank_kms(struct drm_crtc *crtc); 2877 2878 /* 2879 * vm 2880 */ 2881 int radeon_vm_manager_init(struct radeon_device *rdev); 2882 void radeon_vm_manager_fini(struct radeon_device *rdev); 2883 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2884 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2885 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2886 struct radeon_vm *vm, 2887 struct list_head *head); 2888 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2889 struct radeon_vm *vm, int ring); 2890 void radeon_vm_flush(struct radeon_device *rdev, 2891 struct radeon_vm *vm, 2892 int ring, struct radeon_fence *fence); 2893 void radeon_vm_fence(struct radeon_device *rdev, 2894 struct radeon_vm *vm, 2895 struct radeon_fence *fence); 2896 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2897 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2898 struct radeon_vm *vm); 2899 int radeon_vm_clear_freed(struct radeon_device *rdev, 2900 struct radeon_vm *vm); 2901 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2902 struct radeon_vm *vm); 2903 int radeon_vm_bo_update(struct radeon_device *rdev, 2904 struct radeon_bo_va *bo_va, 2905 struct ttm_resource *mem); 2906 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2907 struct radeon_bo *bo); 2908 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2909 struct radeon_bo *bo); 2910 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2911 struct radeon_vm *vm, 2912 struct radeon_bo *bo); 2913 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2914 struct radeon_bo_va *bo_va, 2915 uint64_t offset, 2916 uint32_t flags); 2917 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2918 struct radeon_bo_va *bo_va); 2919 2920 /* audio */ 2921 void r600_audio_update_hdmi(struct work_struct *work); 2922 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2923 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2924 void r600_audio_enable(struct radeon_device *rdev, 2925 struct r600_audio_pin *pin, 2926 u8 enable_mask); 2927 void dce6_audio_enable(struct radeon_device *rdev, 2928 struct r600_audio_pin *pin, 2929 u8 enable_mask); 2930 2931 /* 2932 * R600 vram scratch functions 2933 */ 2934 int r600_vram_scratch_init(struct radeon_device *rdev); 2935 void r600_vram_scratch_fini(struct radeon_device *rdev); 2936 2937 /* 2938 * r600 cs checking helper 2939 */ 2940 unsigned r600_mip_minify(unsigned size, unsigned level); 2941 bool r600_fmt_is_valid_color(u32 format); 2942 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2943 int r600_fmt_get_blocksize(u32 format); 2944 int r600_fmt_get_nblocksx(u32 format, u32 w); 2945 int r600_fmt_get_nblocksy(u32 format, u32 h); 2946 2947 /* 2948 * r600 functions used by radeon_encoder.c 2949 */ 2950 struct radeon_hdmi_acr { 2951 u32 clock; 2952 2953 int n_32khz; 2954 int cts_32khz; 2955 2956 int n_44_1khz; 2957 int cts_44_1khz; 2958 2959 int n_48khz; 2960 int cts_48khz; 2961 2962 }; 2963 2964 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2965 u32 tiling_pipe_num, 2966 u32 max_rb_num, 2967 u32 total_max_rb_num, 2968 u32 enabled_rb_mask); 2969 2970 /* 2971 * evergreen functions used by radeon_encoder.c 2972 */ 2973 2974 extern int ni_init_microcode(struct radeon_device *rdev); 2975 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2976 2977 /* radeon_acpi.c */ 2978 #if defined(CONFIG_ACPI) 2979 extern int radeon_acpi_init(struct radeon_device *rdev); 2980 extern void radeon_acpi_fini(struct radeon_device *rdev); 2981 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2982 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2983 u8 perf_req, bool advertise); 2984 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2985 #else 2986 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2987 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2988 #endif 2989 2990 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2991 struct radeon_cs_packet *pkt, 2992 unsigned idx); 2993 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2994 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2995 struct radeon_cs_packet *pkt); 2996 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2997 struct radeon_bo_list **cs_reloc, 2998 int nomm); 2999 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3000 uint32_t *vline_start_end, 3001 uint32_t *vline_status); 3002 3003 /* interrupt control register helpers */ 3004 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, 3005 u32 reg, u32 mask, 3006 bool enable, const char *name, 3007 unsigned n); 3008 3009 /* Audio component binding */ 3010 void radeon_audio_component_init(struct radeon_device *rdev); 3011 void radeon_audio_component_fini(struct radeon_device *rdev); 3012 3013 #include "radeon_object.h" 3014 3015 #endif 3016