1 /* $NetBSD: atomic.h,v 1.3 2016/08/09 13:45:45 scole Exp $ */
2
3 /*-
4 * Copyright (c) 1998 Doug Rabson
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: releng/10.1/sys/ia64/include/atomic.h 262004 2014-02-16 23:08:21Z marcel $
29 */
30
31 #ifndef _IA64_ATOMIC_H_
32 #define _IA64_ATOMIC_H_
33
34 /*
35 * Various simple arithmetic on memory which is atomic in the presence
36 * of interrupts and SMP safe.
37 */
38
39 /*
40 * Everything is built out of cmpxchg.
41 */
42 #define IA64_CMPXCHG(sz, sem, p, cmpval, newval, ret) \
43 __asm __volatile ( \
44 "mov ar.ccv=%2;;\n\t" \
45 "cmpxchg" #sz "." #sem " %0=%4,%3,ar.ccv\n\t" \
46 : "=r" (ret), "=m" (*p) \
47 : "r" ((uint64_t)cmpval), "r" (newval), "m" (*p) \
48 : "memory")
49
50 /*
51 * Some common forms of cmpxch.
52 */
53 static __inline uint32_t
ia64_cmpxchg_acq_32(volatile uint32_t * p,uint32_t cmpval,uint32_t newval)54 ia64_cmpxchg_acq_32(volatile uint32_t* p, uint32_t cmpval, uint32_t newval)
55 {
56 uint32_t ret;
57 IA64_CMPXCHG(4, acq, p, cmpval, newval, ret);
58 return (ret);
59 }
60
61 static __inline uint32_t
ia64_cmpxchg_rel_32(volatile uint32_t * p,uint32_t cmpval,uint32_t newval)62 ia64_cmpxchg_rel_32(volatile uint32_t* p, uint32_t cmpval, uint32_t newval)
63 {
64 uint32_t ret;
65 IA64_CMPXCHG(4, rel, p, cmpval, newval, ret);
66 return (ret);
67 }
68
69 static __inline uint64_t
ia64_cmpxchg_acq_64(volatile uint64_t * p,uint64_t cmpval,uint64_t newval)70 ia64_cmpxchg_acq_64(volatile uint64_t* p, uint64_t cmpval, uint64_t newval)
71 {
72 uint64_t ret;
73 IA64_CMPXCHG(8, acq, p, cmpval, newval, ret);
74 return (ret);
75 }
76
77 static __inline uint64_t
ia64_cmpxchg_rel_64(volatile uint64_t * p,uint64_t cmpval,uint64_t newval)78 ia64_cmpxchg_rel_64(volatile uint64_t* p, uint64_t cmpval, uint64_t newval)
79 {
80 uint64_t ret;
81 IA64_CMPXCHG(8, rel, p, cmpval, newval, ret);
82 return (ret);
83 }
84
85 #define ATOMIC_STORE_LOAD(type, width, size) \
86 static __inline uint##width##_t \
87 ia64_ld_acq_##width(volatile uint##width##_t* p) \
88 { \
89 uint##width##_t v; \
90 __asm __volatile ("ld" size ".acq %0=%1" : "=r" (v) \
91 : "m" (*p) : "memory"); \
92 return (v); \
93 } \
94 \
95 static __inline uint##width##_t \
96 atomic_load_acq_##width(volatile uint##width##_t* p) \
97 { \
98 uint##width##_t v; \
99 __asm __volatile ("ld" size ".acq %0=%1" : "=r" (v) \
100 : "m" (*p) : "memory"); \
101 return (v); \
102 } \
103 \
104 static __inline uint##width##_t \
105 atomic_load_acq_##type(volatile uint##width##_t* p) \
106 { \
107 uint##width##_t v; \
108 __asm __volatile ("ld" size ".acq %0=%1" : "=r" (v) \
109 : "m" (*p) : "memory"); \
110 return (v); \
111 } \
112 \
113 static __inline void \
114 ia64_st_rel_##width(volatile uint##width##_t* p, uint##width##_t v) \
115 { \
116 __asm __volatile ("st" size ".rel %0=%1" : "=m" (*p) \
117 : "r" (v) : "memory"); \
118 } \
119 \
120 static __inline void \
121 atomic_store_rel_##width(volatile uint##width##_t* p, \
122 uint##width##_t v) \
123 { \
124 __asm __volatile ("st" size ".rel %0=%1" : "=m" (*p) \
125 : "r" (v) : "memory"); \
126 } \
127 \
128 static __inline void \
129 atomic_store_rel_##type(volatile uint##width##_t* p, \
130 uint##width##_t v) \
131 { \
132 __asm __volatile ("st" size ".rel %0=%1" : "=m" (*p) \
133 : "r" (v) : "memory"); \
134 }
135
136 ATOMIC_STORE_LOAD(char, 8, "1")
137 ATOMIC_STORE_LOAD(short, 16, "2")
138 ATOMIC_STORE_LOAD(int, 32, "4")
139 ATOMIC_STORE_LOAD(long, 64, "8")
140
141 #undef ATOMIC_STORE_LOAD
142
143 #define atomic_load_acq_ptr(p) \
144 ((void *)atomic_load_acq_64((volatile uint64_t *)p))
145
146 #define atomic_store_rel_ptr(p, v) \
147 atomic_store_rel_64((volatile uint64_t *)p, (uint64_t)v)
148
149 #define IA64_ATOMIC(sz, type, name, width, op) \
150 static __inline type \
151 atomic_##name##_acq_##width(volatile type *p, type v) \
152 { \
153 type old, ret; \
154 do { \
155 old = *p; \
156 IA64_CMPXCHG(sz, acq, p, old, old op v, ret); \
157 } while (ret != old); \
158 return (old); \
159 } \
160 \
161 static __inline type \
162 atomic_##name##_rel_##width(volatile type *p, type v) \
163 { \
164 type old, ret; \
165 do { \
166 old = *p; \
167 IA64_CMPXCHG(sz, rel, p, old, old op v, ret); \
168 } while (ret != old); \
169 return (old); \
170 }
171
172 IA64_ATOMIC(1, uint8_t, set, 8, |)
173 IA64_ATOMIC(2, uint16_t, set, 16, |)
174 IA64_ATOMIC(4, uint32_t, set, 32, |)
175 IA64_ATOMIC(8, uint64_t, set, 64, |)
176
177 IA64_ATOMIC(1, uint8_t, clear, 8, &~)
178 IA64_ATOMIC(2, uint16_t, clear, 16, &~)
179 IA64_ATOMIC(4, uint32_t, clear, 32, &~)
180 IA64_ATOMIC(8, uint64_t, clear, 64, &~)
181
182 IA64_ATOMIC(1, uint8_t, add, 8, +)
183 IA64_ATOMIC(2, uint16_t, add, 16, +)
184 IA64_ATOMIC(4, uint32_t, add, 32, +)
185 IA64_ATOMIC(8, uint64_t, add, 64, +)
186
187 IA64_ATOMIC(1, uint8_t, subtract, 8, -)
188 IA64_ATOMIC(2, uint16_t, subtract, 16, -)
189 IA64_ATOMIC(4, uint32_t, subtract, 32, -)
190 IA64_ATOMIC(8, uint64_t, subtract, 64, -)
191
192 #undef IA64_ATOMIC
193
194 #define atomic_set_8 atomic_set_acq_8
195 #define atomic_clear_8 atomic_clear_acq_8
196 #define atomic_add_8 atomic_add_acq_8
197 #define atomic_subtract_8 atomic_subtract_acq_8
198
199 #define atomic_set_16 atomic_set_acq_16
200 #define atomic_clear_16 atomic_clear_acq_16
201 #define atomic_add_16 atomic_add_acq_16
202 #define atomic_subtract_16 atomic_subtract_acq_16
203
204 #define atomic_set_32 atomic_set_acq_32
205 #define atomic_clear_32 atomic_clear_acq_32
206 #define atomic_add_32 atomic_add_acq_32
207 #define atomic_subtract_32 atomic_subtract_acq_32
208
209 #define atomic_set_64 atomic_set_acq_64
210 #define atomic_clear_64 atomic_clear_acq_64
211 #define atomic_add_64 atomic_add_acq_64
212 #define atomic_subtract_64 atomic_subtract_acq_64
213
214 #define atomic_set_char atomic_set_8
215 #define atomic_clear_char atomic_clear_8
216 #define atomic_add_char atomic_add_8
217 #define atomic_subtract_char atomic_subtract_8
218 #define atomic_set_acq_char atomic_set_acq_8
219 #define atomic_clear_acq_char atomic_clear_acq_8
220 #define atomic_add_acq_char atomic_add_acq_8
221 #define atomic_subtract_acq_char atomic_subtract_acq_8
222 #define atomic_set_rel_char atomic_set_rel_8
223 #define atomic_clear_rel_char atomic_clear_rel_8
224 #define atomic_add_rel_char atomic_add_rel_8
225 #define atomic_subtract_rel_char atomic_subtract_rel_8
226
227 #define atomic_set_short atomic_set_16
228 #define atomic_clear_short atomic_clear_16
229 #define atomic_add_short atomic_add_16
230 #define atomic_subtract_short atomic_subtract_16
231 #define atomic_set_acq_short atomic_set_acq_16
232 #define atomic_clear_acq_short atomic_clear_acq_16
233 #define atomic_add_acq_short atomic_add_acq_16
234 #define atomic_subtract_acq_short atomic_subtract_acq_16
235 #define atomic_set_rel_short atomic_set_rel_16
236 #define atomic_clear_rel_short atomic_clear_rel_16
237 #define atomic_add_rel_short atomic_add_rel_16
238 #define atomic_subtract_rel_short atomic_subtract_rel_16
239
240 #define atomic_set_int atomic_set_32
241 #define atomic_clear_int atomic_clear_32
242 #define atomic_add_int atomic_add_32
243 #define atomic_subtract_int atomic_subtract_32
244 #define atomic_set_acq_int atomic_set_acq_32
245 #define atomic_clear_acq_int atomic_clear_acq_32
246 #define atomic_add_acq_int atomic_add_acq_32
247 #define atomic_subtract_acq_int atomic_subtract_acq_32
248 #define atomic_set_rel_int atomic_set_rel_32
249 #define atomic_clear_rel_int atomic_clear_rel_32
250 #define atomic_add_rel_int atomic_add_rel_32
251 #define atomic_subtract_rel_int atomic_subtract_rel_32
252
253 #define atomic_set_long atomic_set_64
254 #define atomic_clear_long atomic_clear_64
255 #define atomic_add_long atomic_add_64
256 #define atomic_subtract_long atomic_subtract_64
257 #define atomic_set_acq_long atomic_set_acq_64
258 #define atomic_clear_acq_long atomic_clear_acq_64
259 #define atomic_add_acq_long atomic_add_acq_64
260 #define atomic_subtract_acq_long atomic_subtract_acq_64
261 #define atomic_set_rel_long atomic_set_rel_64
262 #define atomic_clear_rel_long atomic_clear_rel_64
263 #define atomic_add_rel_long atomic_add_rel_64
264 #define atomic_subtract_rel_long atomic_subtract_rel_64
265
266 /* XXX Needs casting. */
267 #define atomic_set_ptr atomic_set_64
268 #define atomic_clear_ptr atomic_clear_64
269 #define atomic_add_ptr atomic_add_64
270 #define atomic_subtract_ptr atomic_subtract_64
271 #define atomic_set_acq_ptr atomic_set_acq_64
272 #define atomic_clear_acq_ptr atomic_clear_acq_64
273 #define atomic_add_acq_ptr atomic_add_acq_64
274 #define atomic_subtract_acq_ptr atomic_subtract_acq_64
275 #define atomic_set_rel_ptr atomic_set_rel_64
276 #define atomic_clear_rel_ptr atomic_clear_rel_64
277 #define atomic_add_rel_ptr atomic_add_rel_64
278 #define atomic_subtract_rel_ptr atomic_subtract_rel_64
279
280 #undef IA64_CMPXCHG
281
282 /*
283 * Atomically compare the value stored at *p with cmpval and if the
284 * two values are equal, update the value of *p with newval. Returns
285 * zero if the compare failed, nonzero otherwise.
286 */
287 static __inline int
atomic_cmpset_acq_32(volatile uint32_t * p,uint32_t cmpval,uint32_t newval)288 atomic_cmpset_acq_32(volatile uint32_t* p, uint32_t cmpval, uint32_t newval)
289 {
290 return (ia64_cmpxchg_acq_32(p, cmpval, newval) == cmpval);
291 }
292
293 static __inline int
atomic_cmpset_rel_32(volatile uint32_t * p,uint32_t cmpval,uint32_t newval)294 atomic_cmpset_rel_32(volatile uint32_t* p, uint32_t cmpval, uint32_t newval)
295 {
296 return (ia64_cmpxchg_rel_32(p, cmpval, newval) == cmpval);
297 }
298
299 /*
300 * Atomically compare the value stored at *p with cmpval and if the
301 * two values are equal, update the value of *p with newval. Returns
302 * zero if the compare failed, nonzero otherwise.
303 */
304 static __inline int
atomic_cmpset_acq_64(volatile uint64_t * p,uint64_t cmpval,uint64_t newval)305 atomic_cmpset_acq_64(volatile uint64_t* p, uint64_t cmpval, uint64_t newval)
306 {
307 return (ia64_cmpxchg_acq_64(p, cmpval, newval) == cmpval);
308 }
309
310 static __inline int
atomic_cmpset_rel_64(volatile uint64_t * p,uint64_t cmpval,uint64_t newval)311 atomic_cmpset_rel_64(volatile uint64_t* p, uint64_t cmpval, uint64_t newval)
312 {
313 return (ia64_cmpxchg_rel_64(p, cmpval, newval) == cmpval);
314 }
315
316 #define atomic_cmpset_32 atomic_cmpset_acq_32
317 #define atomic_cmpset_64 atomic_cmpset_acq_64
318 #define atomic_cmpset_int atomic_cmpset_32
319 #define atomic_cmpset_long atomic_cmpset_64
320 #define atomic_cmpset_acq_int atomic_cmpset_acq_32
321 #define atomic_cmpset_rel_int atomic_cmpset_rel_32
322 #define atomic_cmpset_acq_long atomic_cmpset_acq_64
323 #define atomic_cmpset_rel_long atomic_cmpset_rel_64
324
325 #define atomic_cmpset_acq_ptr(p, o, n) \
326 (atomic_cmpset_acq_64((volatile uint64_t *)p, (uint64_t)o, (uint64_t)n))
327
328 #define atomic_cmpset_ptr atomic_cmpset_acq_ptr
329
330 #define atomic_cmpset_rel_ptr(p, o, n) \
331 (atomic_cmpset_rel_64((volatile uint64_t *)p, (uint64_t)o, (uint64_t)n))
332
333 static __inline uint32_t
atomic_readandclear_32(volatile uint32_t * p)334 atomic_readandclear_32(volatile uint32_t* p)
335 {
336 uint32_t val;
337 do {
338 val = *p;
339 } while (!atomic_cmpset_32(p, val, 0));
340 return (val);
341 }
342
343 static __inline uint64_t
atomic_readandclear_64(volatile uint64_t * p)344 atomic_readandclear_64(volatile uint64_t* p)
345 {
346 uint64_t val;
347 do {
348 val = *p;
349 } while (!atomic_cmpset_64(p, val, 0));
350 return (val);
351 }
352
353 #define atomic_readandclear_int atomic_readandclear_32
354 #define atomic_readandclear_long atomic_readandclear_64
355 #define atomic_readandclear_ptr atomic_readandclear_64
356
357 /*
358 * Atomically add the value of v to the integer pointed to by p and return
359 * the previous value of *p.
360 *
361 * XXX: Should we use the fetchadd instruction here?
362 */
363 static __inline uint32_t
atomic_fetchadd_32(volatile uint32_t * p,uint32_t v)364 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
365 {
366 uint32_t value;
367
368 do {
369 value = *p;
370 } while (!atomic_cmpset_32(p, value, value + v));
371 return (value);
372 }
373
374 #define atomic_fetchadd_int atomic_fetchadd_32
375
376 static __inline u_long
atomic_fetchadd_long(volatile u_long * p,u_long v)377 atomic_fetchadd_long(volatile u_long *p, u_long v)
378 {
379 u_long value;
380
381 do {
382 value = *p;
383 } while (!atomic_cmpset_64(p, value, value + v));
384 return (value);
385 }
386
387 /*
388 * <type> atomic_swap_<type>(volatile <type> *p, <type> v);
389 */
390
391 static __inline uint32_t
ia64_atomic_swap_32(volatile uint32_t * p,uint32_t v)392 ia64_atomic_swap_32(volatile uint32_t *p, uint32_t v)
393 {
394 uint32_t r;
395
396 __asm __volatile ("xchg4 %0 = %3, %2;;" : "=r"(r), "=m"(*p) :
397 "r"(v), "m"(*p) : "memory");
398 return (r);
399 }
400
401 static __inline uint64_t
ia64_atomic_swap_64(volatile uint64_t * p,uint64_t v)402 ia64_atomic_swap_64(volatile uint64_t *p, uint64_t v)
403 {
404 uint64_t r;
405
406 __asm __volatile ("xchg8 %0 = %3, %2;;" : "=r"(r), "=m"(*p) :
407 "r"(v), "m"(*p) : "memory");
408 return (r);
409 }
410
411 #define ia64_atomic_swap_int ia64_atomic_swap_32
412 #define ia64_atomic_swap_long ia64_atomic_swap_64
413 #define ia64_atomic_swap_ptr ia64_atomic_swap_64
414
415 #endif /* ! _IA64_ATOMIC_H_ */
416